DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT137
3-to-8 line decoder/demultiplexer
with address latches; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
FEATURES
•Combines 3-to-8 decoder with 3-bit latch
•Multiple input enable for easy expansion or independent
controls
•Active LOW mutually exclusive outputs
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT137 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers
with latches at the three address inputs (An). The “137”
essentially combines the 3-to-8 decoder function with a
3-bit storage latch. When the latch is enabled (LE = LOW),
the “137” acts as a 3-to-8 active LOW decoder. When the
latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the
latches. Further address changes are ignored as long as
LE remains HIGH.
The output enable input (E1 and E2) controls the state of
the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E2
is HIGH.
The “137” is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed
(stored address) applications in bus oriented systems.
QUICK REFERENCE DATA
GND = 0 V; Tamb=25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC =5 V
A
n
to Yn18 19 ns
LE to Yn17 21 ns
E1 to Yn15 17 ns
E2 to Yn15 15 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 57 59 pF
December 1990 3
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A0 to A2data inputs
4LE latch enable input (active LOW)
5E1data enable input (active LOW)
6E
2data enable input (active HIGH)
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7multiplexer outputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol.
Fig.3 IEC logic symbol. Fig.4 Functional diagram.
December 1990 4
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
LE E1E2A0A1A2Y0Y1Y2Y3Y4Y5Y6Y7
H L H X X X stable
X
XH
XX
LX
XX
XX
XH
HH
HH
HH
HH
HH
HH
HH
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
Fig.5 Logic diagram.
December 1990 5
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Yn
58
21
17
180
36
31
225
45
38
270
54
46 ns 2.0
4.5
6.0 Fig.6
tPHL/ tPLH propagation delay
LE to Yn
55
20
16
190
38
32
240
48
41
285
57
48 ns 2.0
4.5
6.0 Fig.7
tPHL/ tPLH propagation delay
E1 to Yn
50
18
14
145
29
25
180
36
31
220
44
38 ns 2.0
4.5
6.0 Fig.7
tPHL/ tPLH propagation delay
E2 to Yn
50
18
14
145
29
25
180
36
31
220
44
38 ns 2.0
4.5
6.0 Fig.6
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0 Fig.6
tWLE pulse width
HIGH
50
10
9
11
4
3
65
13
11
75
15
13 ns 2.0
4.5
6.0 Fig.8
tsu set-up time
An to LE
50
10
9
3
1
1
65
13
11
75
15
13 ns 2.0
4.5
6.0 Fig.8
thhold time
An to LE
30
6
5
3
1
1
40
8
7
45
9
8ns 2.0
4.5
6.0 Fig.8
December 1990 6
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
An1.50
E11.50
E21.50
LE 1.50
SYMBO L PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Yn22 38 48 57 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
LE to Yn25 44 55 66 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
E1 to Yn20 37 46 56 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
E2 to Yn18 35 44 53 ns 4.5 Fig.6
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
tWLE pulse width
HIGH 10 5 13 15 ns 4.5 Fig.8
tsu set-up time
An to LE 10 2 13 15 ns 4.5 Fig.8
thhold time
An to LE 7 2 9 11 ns 4.5 Fig.8
December 1990 7
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
AC WAVEFORMS
Fig.6 Waveforms showing the address input (An) and
enable inputs (E2) to output (Yn) propagation
delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the enable input (E1, LE)
to output (Yn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the data set-up, hold times for An input to LE input and the latch enable pulse width.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
APPLICATION INFORMATION
Fig.9 6-to-64 line decoder with input address storage.
December 1990 8
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer with
address latches; inverting 74HC/HCT137
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Philips Semiconductors - PIP - 74HC/HCT137; 3-to-8 line decoder/demultiplexer with address latches; inverting
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Product Information
74HC/HCT137; 3-to-8
line
decoder/demultiplexer
with address latches;
inverting
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General description
The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT137 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The '137'
essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW),
the '137' acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data
present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE
remains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch
operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The '137' is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address)
applications in bus oriented systems.
top
Features
● Combines 3-to-8 decoder with 3-bit latch
● Multiple input enable for easy expansion or independent controls
● Active LOW mutually exclusive outputs
● Output capability: standard
● ICC category: MSI
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Datasheet
Type number Title Publication
release date Datasheet status Page
count File
size
(kB)
Datasheet
74HC/HCT137 3-to-8 line
decoder/demultiplexer with
address latches; inverting
12/1/1990 Product
specification 8 66
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PDF
File
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Additional datasheet info
To complete the device datasheet with package and family information, also download the following PDF files. The
"Logic Package Information" document is required to determine in which package(s) this device is available.
Document Description
1
Download
PDF
File
HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic
Family Specifications
2
Download
PDF
File
HCT_PACKAGE_INFO HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic Package
Information
3
Download
PDF
File
HCT_PACKAGE_OUTLINES HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic Package
Outlines
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Parametrics
Type
number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74HC137D SOT109
(SO16)
3-to-8 Line
Decoder/Demultiplexer
with Address Latches;
Inverting
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HC137DB SOT338-
1
(SSOP16)
3-to-8 Line
Decoder/Demultiplexer
with Address Latches;
Inverting
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HC137N SOT38-1
(DIP16)
3-to-8 Line
Decoder/Demultiplexer
with Address Latches;
Inverting
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HCT137D SOT109-
1 (SO16)
3-to-8 Line
Decoder/Demultiplexer
with Address Latches;
Inverting; TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
74HCT137N SOT38-1
(DIP16)
3-to-8 Line
Decoder/Demultiplexer
with Address Latches;
Inverting; TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
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Products, packages, availability and ordering
Type number North
American
type number
Ordering code
(12NC) Marking/Packing
Download
PDF
File
Discretes packing
info
Package Device status Buy online
74HC137D 74HC137D 9337 570 70652 Standard Marking *
Bulk Pack, CECC SOT109
(SO16) Full production
-
74HC137D-T 9337 570 70653 Standard Marking *
Reel Pack, SMD,
13", CECC
SOT109
(SO16) Full production
-
74HC137DB 74HC137DB 9351 896 60112 Standard Marking *
Bulk Pack SOT338-1
(SSOP16) Full production
-
74HC137DB-
T 9351 896 60118 Standard Marking *
Reel Pack, SMD,
13"
SOT338-1
(SSOP16) Full production
-
74HC137N 74HC137N 9337 570 60652 Standard Marking *
Bulk Pack, CECC SOT38-1
(DIP16) Full production
-
74HCT137D 74HCT137D 9337 570 90652 Standard Marking *
Bulk Pack, CECC SOT109-1
(SO16) Full production
-
74HCT137D-
T 9337 570 90653 Standard Marking *
Reel Pack, SMD,
13", CECC
SOT109-1
(SO16) Full production
-
74HCT137N 74HCT137N 9337 570 80652 Standard Marking *
Bulk Pack, CECC SOT38-1
(DIP16) Full production
-
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
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Products
similar
to
74HC/HCT137
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or related to the type number(s) as listed on this page. The similar products page includes products from the same
catalog tree(s), relevant selection guides and products from the same functional category.
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Support & tools
Download
PDF
File
HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 01-Mar-98)
Download
PDF
File
HC/T User Guide(date 01-Nov-97)
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