High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
1 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date
2.0 Initial issue with new naming rule Feb.15, 2005
2.1
2.2
2.3
Add 48CSP-6x8mm package outline
Revise 48CSP-8x10mm pkg code from W to K
Revised DC characteristics
Mar. 08, 2005
Oct. 25, 2005
Nov. 23, 2006
2.4 Revised DC characteristics Jun. 20,2007
2.5 Change wafer process from 0.18um to 0.15um May. 19, 2008
2.6 Add CE2 description of 48BGA package Nov. 20, 2009
2.7 Modify Data Retention waveform May. 27.2010
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
2 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
PRODUCT DESCRIPTION
The CS16LV81923 is a high performance, high speed, low power CMOS Static Random
Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7 to
3.6V supply voltage. Advanced 0.15um CMOS technology and circuit techniques provide both high
speed and low power features with a Typical CMOS standby current of 0.3uA and maximum access
time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip
enable1 (/CE), active HIGH chip enable2 (CE2) for BGA product and active LOW output enable
(/OE) and three-state output drivers.
The CS16LV81923 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS16LV81923 is available in JEDEC standard 44L TSOP
2 and 48Ball Mini_BGA 8x10mm packages.
FEATURES
Low operation voltage: 2.7 ~ 3.6V
Ultra low power consumption:
Vcc = 3.0V: 25mA (Typ.) operating current, 0.3uA (Typ.) CMOS standby current
High speed access time: 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE&CE2 and /OE options.
PRODUCT FAMILY
Product Family
Operating
Temp Vcc. Range
Speed (ns)
Standby
Current
(Typ.) Package Type
0 ~ 70
o
C 0.3 uA
(V
CC
= 3.0V)
CS16LV81923
-40 ~ 85
o
C
2.7 ~ 3.6 55/70
0.3 uA
(V
CC
= 3.0V)
44 TSOP 2-400mil
48 Mini_BGA 8x10mm
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
3 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
■
FUNCTIONAL BLOCK DIAGRAM
For single CE product of 44 TSOP 2-400mil
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
4 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
For dual CE product of 48 Mini_BGA 8x10mm
PIN DESCRIPTIONS
Name Type Function
A0 ~ A18 Input 19 address inputs for selecting one of the 524,288 x 16 bit words in the RAM
/CE
/CE1 & CE2
Input
/CE1 is active LOW and CE2 is active high. Chip enable must be active when
data read from or write to the device. If chip enable is not active, the device is
deselected and in a standby power mode. The DQ pins will be in high
impedance state when the device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will be
present on the DQ pins, when /WE is LOW, the data present on the DQ pins
will be written into the selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the DQ
pins and they will be enabled. The DQ pins will be in the high impedance state
when /OE is inactive.
/LB and /UB
Input Lower byte and upper byte data input/output control pins.
DQ0~DQ15 I/O These 16 bi-directional ports are used to read data from or write data into the
RAM.
Vcc Power
Power Supply
Vss Power
Ground
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
5 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
TRUTH TABLE
MODE /CE
(1)
/CE1
(2)
CE2
(2)
/WE
/OE
/LB
/UB
DQ0~7 DQ8~15 Vcc Current
H H X X X X X High Z High Z I
CCSB
, I
CCSB1
Fully
Standby X X L X X X X High Z High Z I
CCSB
, I
CCSB1
Output
Disabled L L H H H X X High Z High Z I
CC
L L D
OUT
D
OUT
I
CC
H L High Z D
OUT
I
CC
Read L L H H L
L H D
OUT
High Z I
CC
L L D
IN
D
IN
I
CC
H L High Z D
IN
I
CC
Write L L H L X
L H D
IN
High-Z I
CC
Note: (1) /CE is used for 44 TSOP 2-400mil of single CE product only.
(2) /CE1 and CE2 are used for 48 Mini_BGA 8x10mm dual CE product only.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Rating Unit
V
TERM
Terminal Voltage with Respect to GND -0.2 to Vcc+0.5 V
T
BIAS
Temperature Under Bias -40 to +125
O
C
T
STG
Storage Temperature -60 to +150
O
C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 35 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
6 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
DC ELECTRICAL CHARACTERISTICS (
TA = 0~+70
o
C / -40
0
C~+85
0
C ,V
CC
= 3.0V)
Parameter
Name Parameter Test Conduction MIN
TYP
(1)
MAX Unit
V
IL
Guaranteed Input Low
Voltage
(2)
-0.2
(2)
0.6 V
V
IH
Guaranteed Input High
Voltage
(2)
2.2 Vcc+0.2
(2)
V
I
IL
Input Leakage Current V
CC
=MAX, V
IN
=0 to V
CC
-1 1 uA
I
OL
Output Leakage Current V
CC
=MAX, /CE=V
IH
, or
/OE=V
IH
, V
IO
=0V to V
CC
-1 1 uA
V
OL
Output Low Voltage V
CC
=MAX, I
OL
= 2 mA 0.4 V
V
OH
Output High Voltage V
CC
=MIN, I
OH
= -1mA 2.4 V
I
CC
Operating Power Supply
Current /CE=V
IL
, I
DQ
=0mA,
F=F
MAX(3)
25 35 mA
I
CCSB
Standby Supply -TTL /CE=V
IH
, I
DQ
=0mA, 0.5 mA
I
CCSB1
Standby Current-CMOS /CE V≧
CC
-0.2V,
V
IN
V≧
CC
-0.2V or
V
IN
0.2V≦ 0.3 6 uA
1. Typical characteristics are at TA = 25
o
C.
2. Overshoot: Vcc+2.0V in case of pulse width 20ns. Undershoot: ≦-2.0V in case of pulse width 20ns.≦
Overshoot and undershoot are sampled, not 100% tested.
3. Fmax = 1/t
RC
.
OPERATING RANGE
Range Ambient Temperature V
CC
Commercial 0~70
o
C 2.7V ~ 3.6V
Industrial -40~85
o
C 2.7V ~ 3.6V
CAPACITANCE
(1)
(TA = 25
o
C, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
C
IN
Input Capacitance V
IN
=0V 8 pF
C
DQ
Input/Output Capacitance V
I/O
=0V 10 pF
1. This parameter is guaranteed and not 100% tested.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
7 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
DATA RETENTION CHARACTERISTICS (
TA = 0~+70
o
C / -40
0
C~+85
0
C )
Parameter
Name Parameter Test Conduction MIN TYP
(1)
MAX Unit
V
DR
V
CC
for Data Retention
/CE V≧
CC
-0.2V, V
IN
V≧
CC
-0.2V
or V
IN
0.2V≦ 1.5 V
I
CCDR
Data Retention Current
/CE V≧
CC
-0.2V, V
CC
=1.5V
V
IN
V≧
CC
-0.2V or V
IN
0.2V≦ 0.1 3 uA
t
SDR
Chip Deselect to Data
Retention Time 0 ns
t
RDR
Operation Recovery
Time
See Retention Waveform
t
RC
(2)
ns
1. V
CC
= 3.0V, TA = +25
o
C
2. t
RC
(2)
= Read Cycle Time.
LOW V
CC
DATA RETENTION WAVEFORM (1) ( /CE1 or /CE Controlled )
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
8 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
LOW V
CC
DATA RETENTION WAVEFORM (2) ( CE2 Controlled-BGA only )
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS OUTPUTS
MUST BE STEADY MUST BE STEADY
MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L
MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H
DON’T CARE ANY CHANGE
PERMITTED CHANGE STATE UNKNOWN
DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE
AC TEST LOADS
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
9 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS(
TA = 0~+70
o
C / -40
0
C~+85
0
C , Vcc = 3.0V )
< READ CYCLE >
55 70 JEDEC
Name
Parameter
Name Description MIN
MAX
MIN
MAX
Unit
t
AVAX
t
RC
Read Cycle Time 55
70
ns
t
AVQV
t
AA
Address Access Time 55
70
ns
t
ELQV
t
CO
Chip Select Access Time (/CE) 55
70
ns
t
BA
t
BA
Data Byte Control Access Time (/LB, /UB) 55
70
ns
t
GLQV
t
OE
Output Enable to Output Valid 30
35
ns
t
ELQX
t
LZ
Chip Select to Output Low Z (/CE) 5 5 ns
t
BE
t
BLZ
Data Byte Control to Output Low Z (/LB, /UB) 10
10
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z 5 5 ns
t
EHQZ
t
HZ
Chip Deselect to Output in High Z (/CE) 0 20
0 20
ns
t
BDO
t
BHZ
Data Byte Control to Output High Z (/LB, /UB) 0 20
0 20
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z 0 20
0 20
ns
t
AXOX
t
OH
Out Disable to Address Change 10
10
ns
SWITCHING WAVEFORMS (READ CYCLE)
For single CE product of 44 TSOP 2- 400mil
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
10 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. t
HZ
and t
OHZ
are defined as the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
2. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device
and from device to device interconnection.
For dual CE product of 48 Mini_BGA 8x10mm
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
11 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. t
HZ
and t
OHZ
are defined as the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and
from device to device interconnection.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
12 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS (
TA = 0~+70
o
C / -40
0
C~+85
0
C , Vcc = 3.0V )
< WRITE CYCLE >
55 70 JEDEC
Name
Parameter
Name
Description
MIN
MAX
MIN
MAX
Unit
t
AVAX
t
WC
Write Cycle Time 55
70
ns
t
E1LWH
t
CW
Chip Select to End of Write 45
60
ns
t
AVWL
t
AS
Address Setup Time 0 0 ns
t
AVWH
t
AW
Address Valid to End of Write 45
60
ns
t
WLWH
t
WP
Write Pulse Width 45
55
ns
t
WHAX
t
WR
Write Recovery Time (/CE, /WE) 0 0 ns
t
BW
t
BW
Data Byte Control to End of Write(/LB, /UB) 55
70
ns
t
WLQZ
t
WHZ
Write to Output in High Z 0 20
0 20
ns
t
DVWH
t
DW
Data to Write Time Overlap 30
30
ns
t
WHDX
t
DH
Data Hold from Write Time 0 0 ns
t
WHOX
t
OW
End of Write to Output Active 5 5 ns
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
13 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (WRITE CYCLE)
For single CE product of 44 TSOP 2- 400mil
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
14 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. A write occurs during the overlap(t
WP
) of low /CE and low /WE. A write begins when /CE goes low and
/WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition
when /CE goes high and /WE goes high. The t
WP
is measured from the beginning of the write to the end
of write.
2. t
CW
is measured from the /CE going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. T
WR
applied in case a write ends as /CE or
/WE going high.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
15 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
For dual CE product of 48 Mini_BGA 8x10mm
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
16 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. A write occurs during the overlap(t
WP
) of low /CE1, high CE2and low /WE. A write begins when /CE1 goes
low, CE2 goes high and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at
the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The t
WP
is measured from
the beginning of the write to the end of write.
2. t
CW
is measured from the /CE1 going low or CE2 going high to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end or write to the address change. T
WR
applied in case a write ends as /CE1
going high, CE2 going low or /WE going high.
High Speed Super Low Power SRAM
512k Word By 16 bit
CS16LV81923
17 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
ORDER INFORMATION
Note: Package material code “P” & “R” comply with RoHS.
