A43L3616A Series
2M x 16 Bit x 4 Banks Synchronous DRAM
Preliminary
PRELIMINARY (November, 2011, Version 0.8) AMIC Technology, Corp.
Document Title
2M x 16 Bit x 4 Banks Synchronous DRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue August 7, 2007 Preliminary
0.1 Change clock frequency from 133MHz to 143MHz at 7ns cycle November 14, 2007
time
0.2 Add part numbering scheme February 20, 2008
0.3 Add A43L4608A part number May 5, 2008
Modify DC spec.
0.4 Add Test Mode description August 13, 2008
0.5 Add automotive temperature grade November 11, 2008
0.6 Remove A43L4608A part number January 7, 2009
Modify DC current spec.
0.7 Add 54 balls CSP (8mm x 8mm) package August 28, 2009
0.8 Modify tRAS(max.) from 100ns to 100μs November 8, 2011
A43L3616A Series
2M x 16 Bit x 4 Banks Synchronous DRAM
Preliminary
PRELIMINARY (November, 2011, Version 0.8) 1 AMIC Technology, Corp.
Features
JEDEC standard 3.3V ± 0.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse RAS
MRS cycle with address key programs
- CAS Lat ency (2,3)
- Burst Length (1,2,4,8)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Industrial operating range: -40°C to +85°C for –U
Automotive temperature operation:-40°C to +85°C for -A
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L3616A is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 X 2,097,152 words by 16
bits, abricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock. I/O transactions are possible on
every clock cycle. Range of operating frequencies,
programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory
system applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
54 Ball (6X9) CSP
1 2 3 7 8 9
A VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE
CAS RAS WE
G NC A11 A9 BA0 BA1
CS
H A8 A7 A6 A0 A1 A10
J VSS A5 A4 A3 A2 VDD
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 2 AMIC Technology, Corp.
Pin Configuration (continued)
TSOP (II)
A43L3616AV
54
53
52
51
50
49
48
47
46
45
43
44
42
41
40
39
38
37
36
35
34
33
32
31
30
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
A10/AP
BA1
BA0
A0
A1
A2
26
27 28
29A3
VDD
A11
NC/RFU
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 3 AMIC Technology, Corp.
Block Diagram
Notes: This figure shows the A43L3616A.
Bank Select
Row Buffer
Refresh Counter
Address Register
Row Decoder Column Buffer
LCBR
LRAS
CLK
ADD
Timing Re gist er
Data Input Register
2M X 16
Sense AMP
Column Decoder
Latency & Burst Length
Programming Register
LRAS
LCAS
LRAS LCBR LWE LWCBR
DQM
CLK CKE CS RAS CAS WE DQM
I/O Control Output Buffer
LWE
DQM
DQi
2M X 16
2M X 16
2M X 16
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 4 AMIC Technology, Corp.
Pin Descriptions
Symbol Name Description
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM.
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
A0~A11 Address Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA8 (x16).
BA0, BA1 Bank Select Address Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column Address
Strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write Enable Enables write operation and Row precharge.
DQM,
L(U)DQM Data Input/Output
Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
LDQM corresponds to DQ0 ~ DQ7, UDQM corresponds to DQ8 ~ DQ15 .
DQ0-15 Data Input/Output Data inputs/output s are multiplexed on the same pins.
VDD/VSS Power
Supply/Ground Power Supply: +3.3V±0.3V/Ground.
VDDQ/VSSQ Data Output
Power/Ground Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU No Connection
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 5 AMIC Technology, Corp.
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +4.6V
Storage Temperature (TSTG) . . . . . . . . . . -55°C to +125°C
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (TA=25°C, f=1MHz)
Parameter Symbol Condition Min Typ Max Unit
Input Capacitance CI1 A0 to A11, BA0, BA1 2.5 3.5 pF
CI2
CLK, CKE, CS , RAS ,CAS ,WE ,
DQM 2.5 3.5 pF
Data Input/Output Capacitance CI/O DQ0 to DQ15 4 6.5 pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, TA = 0ºC to +70ºC, -40°C to +85°C for industrial
temperature range or -40°C to +85°C for automotive temperature range)
Parameter Symbol Min Typ Max Unit Note
Supply Voltage VDD,VDDQ 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 3.0 VDD+0.3 V Note 1
Input Low Voltage VIL -0.3 0 0.8 V Note 2
Output High Voltage VOH 2.4 - - V IOH = -2mA
Output Low Voltage VOL - - 0.4 V IOL = 2mA
Input Leakage Current IIL -5 - 5 μA Note 3
Output Leakage Current IOL -5 - 5 μA Note 4
Output Loading Condition See Figure 1
Note:
1. VIH (max) = 4.6V AC (pulse width ≤ 10ns).
2. VIL (min) = -1.5V AC (pulse width ≤ 10ns).
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under t est = 0V
4. Dout is disabled, 0V ≤ Vout ≤ VDD
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 6 AMIC Technology, Corp.
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter Symbol Value Unit
Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 μF
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 μF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, -40°C to +85°C for industrial temperature range or
-40°C to +85°C for automotive temperature range)
Speed
Symbol Parameter Test Conditions -6 -7 -75
Unit Notes
Icc1 Operating Current
(One Bank Active) Burst Length = 1
tRC = tRC(min), tCC = tCC(min), IOL = 0mA 95 85 80 mA 1
Icc2 P CKE = VIL(max), tCC = 10ns 2
Icc2 PS
Precharge Standby
Current in power-down
mode CLK = VIL(max), tCC = ∞ 1.5 mA
ICC2N CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 15
ICC2NS
Precharge Standby
Current in non power-
down mode CKE = VIH(min), CLK = VIL(max), tCC = ∞
Input signals are stable. 10
mA
ICC3N CKE = VIH(min), CS = VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 25 mA
ICC3NS
Active Standby current
in non power-down
mode (One Bank Active) CKE = VIH(min), CLK = VIL(max), tCC = ∞
Input signals are stable 20 mA
ICC3P CKE = VIL(max), tcc=10ns 4 mA
ICC3PS
Active Standby current
in power-down mode
(One Bank Active) CKE & CLK = VIL(max), tcc= ∞ 2 mA
ICC4 Operating Current
(Burst Mode) IOL = 0mA, Page Bust
All bank Activated, tCCD = tCCD (min) 120 100 90 mA 1
ICC5 Refresh Current tRC = tRC (min) 140
120 110 mA 2
ICC6 Self Refresh Current CKE = 0.2V 2 2 2 mA
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
3. Unless otherwise noted, input swing IeveI is CMOS (VIH /VIL=VDDQ/VSSQ).
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 7 AMIC Technology, Corp.
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C, -40°C to +85°C for industrial temperature range or -40°C to +85°C for automotive
temperature range)
Parameter Value
AC input levels VIH/VIL = 2.4V/0.4V
Input timing measurement ref erence level 1.4V
Input rise and all time (See note3) tr/tf = 1ns/1ns
Output timing measurement ref erence level 1.4V
Output load condition See Fig.2
Output
870Ω
1200Ω
(Fig. 1) DC Output Load Circuit
ZO=50Ω
OUTPUT
50Ω
VTT =1.4V
50pF
(Fig. 2) AC Output Load Circuit
3.3V
50pF
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
AC Characteristics
(AC operating conditions unless otherwise noted)
-6 -7 -75
Symbol Parameter CAS
Latency Min Max Min Max Min Max Unit Note
3 6 7 7.5
tCC CLK cycle time 2 10
1000 10 1000 10 1000 ns 1
3 5.4 5.4 5.4
tSAC CLK to valid
Output delay 2 - 5.4 - 5.4 - 6 ns 1,2
3 2.5 3 3
tOH Output data hold time 2 3
- 3 - 3 - ns 2
tCH CLK high pulse width 2.5 - 2.5 - 2.5 - ns 3
tCL CLK low pulse width 2.5 - 2.5 - 2.5 - ns 3
tSS Input setup time 1.5 - 1.5 - 1.5 - ns 3
tSH Input hold time 1 - 1 - 1 - ns 3
tSLZ CLK to output in Low-Z
2, 3
1 - 1 - 1 - ns 2
3 5.4 5.4 5.4
tSHZ CLK to output In Hi-Z 2 - 5.4 - 5.4 - 6 ns -
*All AC parameters are measured from half to half .
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 8 AMIC Technology, Corp.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version Symbol Parameter CAS
Latency -6 -7 -75
Unit Note
tRRD(min) Row active to row active delay 12 14 15 ns 1
tRCD(min) RAS to CAS delay 18 20 20 ns 1
tRP(min) Row precharge time 18 20 20 ns 1
tRAS(min) 42 45 45 ns
tRAS(max) Row active time 100 100 100 μs 1
tRC(min) Row cycle time 60 63 65 ns 1
tCDL(min) Last data in new col. Address delay 1 1 1 CLK 2
tRDL(min) Last data in row precharge 2 2 2 CLK 2
tCCD(min) Col. Address to col. Address delay
2,3
1 1 1 CLK
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 9 AMIC Technology, Corp.
Simplified Truth Table
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0
BA1 A10
/AP A9~A0,
A11 Notes
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry H L L L L H X X 3
L H H H 3
Refresh
Self
Refresh Exit L H
H X X X X X 3
Bank Active & Row Addr. H X L L H H X V Row Addr. 4
Auto Precharge Disable L 4 Read &
Column Addr. Auto Precharge Enable H X L H L H X V
H Column
Addr. 4,5
Auto Precharge Disable L 4 Write &
Column Addr. Auto Precharge Enable H X L H L L X V
H Column
Addr. 4,5
Reserved H X L H H L X X
Bank Selection V L
Precharge Both Banks H X L L H L X
X H X
L H H H
Entry H L
H X X X X
Clock Suspend or
Active Power Down Exit L H X X X X X X
L H H H
Entry H L
H X X X X
L V V V
Precharge Power Down Mode Exit L H
H X X X X X
DQM H X V X 6
L H H H
No Operation Command H X H X X X X X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code: Operand Code
A0~A11, BA0, BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
4. BA0, BA1 : Bank select address.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read write command cannot be issued.
Another bank read write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 10 AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address BA0 BA1 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function RFU RFU W.B.L TM CAS Latency BT Burst Length
(Note 1) (Note 2)
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 0 1 0 2 0 1 0 4 4
1 1
Vendor
Use
Only 0 1 1 3 0 1 1 8 8
Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved
A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved
0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved
1 1 1 Reserved Reserved
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 11 AMIC Technology, Corp.
Burst Sequence (Burst Length = 4)
Initial address
A1 A0 Sequential Interleave
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
Burst Sequence (Burst Length = 8)
Initial address
A2 A1 A0 Sequential Interleave
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 12 AMIC Technology, Corp.
Device Operations
Clock (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive edge
of the clock for proper functionality and ICC specifications.
Clock Enable (CLK)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time
same as other inputs), the internal clock is suspended form
the next clock cycle and the state of output and burst address
is frozen as long as the CKE remains low. All other inputs are
ignored from the next clock cycle after CKE goes low. When
both banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power down
mode form the next clock cycle. The SDRAM remains in the
power down mode ignoring the other inputs as long as CKE
remains low. The power down exit is synchronous as the
internal clock is suspended. When CKE goes high at least
“tSS + 1 CLOCK” before the high going edge of the clock, then
the SDRAM becomes active from the same clock edge
accepting all the input commands.
Bank Select (BA0, BA1)
This SDRAM is organized as two independent banks of
4,194,304 words X 8 bits memory arrays. The BA0, BA1
inputs is latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The bank
select BA0, BA1 is latched at bank act ivate, read, write mode
register set and precharge operations.
Address Input (A0 ~ A11)
The 22 address bits required to decode the 4,194,304 word
locations are multiplexed into 12 address input pins
(A0~A11). The 12 bit row address is latched along with RAS ,
BA0 and BA1 during bank activate command. The 9 bit
column address is latched along with CAS , WE, BA0 and
BA1during read or write command.
NOP and Device Deselect
When RAS , CAS and WE are high, the SDRAM performs
no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS , CAS and WE, and all the
address inputs are ignored.
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at t he same time.
2. After VDD reaches the desired voltage, a minimum pause
of 200 microseconds is required with inputs in NOP
condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operation modes of SDRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various vendor
specific options to make SDRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after
power up to operate the SDRAM. The mode register is
written by asserting low on CS ,RAS , CAS ,WE (The
SDRAM should be in active mode with CKE already high
prior to writing the mode register). The state of address pins
A0~A11, BA0 and BA1 in the same cycle as
CS ,RAS ,CAS ,WE going low is the data written in the
mode register. One clock cycle is required to complete the
write in the mode register. The mode register contents can
be changed using the same command and clock cycle
requirements during operation as long as both banks are in
the idle state. T he mode register is divided into various fields
depending on functionality. The burst length field uses
A0~A2, burst type uses A3, addressing mode uses A4~A6,
A7~A8, A11, BA0 and BA1 are used for vendor specific
options or test mode. And the write burst length is
programmed using A9. A7~A8, A11, BA0 and BA1 must be
set to low for normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 13 AMIC Technology, Corp.
Device Operations (continued)
Bank Activate
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SDRAM has two
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts the
activation of both banks immediately. Also the noise
generated during sensing of each bank of SDRAM is high
requiring some time for power supplies recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar t o tRCD specification. T he
minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is
determined by tRAS(min) specification before a precharge
command to that active bank can be asserted. T he maximum
time any bank can be in the active state is determined by
tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
Burst Read
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
C
S
and CAS with WE being high on the positive edge of
the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wr aps around if the initial address does not
start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode
register. The output goes into high-impedance at the end of
the burst, unless a new burst read was initiated to keep the
data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or
the other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.
Burst Write
The burst write command is similar to burst read command,
and is used to write data into the SDRAM consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS ,CASand WE with
valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing may not have been completed yet. The writing
can not complete to burst length. The burst write can be
terminated by issuing a burst read and DQM for blocking
data inputs or burst write in the same or the other active
bank. The burst stop command is valid only at f ull page burst
length where the writing continues at the end of burst and the
burst is wrap around. The write burst can also be terminated
by using DQM for blocking data and precharging the bank
“tRDL” after the last data input to be written into the active row.
See DQM OPERATION also.
DQM Operation
The DQM is used to mask input and output operation. It
works similar to OE during read operat ion and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in the read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock, therefore the masking occurs for
a complete cycle. The DQM signal is important during burst
interrupts of write with read or precharge in the SDRAM. Due
to asynchronous nature of the internal write, the DQM
operation is critical to avoid unwanted or incomplete writes
when the complete burst write is not required.
Precharge
The precharge operation is performed on an active bank by
asserting low on CS ,RAS ,WE and A10/AP with valid BA
of the bank to be precharged. The precharge command can
be asserted anytime after tRAS(min) is satisfied from the bank
activate command in the desired bank. “tRP” is defined as the
minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
time and rounding up to the next higher int eger. Care should
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by tRAS(max). Therefore, each bank has to be
precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in idle
state.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 14 AMIC Technology, Corp.
Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS(min) and “tRP” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands are possible to that particular bank
until the bank achieves idle state.
Four Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS ,RAS and
WE with high on A10/AP after both banks have satisfied
tRAS(min) requirement, performs precharge on both banks. At
the end of tRP after performing precharge all, both banks are
in idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS ,RAS and CAS with high on CKE and
WE. The auto refresh command can only be asserted with
both banks being in idle state and the device is not in power
down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified
by “tRC(min)”. The minimum number of clock cycles required
can be calculated by driving “tRC” with clock cycle time and
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. Both banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 4096 auto refresh
cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS ,RAS ,CAS and CKE with high on
WE. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exit ed by restarting the external clock and
then asserting high on CKE. This must be f ollowed by NOP’s
for a minimum time of “tRC” before the SDRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 4096 auto refresh cycles immediately after exiting self
refresh.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 15 AMIC Technology, Corp.
1) C lick Suspended D uring Write (BL=4)
Masked by CKE
Q0 Q1 Q3
Q0 Q2 Q3
Suspended Dout
2) C lock Suspended During R ead (BL=4)
WR
Masked by CKE
D0 D1 D2 D3
D0 D1 D2 D3
N o t W r itten
DQ(CL3)
DQ(CL2)
Internal
CLK
CKE
CMD
CLK
RD
Q2
Q1
No te : CL K to CL K d is ab le /en a b le= 1 clo ck
Basic feature And Function Descriptions
1. CLOCK Suspend
2. DQM Operation
* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.
2. DQM masks both data-in and data-out.
1) Write Mask (BL=4)
Masked by CKE
Q0 Q1 Q3
Q1 Q2 Q3
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
WR
Masked by CKE
D0 D1 D3
D0 D1 D3
DQM to Data-in Mask = 0CLK
DQ(CL3)
DQ(CL2)
DQM
CMD
CLK
RD
Hi-Z
Hi-Z
Q0 Q2 Q4
2) Read Mask (BL=4)
RD
Hi-Z
Hi-Z
Hi-Z Q6 Q7 Q8
Hi-Z
Q1 Q3
Hi-Z Hi-Z Q5 Q6 Q7
CLK
CMD
CKE
DQM
DQ(CL2)
DQ(CL3)
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 16 AMIC Technology, Corp.
3. CAS Interrupt (I)
Note : 1. By “Interrupt”, It is possible t o stop burst read/write by external command before the end of burst.
By “CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (= 1CLK).
1) Read interrupted by Read (BL=4)
Note 1
RD RD
AB
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
CLK
CMD
ADD
DQ(CL2)
DQ(CL3) t
CCD
Note2
2) Write interrupted by Write (BL =2)
WR WR
AB
CLK
CMD
ADD t
CCD Note2
DA0 DB0 DB1
t
CDL
Note3
DQ
3) Write interrupted by Read (BL =2)
WR RD
AB
t
CCD Note2
DA0 QB0 QB1
t
CDL
Note3
DQ(CL2)
QB0 QB1
DQ(CL3) DA0
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 17 AMIC Technology, Corp.
4. CAS Interrupt (II) : Read Interrupted Write & DQM
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
RD WR
D0 D1 D2 D3
RD WR
D0 D1 D2 D3
WRRD
Hi-Z
Hi-Z D0 D1 D2 D3
RD WR
D0 D1 D2 D3Q0 Hi-Z
Note 1
RD WR
D0 D1 D2 D3
RD WR
D0 D1 D2 D3
WRRD
Hi-Z D0 D1 D2 D3
RD
WR
D0 D1 D2Q0 Hi-Z
Note 2
D0 D1 D2 D3
RD WR
WR
(1) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
(2) CL=3, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
v) CMD
DQM
DQ D3
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 18 AMIC Technology, Corp.
5. Write Interrupted by Precharge & DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual banks operation.
6. Precharge
7. Auto Precharge
* Note : 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
WR PRE
Note 2
Note 1
D0 D1 D2 D3
Masked by DQM
CLK
CMD
DQM
DQ
WR PRE
D0 D1 D2 D3
CLK
CMD
DQ
1) N orm al Write (B L=4)
tRDL
RD PRE
Q0 Q1 Q2 Q3
CLK
CMD
DQ(CL2)
2) R ead (B L=4)
Q0 Q1 Q2 Q3DQ(CL3)
WR
D0 D1 D2 D3
CLK
CMD
DQ
1) Normal W rite (BL=4)
N o te 1
RD
Q0 Q1 Q2 Q3
CLK
CMD
DQ(CL2)
2) Read (BL=4)
Q0 Q1 Q2 Q3DQ(CL3)
Auto Precharge Starts
Note 1
Auto Precharge Starts
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 19 AMIC Technology, Corp.
8. MRS
Note : 1. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
9. Clock Suspend Exit & Power Down Exit
10. Auto Refresh & Self Refresh
PRE MRS
Note 1
CLK
CMD
Mode Register Set
2CLK
ACT
t
RP
2) Self Refresh
CLK
CMD
1) Auto Refresh
CKE
Internal
CLK
CLK
CMD SR
CKE
PRE
Note 4
PRE AR CMD
Note 5
~
~
~
~
~
~
~
~
t
RP
t
RC
Note 3
Note 6
~
~
CMD
~
~
Note 4
t
RP
t
RC
~
~
~
~
~
~
2) Power Down (=Precharge Power Down) Exit
Note 1
CLK
CMD
1) Clock Suspend (=Active Power Down) Exit
RD
t
SS
CKE
Internal
CLK
Note 2
CLK
CMD ACT
CKE
Internal
CLK
t
SS
NOP
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 20 AMIC Technology, Corp.
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refr esh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle stat e.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refr esh interval and refresh operation are performed int ernally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.
11. About Burst Type Control
Sequential counting At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
Basic
MODE Interleave counting At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Random
MODE Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
12. About Burst Length Control
1 At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violat ed.
2 At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violat ed.
4 At MRS A2,1,0 = “010”
Basic
MODE
8 At MRS A2,1,0 = “011”.
Special
MODE
BRSW
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
RAS Interrupt
(Interrupted by Precharge)
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
tRDL=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Interrupt
MODE CAS Interrupt Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 21 AMIC Technology, Corp.
Power On Sequence & Auto Refresh
KEY
KEY
KEY Ra
BA
Ra
Hig h level is nec e s s ary
High level is necessary
High-Z
tRP tRC
0 1 2 3 4 5 6 7 8 9 10111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA0, BA1
A10/AP
WE
DQM
DQ
Precharge
(All Banks) Auto Re fres h Auto Refresh Mode R egiser Set
Row Active
(A-Bank)
: Do n 't ca re
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~
~
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 22 AMIC Technology, Corp.
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
Rb
High
tRCD tRP
0 1 2 3 4 5 6 7 8 9 10111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA0, BA1
A10/AP
WE
DQM
DQ
Row Active Read Write Row Active
: Don't care
tCH
tCL
tCC
Ra Ca Cb Cc
BA BA BA BA BA BA
Ra Rb
Qa Db Qc
tRAS
tRC tSH
tSS
*Note 1
tSH
tSS tCCD
tSH
tSS
tSH
tSS
tSS
tSH
*Note 2 *Note 2,3 *Note 2,3 *Note 2,3 *Note 4 *Note 2
*Note 3 *Note 3 *Note 3 *Note 4
tSH
tSS
tSHtSS
tSH
tSS
tRAC tSAC
tSLZ tOH tSHZ
Read
Precharge
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 23 AMIC Technology, Corp.
* Note : 1. All inputs can be don’t care when CS is high at t he CLK high going edge.
2. Bank active & read/write are controlled by BA0, BA1.
BA1 BA0 Active & Read/Write
0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA1 BA0 Operation
0 0 Disable auto precharge, leave bank A active at end of burst .
0 1 Disable auto precharge, leave bank B active at end of burst .
1 0 Disable auto precharge, leave bank C active at end of burst.
0
1 1 Disable auto precharge, leave bank D active at end of burst.
0 0 Enable auto precharge, precharge bank A at end of burst.
0 1 Enable auto precharge, precharge bank B at end of burst.
1 0 Enable auto precharge, precharge bank C at end of burst.
1
1 1 Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BA0, BA1 control bank precharge when precharge command is asserted.
A10/AP BA1 BA0 Precharge
0 0 0 Bank A
0 0 1 Bank B
0 1 0 Bank C
0 1 1 Bank D
1 X X All Banks
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 24 AMIC Technology, Corp.
Read & Write Cycle at Same Bank @Burst Length=4
High
tRC
tRCD
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA0
WE
DQM
DQ
(CL = 2)
Row Active
(A-Bank) Read
(A-Bank) Precharge
(A-Bank) Row Active
(A-Bank) Precharge
(A-Bank)
: Don't c are
*Note 1
*Note 2
Ra Ca0 Rb Cb0
Ra RbA10/AP
Qa0
tOH
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
tRAC tSAC
*Note 3 tSHZ *Note 4 tRDL
Qa0
tOH
Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
tRAC tSAC
*Note 3 tSHZ *Note 4 tRDL
Write
(A-Bank)
DQ
(CL = 3)
BA1
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 25 AMIC Technology, Corp.
Page Read & Write Cycle at Same Bank @Burst Length=4
tRDL
High
tRCD
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA0
WE
DQM
DQ
(CL=2)
Row Active
(A-Bank) Read
(A-Bank) Precharge
(A-Bank)
: Don't care
*Note 2
Ra Ca0 Cb0 Cc0
RaA10/AP
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1
Qa0 Qa1 Qb0
Write
(A-Bank)
Cd0
tCDL
*Note 2
*Note1 *Note3
Dc0 Dc1 Dd0 Dd1
Read
(A-Bank) Write
(A-Bank)
DQ
(CL=3)
BA1
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 26 AMIC Technology, Corp.
Page Read Cycle at Different Bank @Burst Length = 4
* Note : 1. CS can be don’t care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 27 AMIC Technology, Corp.
Page Write Cycle at Different Bank @Burst Length=4
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 28 AMIC Technology, Corp.
Read & Write Cycle at Different Bank @Burst Length=4
High
0 12345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA1
Row Active
(A-Bank) Read
(A-Bank)
: Don't care
RAa CAa
A10/AP
RBb
Precharge
(A-Bank)
CBb CAc
RAa
WE
QAa2QAa1QAa0 QAa3 DBb0
Write
(D-Bank) Read
(B-Bank)
DQM
QAc0 QAc1
RAc
RAcRBb tCDL
*Note 1
QAa3QAa2QAa0 QAa1 DBb0 DBb1 QAc0DBb2 DBb3 QAc1 QAc2
DQ
(CL=2)
DBb1 DBb2 DBb3
DQ
(CL=3)
Row Active
(B-Bank)
Row Active
(D-Bank)
BA0
* Note : tCDL should be met to complete write.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 29 AMIC Technology, Corp.
Read & Write Cycle with Auto Precharge @Burst Length=4
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 30 AMIC Technology, Corp.
Clock Suspension & DQM Operation Cycl e @CAS Latency = 2, Burst Length=4
* Note : DQM needed to prevent bus contention.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 31 AMIC Technology, Corp.
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
012345678910111213141516171819
CLOCK
CKE
CS
RAS
CAS
ADDR
BA1
Precharge
Power-down
Exit
: Don't care
A10/AP
Active
Power-down
Entry
Row Active
WE
Qa2
Read Precharge
DQM
DQ Qa0 Qa1
Precharge
Power-
down
Entry
tSS tSS
* Note 2
* Note 1
*Note 3
tSS tSS
Ra Ca
Active
Power-
down
Exit
~
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~
BA0
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~
Ra
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~
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (64ms)
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 32 AMIC Technology, Corp.
Self Refresh Entry & Exit Cycle
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* Note : TO ENTER SELF REFRESH MODE
1.
CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 33 AMIC Technology, Corp.
Mode Register Set Cycle Auto Refresh Cycle
0 123456 012345678910
CLOCK
CKE
CS
RAS
CAS
ADDR
: Don't care
WE
Auto Refresh New Command
DQM
DQ
MRS
~
~~
~
* Note 1
~
~
~
~
Hi-ZHi-Z
High High
~
~
~
~
tRC
*Note 2
~
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~
~
~
~
~
~
~
Key
* Note 3
~
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~
New
Command
~
~
~
~
Ra
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1. CS, RAS , CAS & WE activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 34 AMIC Technology, Corp.
Function Truth Table (Table 1)
Current
State CS RA
S
CAS WE BA Address Action Note
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L X BA CA, A10/AP ILLEGAL 2
L L H H BA RA Row Active; Latch Row Address
L L H L BA PA NOP 4
L L L H X X Auto Refresh or Self Ref resh 5
IDLE
L L L L OP Code Mode Register Access 5
H X X X X X NOP
L H H H X X NOP
L H H L X X ILLEGAL 2
L H L H BA CA,A10/AP Begin Read; Latch CA; Determine AP
L H L L BA CA,A10/AP Begin Write; Latch CA; Determine AP
L L H H BA RA ILLEGAL 2
L L H L BA PA Precharge
Row
Active
L L L X X X ILLEGAL
H X X X X X NOP(Continue Burst to End →Row Active)
L H H H X X NOP(Continue Burst to End →Row Active)
L H H L X X Term burst →Row Active
L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BA CA,AP Term burst; Begin Write; Latch CA; Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA PA Term Burst; Precharge timing for Reads 3
Read
L L L X X X ILLEGAL
H X X X X X NOP(Continue Burst to End→Row Active)
L H H H X X NOP(Continue Burst to End→Row Active)
L H H L X X ILLEGAL
L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L H L L BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP 3
L L H H BA RA ILLEGAL 2
L L H L BA A10/AP Term Burst; Precharge timing for Writes 3
Write
L L L X X X ILLEGAL
H X X X X X NOP(Continue Burst to End→Precharge)
L H H H X X NOP(Continue Burst to End→Precharge)
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
Read with
Auto
Precharge
L L L X X X ILLEGAL 2
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 35 AMIC Technology, Corp.
Function Truth Table (Table 1, Continued)
Current
State CS RA
S
CAS WE BA Address Action Note
H X X X X X NOP(Continue Burst to End→Precharge)
L H H H X X NOP(Continue Burst to End→Precharge)
L H H L X X ILLEGAL
L H L H BA CA,A10/AP ILLEGAL 2
L H L L BA CA,A10/AP ILLEGAL 2
L L H X BA RA, PA ILLEGAL
Write with
Auto
Precharge
L L L X X X ILLEGAL 2
H X X X X X NOP→Idle after tRP
L H H H X X NOP→Idle after tRP
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA PA NOP→Idle after tRP 2
Precharge
L L L X X X ILLEGAL 4
H X X X X X NOP→Row Active after tRCD
L H H H X X NOP→Row Active after tRCD
L H H L X X ILLEGAL
L H L X BA CA,A10/AP ILLEGAL 2
L L H H BA RA ILLEGAL 2
L L H L BA PA ILLEGAL 2
Row
Activating
L L L X X X ILLEGAL 2
H X X X X X NOP→Idle after tRC
L H H X X X NOP→Idle after tRC
L H L X X X ILLEGAL
L L H X X X ILLEGAL
Refreshing
L L L X X X ILLEGAL
Abbreviations
RA = Row Address BA = Bank Address AP = Auto Precharge
NOP = No Operation Command CA = Column Address PA = Precharge All
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state: Function may be legal in the bank indicated by BA, depending on the state of that
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).
5. Illegal if any banks is not idle.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 36 AMIC Technology, Corp.
Function Truth Table for CKE (Table 2)
Current
State CKE
n-1 CKE
n CS RA
S
CAS WE Address Action Note
H X X X X X X INVALID
L H H X X X X
Exit Self Refresh→ABI after tRC 6
L H L H H H X
Exit Self Refresh→ABI after tRC 6
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Self
Refresh
L L X X X X X NOP(Maintain Self Refresh)
H X X X X X X INVALID
L H H X X X X
Exit Power Down→ABI 7
L H L H H H X
Exit Power Down→ABI 7
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
Both
Bank
Precharge
Power
Down
L L X X X X X NOP(Maintain Power Down Mode)
H H X X X X X Refer to Table 1
H L H X X X X Enter Power Down 8
H L L H H H X Enter Power Down 8
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L H X X ILLEGAL
H L L L L H X Enter Self Refresh 8
H L L L L L X ILLEGAL
All
Banks
Idle
L L X X X X X NOP
H H X X X X X Refer to Operations in Table 1
H L X X X X X Begin Clock Suspend next cycle 9
L H X X X X X Exit Clock Suspend next cycle 9
Any State
Other than
Listed
Above L L X X X X X Maintain clock Suspend
Abbreviations : ABI = All Banks Idle
Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to
high transition to issue a new command.
7. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.
8. Power-down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 37 AMIC Technology, Corp.
Part Numbering Scheme
A43 XX
Package Type
V: TSOP
G: CSP
Operating Vcc
L: 3V~3.6V
P: 2.3V~2.7V
E: 1.7V~2.0V
Device Ve rs ion*
Device Type
A43: AMIC SDRAM
Device De ns i ty
06: 1M
16: 2M
26: 4M
36: 8M
46: 16M
56: 32M
83: 256K
Temperature
X
Package Material
Blank: normal
F: PB free
X
* Optional
XX
XX X
Mobile Functi on*
XX
Speed
95: 105 MHz
75: 133 MHz
7: 143 MHz
6: 166 MHz
55: 183 MHz
5: 200 MHz
I/O Width
08: 8 I/O
16: 16 I/O
32: 32 I/O
C70~C0:Blank °° gradeIndustrial C85~C-40:U °° C85~C-40:
A
°° Automative grade
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 38 AMIC Technology, Corp.
Ordering Information
Part No. Cycle Time (ns) Clock Frequen cy (MHz) Access Time Package
166 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -6F 100 @ CL = 2 5.4 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
166 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -6UF 100 @ CL = 2 5.4 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
166 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -6F 100 @ CL = 2 5.4 ns @ CL = 2 54B Pb-Free CSP
166 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -6UF
6
100 @ CL = 2 5.4 ns @ CL = 2 54B Pb-Free CSP
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -7F 100 @ CL = 2 5.4 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -7UF 100 @ CL = 2 5.4 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -7AF 100 @ CL = 2 5.4 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -7F 100 @ CL = 2 5.4 ns @ CL = 2 54B Pb-Free CSP
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -7UF 100 @ CL = 2 5.4 ns @ CL = 2 54B Pb-Free CSP
143 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -7AF
7
100 @ CL = 2 5.4 ns @ CL = 2 54B Pb-Free CSP
133 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -75F 100 @ CL = 2 6 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
133 @ CL = 3 5.4 ns @ CL = 3
A43L3616AV -75UF 100 @ CL = 2 6 ns @ CL = 2
54 TSOP (II)
(Pb-Free)
133 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -75F 100 @ CL = 2 6 ns @ CL = 2 54B Pb-Free CSP
133 @ CL = 3 5.4 ns @ CL = 3
A43L3616AG -75UF
7.5
100 @ CL = 2 6 ns @ CL = 2 54B Pb-Free CSP
Note: -U is for industrial operating t emperature range -40ºC to +85ºC.
-A is for automotive operating temperat ure range -40ºC to +85ºC.
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 39 AMIC Technology, Corp.
Package Information
54 Balls CSP (8 x 8 mm) Outline Dimensions unit: mm
0.050.40
±
0.108.00 ±
0.108.00 ±
A43L3616A Series
PRELIMINARY (November, 2011, Version 0.8) 40 AMIC Technology, Corp.
Package Information
TSOP 54 (Type II) Outline Dimensions unit: inches/mm
1
E1
E
c
54
A1A2
A
D
0.1
e
D
b
L
θ
Detail "A"
Detail "A"
27
28
Seating Plane
R1
R2
L
1
-C-
0.21 REF
0.665 REF
S
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A - - 0.047 - - 1.20
A1 0.002 0.004 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05
b 0.012 - 0.018 0.30 - 0.45
c 0.005 - 0.008 0.12 - 0.21
D 0.875 BSC 22.22 BSC
S 0.028 REF 0.71 REF
E 0.463 BSC 11.76 BSC
E1 0.400 BSC 10.16 BSC
e 0.031 BSC 0.80 BSC
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 0.031 REF 0.80 REF
R1 0.005 - - 0.12 - -
R2 0.005 - 0.010 0.12 - 0.25
θ 0° - 8° 0° - 8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
