Rev.8.00, Nov. 27.2003, page 1 of 21
HN58C1001 Series
1M EEPROM (128-kword × 8-bit)
Ready/Busy and RES function
REJ03C0145-0800Z
(Previous ADE-203-028G (Z) Rev.7.0)
Rev. 8.00
Nov. 27. 2003
Description
Renesas Technology's HN58C1001 is an electrically erasable and programmable ROM organized as 131072-
word × 8-bit. It has realized high speed, low power co nsumption an d high reliab ility by employing advanced
MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page
programming function to make the write operations faster.
Features
• Single supply: 5.0 V ± 10%
• Access time: 150 ns (max)
• Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic by te wr ite: 1 0 ms (max)
• Automatic page write (128 bytes): 10 ms (max)
• Data polling and RDY/Busy
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 104 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin
• There are also lead free products.
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 2 of 21
Ordering Information
Type No. Access time Package
HN58C1001FP-15 150 ns 525 mil 32-pin plastic SOP (FP-32D)
HN58C1001T-15 150 ns 32-pin plastic TSOP (TFP-32DA)
HN58C1001FP-15E 150 ns 525 mil 32-pin plastic SOP (FP-32DV)
Lead free
HN58C1001T-15E 150 ns 32-pin plastic TSOP (TFP-32DAV)
Lead free
Pin Arrangement
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A4
A5
A6
A7
A12
A14
A16
RDY/
Busy
V
CC
A15
RES
WE
A13
A8
A9
A11
(Top view)
HN58C1001T Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
RES
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58C1001FP Series
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 3 of 21
Pin Description
Pin name Function
A0 to A16 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy Ready busy
RES Reset
Block Diagram
V
V
OE
CE
A6
A0
A7
A16
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
to
to
to
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 4 of 21
Operation Table
Operation CE
CECE
CE OE
OEOE
OE WE
WEWE
WE RES
RESRES
RES RDY/Busy
BusyBusy
Busy I/O
Read VIL V
IL V
IH V
H*1 High-Z Dout
Standby VIH ×*2 × × High-Z High-Z
Write VIL V
IH V
IL V
H High-Z to VOL Din
Deselect VIL V
IH V
IH V
H High-Z High-Z
Write Inhibit × × V
IH ×
× V
IL × ×
Data Polling VIL V
IL V
IH V
H V
OL Dout (I/O7)
Program reset × × × V
IL High-Z High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.6 to +7.0 V
Input voltage relative to VSS Vin −0.5*1 to +7.0 V
Operating temperature range*2 Topr 0 to +70
°C
Storage temperature range Tstg −55 to +125 °C
Notes: 1. Vin min = −3.0 V for pulse width ≤ 50 ns
2. Including electrical characteristics and data retention
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
V
SS 0 0 0 V
Input voltage VIL −0.3*1 0.8 V
VIH 2.2 VCC + 0.3 V
V
H V
CC – 0.5 VCC + 1.0 V
Operating temperature Topr 0 +70 °C
Note: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 5 of 21
DC Characteristics (Ta = 0 to +70°C, VCC = 5.0V ± 10%)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2*1 µA VCC = 5.5 V, Vin =5.5 V
Output leakage current ILO 2 µA VCC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current ICC1 20 µA CE = VCC
ICC2 1 mA CE = VIH
Operating VCC current ICC3 15 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 5.5 V
50 mA Iout = 0 mA, Duty = 100%,
Cycle = 150 ns, VCC = 5.5 V
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH 2.4 V IOH = –400 µA
Notes: 1. ILI on RES: 100 µA (max)
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1 Cin 6 pF Vin = 0 V
Output capacitance*1 Cout 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 6 of 21
AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10%)
Test Condit ions
• Input pulse levels: 0.4 V to 2.4 V
0 V to VCC (RES pin)
• Input rise and fall time: ≤ 20 ns
• Output load: 1TTL Gate +100 pF
• Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
HN58C1001-15
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC 150 ns CE = OE = VIL, WE = VIH
CE to output delay tCE 150 ns OE = VIL, WE = VIH
OE to output delay tOE 10 75 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 50 ns CE = VIL, WE = VIH
RES low to output float*1 tDFR 0 350 ns CE = OE = VIL, WE = VIH
RES to output delay tRR 0 450 ns CE = OE = VIL, WE = VIH
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 7 of 21
Write Cycle
Parameter Symbol Min*2 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 150 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 100 ns
Data hold time tDH 10 ns
WE pulse width (WE controlled) tWP 250 ns
CE pulse width (CE controlled) tCW 250 ns
Data latch time tDL 300 ns
Byte load cycle tBLC 0.55 30 µs
Byte load window tBL 100 µs
Write cycle time tWC — 10*3 ms
Time to device busy tDB 120 ns
Write start time tDW 150*4 ns
Reset protect time tRP 100 µs
Reset high time*5 t
RES 1 µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100% tested.
6. A7 to A16 are page addresses and must be same within the page write operation.
7. See AC read characteristics.
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 8 of 21
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
tRR
tDFR
RES
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 9 of 21
Byte Writ e Timing Waveform (1 ) (WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
tDB
tRP
RES
VCC
tRES
High-Z High-Z
tDW
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 10 of 21
Byte Writ e Timing Waveform (2 ) (CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z High-Z
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 11 of 21
Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/
Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
VCC
tCH
tCS
tWP tDL tBLC
tDS
tDW
High-Z High-Z
*6
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 12 of 21
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/
Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
VCC
tWH
tWS
tCW
tDL tBLC
tDS
tDW
High-Z High-Z
*6
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 13 of 21
Data Polling Timing Wavef orm
tCE
tOEH
tWC
tDW
tOES
Address
CE
WE
OE
I/O7
tOE
Din X
An An
Dout
X
Dout X
*7
*7
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 14 of 21
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the intern al programming cycle is finished, tog gling of I/O6 will stop and the d e v ice can be accessible
for next read or program.
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will vary .
3. See AC read characteristics.
4. Any location can be used, but the address must be fixed.
Toggle bit Waveform
WE
t
OES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1 *2 *2
Address
*3
*3
*4
Din
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 15 of 21
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
AAAA or
2AAA
55
5555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555
AA
AAAA
or
2AAA
55
5555
80
5555
AA
AAAA
or
2AAA
55
5555
20
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 16 of 21
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each
additional b y te lo ad cycle must be started with in 30 µs from th e p receding falling ed ge of WE or CE. When
CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data
DataData
Data Polling
Data polling allows the status of the EEPROM to be determined . I f EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/Busy
BusyBusy
Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write sign a l. At th e end of write cycle,
the RDY/Busy signal changes state to high impedance.
RES
RESRES
RES Signal
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide
a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
WE
WEWE
WE, CE
CECE
CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 17 of 21
Write/Erase Endurance and Data Retentio n Time
The endurance is 104 cycles in case of the page programming and 103 cycles in case of the byte programming
(1% cumulative failure rate). The d ata retention time is m o r e than 10 years when a device is pag e -
programmed less than 104 cycles.
Data Protection
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns
or less in program mode.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the
control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 18 of 21
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
2.1 Protection by RES
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off.
The EEPROM brakes off programming operation when RES becomes low, programming operation
doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept
high for 10 ms after the last data input.
V
CC
RES
WE
or
CE
100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 19 of 21
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The
SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3
bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write
data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
Write address Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can note be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
5555
↓
AAAA or 2AAA
↓
5555
The software data protection is not enabled at the shipment.
Note: There are some differences between Renesas Technology’s and other company’s for enable/disable
sequence of software data protection. If there are any questions , please contact with Renesas
Technology’s sales offices.
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 20 of 21
Package Dimensions
HN58C1001FP Series (FP-32D, FP-32DV)
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-32D, FP-32DV
Conforms
—
1.3 g
*Dimension including the plating thickness
Base material dimension
0.15 M
*0.40 ± 0.08
20.45
1.00 Max
1.27
11.30
1.42
3.00 Max
*0.22 ± 0.05
20.95 Max
32 17
116
0˚ – 8˚
0.80 ± 0.20
14.14 ± 0.30
0.10
0.38 ± 0.06
+ 0.12
– 0.10
0.15
0.20 ± 0.04
Unit: mm
HN58C1001 Series
Rev.8.00, Nov. 27.2003, page 21 of 21
Package Dimensions (cont.)
HN58C1001T Series (TFP-32DA, TFP-32DAV)
0.10
0.08 M
0.50
8.00
*0.22 ± 0.08
14.00 ± 0.20
1.20 Max
12.40
32
116
17
*0.17 ± 0.05
0.13 ± 0.05
0˚ – 5˚
8.20 Max
0.45 Max
0.50 ± 0.10
0.80
0.20 ± 0.06
0.125 ± 0.04
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-32DA, TFP-32DAV
Conforms
Conforms
0.26 g
*Dimension including the plating thickness
Base material dimension
Unit: mm
Revision History HN58C1001 Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.0 Jul. 11. 1991 Initial issue
1.0 Jan. 10. 1992
5
6
16
8
Recommended DC Operating Conditions
Addition of VH
DC Characteristics
ICC3 max: 40 mA to 50 mA
ICC3 test: Cycle = 200 ns to Cycle = 150 ns
VIH max: VCC + 1 V to VCC + 0.3 V
VH min: VCC − 1.0 V to VCC − 0.5 V
AC Characteristics
Change of Test Conditions
Reference level: 1.8 V to 2.0 V
tDL min: 200 ns to 300 ns
tBLC min: 0.35 µs to 0.55 µs
tWP/tCW min: 150 ns to 250 ns
tCS/tCH to tWS/tWH (CE Controlled)
Functional Description
Deletion of Write Protection (2)
Data Protection 2:
during programming because to during
programming and read because
unprogrammable, standby or readout state to
unprogrammable state
Deletion of protection of mistake
by CE = VCC or OE = Low or
WE = VCC level at VCC on/off
Software data protection
Address: AAAA to AAAA or 2AAA
Change of Timing Waveforms
2.0 Jan. 21. 1993
6
Deletion of HN58C1001-12
AC Characteristics
tDH min: 0 ns to 10 ns
Deletion of Mode Description
Addition of Reset function
Change of erase/write cycles in page mode: 105 to 104
Change of erase/write cycles in byte mode: 104 to 103
3.0 Apr. 23. 1993 14 Addition of Toggle Bit
4.0 Nov. 25. 1994 6
6
11
Capacitance
Addition of note 1
AC Characteristics
Write cycle: Addition of note 2,3
Addition of tDW min: 150 ns
Page write timing wa veform
Addition of note 1
5.0 May. 23. 1995 Deletion of HN58C1001R series (TFP-32DAR)
Revision Record (cont.)
6.0 Apr. 8. 1997
6
8
16
Change of format
AC Characteristics
Addition of note.6
Timing Waveforms
Toggle bit
Addition of note.3, 4
Functional Description
Addition of CPU Reset timing waveform
Data protection 3: Addition of note
7.0 Oct. 31. 1997 8 Timing Waveforms
Read Timing Waveforms: Correct error
8.00 Nov. 27. 2003
2
20-21
Change format issued by Renesas Technology Corp.
Ordering Information
Deletion of HN58C1001P-15
Addition of HN58C1001FP-15E, HN58C1001T-15E
Package Dimensions
Deletion of DP-32
FP-32D to FP-32D, FP-32DV
TFP-32DA to TFP-32DA, TFP-32DAV
©
2003. Renesas Technolo
gy
Corp., All ri
g
hts reserved. Printed in Japan
.
Colo
p
hon 1.0
Keep safet
y
first in
y
our circuit desi
g
ns
!
1. Renesas Technolo
gy
Corp. puts the maximum effort into makin
g
semiconductor products better and more reliable, but there is alwa
y
s the possibilit
y
that trouble
m
a
y
occur with them. Trouble with semiconductors ma
y
lead to personal in
j
ur
y
, fire or propert
y
dama
g
e
.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
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The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
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An
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Renesas Technology America, Inc.
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FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
RENESAS SALES OFFICES