1
®
FN8108.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC256
256K, 32K x 8 Bit
5 Volt, Byte Alterable EEPROM
FEATURES
• Access time: 70ns
• Simple byte and page write
—Single 5V supply
—No external high voltages or VPP control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—Active: 60mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable Direct Write™ cell
—Endurance: 1,000,000 cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
—Toggle bit polling
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Intersil’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvola-
tile memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Latches and
DECODER
Control
Logic and
Timing
256Kbit
EEPROM
Array
I/O0–I/O7
Data Inputs/Outputs
CE
OE
VCC
VSS
A0–A14
WE
Address
Inputs
Data Sheet May 17, 2006
2FN8108.1
May 17, 2006
Ordering Information
PART NUMBER PART MARKING ACCESS TIME
(ns) TEMP. RANGE
(°C) PACKAGE PKG. DWG. #
X28HC256DI-15 X28HC256DI-15 150 -40 to +85 28 Ld CERDIP (520 mils)
X28HC256DM-15 X28HC256DM-15 -55 to +125 28 Ld CERDIP (520 mils)
X28HC256DMB-15 X28HC256DMB-15 MIL-STD-883 28 Ld CERDIP (520 mils)
X28HC256EMB-15 X28HC256EMB-15 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FMB-15 X28HC256FMB-15 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-15* X28HC256J-15 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-15* (Note) X28HC256J-15 Z 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-15* X28HC256JI-15 -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-15* (Note) X28HC256JI-15 Z -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JM-15* X28HC256JM-15 -55 to +125 32 Ld PLCC N32.45x55
X28HC256KI-15 X28HC256KI-15 -40 to +85 28 Ld PGA G28.550x650A
X28HC256KM-15 X28HC256KM-15 -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-15 X28HC256KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-15 X28HC256P-15 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-15 (Note) X28HC256P-15 Z 0 to +70 28 Ld PDIP (Pb-free)** E28.6
X28HC256PI-15 X28HC256PI-15 -40 to +85 28 Ld PDIP E28.6
X28HC256PIZ-15 (Note) X28HC256PI-15 Z -40 to +85 28 Ld PDIP (Pb-free)** E28.6
X28HC256PM-15 X28HC256PM-15 -55 to +125 28 Ld PDIP E28.6
X28HC256SI-15* X28HC256SI-15 -40 to +85 28 Ld SOIC (300 mil) MDP0027
X28HC256SM-15 X28HC256SM-15 -55 to +125 28 Ld SOIC (300 mil) MDP0027
X28HC256D-12 X28HC256D-12 120 0 to +70 28 Ld CERDIP (520 mils)
X28HC256DI-12 X28HC256DI-12 -40 to +85 28 Ld CERDIP (520 mils)
X28HC256DM-12 X28HC256DM-12 -55 to +125 28 Ld CERDIP (520 mils)
X28HC256DMB-12 X28HC256DMB-12 MIL-STD-883 28 Ld CERDIP (520 mils)
X28HC256EI-12 X28HC256EI-12 -40 to +85 32 Ld LCC (458 mils)
X28HC256EM-12 X28HC256EM-12 -55 to +125 32 Ld LCC (458 mils)
X28HC256EMB-12 X28HC256EMB-12 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FMB-12 X28HC256FMB-12 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-12* X28HC256J-12 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-12* (Note) X28HC256J-12 Z 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-12* X28HC256JI-12 -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-12* (Note) X28HC256JI-12 Z -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256KI-12 X28HC256KI-12 -40 to +85 28 Ld PGA G28.550x650A
X28HC256KM-12 X28HC256KM-12 -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-12 X28HC256KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-12 X28HC256P-12 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-12 (Note) X28HC256P-12 Z 0 to +70 28 Ld PDIP (Pb-free)** E28.6
X28HC256PI-12 X28HC256PI-12 -40 to +85 28 Ld PDIP E28.6
X28HC256PIZ-12 (Note) X28HC256PI-12 Z -40 to +85 28 Ld PDIP (Pb-free)** E28.6
X28HC256
3FN8108.1
May 17, 2006
X28HC256S-12* X28HC256S-12 120 0 to +70 28 Ld SOIC (300 mils) MDP0027
X28HC256SZ-12 (Note) X28HC256S-12 Z 0 to +70 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256SI-12* X28HC256SI-12 -40 to +85 28 Ld SOIC (300 mils) MDP0027
X28HC256SIZ-12 (Note) X28HC256SI-12 Z -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256SM-12* X28HC256SM-12 -55 to +125 28 Ld SOIC (300 mils) MDP0027
X28HC256D-90 X28HC256D-90 90 0 to +70 28 Ld CERDIP (520 mils)
X28HC256DI-90 X28HC256DI-90 -40 to +85 28 Ld CERDIP (520 mils)
X28HC256DM-90 X28HC256DM-90 -55 to +125 28 Ld CERDIP (520 mils)
X28HC256DMB-90 X28HC256DMB-90 MIL-STD-883 28 Ld CERDIP (520 mils)
X28HC256EM-90 X28HC256EM-90 -55 to +125 32 Ld LCC (458 mils)
X28HC256EMB-90 X28HC256EMB-90 MIL-STD-883 32 Ld LCC (458 mils)
X28HC256FI-90 X28HC256FI-90 -40 to +85 28 Ld FLATPACK (440 mils)
X28HC256FM-90 X28HC256FM-90 -55 to +125 28 Ld FLATPACK (440 mils)
X28HC256FMB-90 X28HC256FMB-90 MIL-STD-883 28 Ld FLATPACK (440 mils)
X28HC256J-90* X28HC256J-90 0 to +70 32 Ld PLCC N32.45x55
X28HC256JZ-90* (Note) X28HC256J-90 Z 0 to +70 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JI-90* X28HC256JI-90 -40 to +85 32 Ld PLCC N32.45x55
X28HC256JIZ-90* (Note) X28HC256JI-90 Z -40 to +85 32 Ld PLCC (Pb-free) N32.45x55
X28HC256JM-90* X28HC256JM-90 -55 to +125 32 Ld PLCC N32.45x55
X28HC256KM-90 X28HC256KM-90 -55 to +125 28 Ld PGA G28.550x650A
X28HC256KMB-90 X28HC256KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A
X28HC256P-90 X28HC256P-90 0 to +70 28 Ld PDIP E28.6
X28HC256PZ-90 (Note) X28HC256P-90 Z 0 to +70 28 Ld PDIP (Pb-free)** E28.6
X28HC256PI-90 X28HC256PI-90 -40 to +85 28 Ld PDIP E28.6
X28HC256PIZ-90 (Note) X28HC256PI-90 Z -40 to +85 28 Ld PDIP (Pb-free)** E28.6
X28HC256S-90* X28HC256S-90 0 to +70 28 Ld SOIC (300 mils) MDP0027
X28HC256SI-90* X28HC256SI-90 -40 to +85 28 Ld SOIC (300 mils) MDP0027
X28HC256SIZ-90 (Note) X28HC256SI-90 Z -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027
X28HC256DMB-70 X28HC256DMB-70 70 MIL-STD-883 28 Ld CERDIP (520 mils)
X28HC256JI-20 X28HC256JI-20 200 -40 to +85 32 Ld PLCC N32.45x55
X28HC256SI-20T1 200 -40 to +85 28 Ld SOIC (300 mils) Tape and Reel MDP0027
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER PART MARKING ACCESS TIME
(ns) TEMP. RANGE
(°C) PACKAGE PKG. DWG. #
X28HC256
4FN8108.1
May 17, 2006
PIN CONFIGURATION
PIN DESCRIPTIONS
Addresses (A0-A14)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
PIN NAMES
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X28HC256
PLASTIC DIP
CERDIP
FLAT PLASTIC
SOIC
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4 3 2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
LCC
PLCC
A7
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
(Top View)
A12
A14
NC
VCC
WE
A13
NC
X28HC256
11
I/O0
10
A0
14
VSS
9
A1
8
A2
7
A3
6
A4
5
A5
2
A12
28
VCC
12
I/O1
13
I/O2
15
I/O3
4
A6
3
A7
1
16
I/O4
20
CE
22
OE
24
A9
17
I/O5
27
WE
19
I/O7
21
A10
23
A11
25
A8
18
I/O6
26
A13
(Bottom View)
PGA
A14
X28HC256
Symbol Description
A0-A14 Address Inputs
I/O0-I/O7Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
VCC +5V
VSS Ground
NC No Connect
X28HC256
5FN8108.1
May 17, 2006
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC256 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight
bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from
another device within the system during a page write
operation (change the source address), but the page
address (A7 through A14) for each subsequent valid
write cycle to the part during this operation must be the
same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to one hundred
twenty-seven bytes in the same manner as the first
byte was written. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O7)
The X28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC256. This eliminates additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the pro-
gramming cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28HC256 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease, and the device will be
accessible for additional read and write operations.
5TBDP 43210I/O
Reserved
Toggle Bit
DATA Polling
X28HC256
6FN8108.1
May 17, 2006
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
Figure 3. DATA Polling Software Flow DATA Polling can effectively halve the time for writing
to the X28HC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The soft-
ware flow diagram in Figure 3 illustrates one method
of implementing the routine.
CE
OE
WE
I/O7
X28HC256
Ready
Last
Write
HIGH Z
VOL
VIH
A0–A14 An An An An An An
VOH
An
Write Data
Save Last Data
and Address
Read Last
Address
IO7
Compare?
X28HC256
No
Yes
Writes
Complete?
No
Yes
Ready
X28HC256
7FN8108.1
May 17, 2006
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
¬
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an
array comprised of multiple X28HC256 memories that
is frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The
software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default VCC Sense—All write functions are inhibited
when VCC is 3.5V typically.
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/down operations through the use of external cir-
cuits. The host would then have open read and write
access of the device once VCC was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm must
be issued prior to writing additional data to the device.
CE
OE
WE
X28C512/513
Last
Write
I/O6
HIGH Z
**
VOH
VOL
Ready
* I/O6 Beginning and ending state of I/O6 will vary.
Compare
X28C256
No
Yes
ok?
Compare
Accum with
Addr n
Load Accum
From Addr n
Last Write
Ready
Yes
X28HC256
8FN8108.1
May 17, 2006
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
The three-byte sequence opens the page write window,
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle
has been completed, the device will automatically be
returned to the data protected state.
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28HC256 will be
write protected during power-down and after any sub-
sequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
CE
WE
(VCC)
Write
Protected
VCC
0V
Data
Address
AAA
5555
55
2AAA
A0
5555
≤ tBLC MAX
Writes
ok
Byte
or
Age
tWC
Write Last
Write Data XX
to Any
Write Data A0
to Address
5555
Write Data 55
to Address
2AAA
Write Data AA
to Address
5555
After tWC
Re-Enters Data
Protected State
Byte to
Last Address
Address Optional
Byte/Page
Load Operation
Byte/Page
Load Enabled
X28HC256
9FN8108.1
May 17, 2006
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
Figure 9. Write Sequence for resetting Software
Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After tWC,
the X28HC256 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large
memory arrays, it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC256 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the l/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
CE
WE
Standard
Operating
Mode
VCC
Data
Address
AAA
5555
55
2AAA
80
5555 tWC
AA
5555
55
2AAA
20
5555
Write Data 55
to Address
2AAA
Write Data 55
to Address
2AAA
Write Data 80
to Address
5555
Write Data AA
to Address
5555
Write Data 20
to Address
5555
Write Data AA
to Address
5555
After tWC,
Re-Enters
Unprotected
State
X28HC256
10 FN8108.1
May 17, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias
X28HC256 ....................................... -10°C to +85°C
X28HC256I, X28HC256M.............. -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to VSS ........................................ -1V to +7V
D.C. output current ............................................. 10mA
Lead temperature (soldering, 10 seconds)........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage.
(2) VIL min. and VIH max. are for reference only and are not tested.
POWER-UP TIMING
Note: (3) This parameter is periodically sampled and not 100% tested.
Symbol Parameter
Limits
Unit Test ConditionsMin. Typ.(7) Max.
ICC VCC active current (TTL
Inputs)
30 60 mA CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V levels @ f = 10MHz
ISB1 VCC standby current
(TTL Inputs)
12mACE = VIH, OE = VIL, All I/O’s = open, other
inputs = VIH
ISB2 VCC standby current
(CMOS Inputs)
200 500 µA CE = VCC - 0.3V, OE = GND, All I/Os = open,
other inputs = VCC - 0.3V
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC, CE = VIH
VlL(2) Input LOW voltage -1 0.8 V
VIH(2) Input HIGH voltage 2 VCC + 1 V
VOL Output LOW voltage 0.4 V IOL = 6mA
VOH Output HIGH voltage 2.4 V IOH = -4mA
Symbol Parameter Max. Unit
tPUR(3) Power-up to read 100 µs
tPUW(3) Power-up to write 5 ms
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial -40°C +85°C
Military -55°C +125°C
Supply Voltage Limits
X28HC256 5V ±10%
X28HC256
11 FN8108.1
May 17, 2006
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
ENDURANCE AND DATA RETENTION
A.C. CONDITIONS OF TEST
MODE SELECTION
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
Symbol Test Max. Unit Conditions
CI/O(9) Input/output capacitance 10 pF VI/O = 0V
CIN(9) Input capacitance 6 pF VIN = 0V
Parameter Min. Max. Unit
Endurance 1,000,000 Cycles
Data retention 100 Years
Input pulse levels 0V to 3V
Input rise and fall times 5ns
Input and output timing levels 1.5V
CE OE WE Mode I/O Power
L L H Read DOUT active
LHL Write D
IN active
H X X Standby and
write inhibit
High Z standby
X L X Write inhibit — —
X X H Write inhibit — —
5V
1.92kΩ
30pF
OUTPUT
1.37kΩ
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X28HC256
12 FN8108.1
May 17, 2006
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
Read Cycle
Notes: (4) tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the
point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
(5) For faster 256K products, refer to X28VC256 product line.
Symbol Parameter
X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15
UnitMin. Max. Min. Max. Min. Max. Min. Max.
tRC(5) Read cycle time 70 90 120 150 ns
tCE(5) Chip enable access time 70 90 120 150 ns
tAA(5) Address access time 70 90 120 150 ns
tOE Output enable access time 35 40 50 50 ns
tLZ(4) CE LOW to active output 0 0 0 0 ns
tOLZ(4) OE LOW to active output 0 0 0 0 ns
tHZ(4) CE HIGH to high Z output 35 40 50 50 ns
tOHZ(4) OE HIGH to high Z output 35 40 50 50 ns
tOH Output hold from address change 0 0 0 0 ns
tCE
tRC
Address
CE
OE
WE
Data Valid
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
Data I/O
VIH
HIGH Z Data Valid
X28HC256
13 FN8108.1
May 17, 2006
Write Cycle Limits
Notes: (6) Typical values are for TA = 25°C and nominal supply voltage.
(7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(8) tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
Symbol Parameter Min. Typ.(6) Max. Unit
tWC(7) Write cycle time 3 5 ms
tAS Address setup time 0 ns
tAH Address hold time 50 ns
tCS Write setup time 0 ns
tCH Write hold time 0 ns
tCW CE pulse width 50 ns
tOES OE HIGH setup time 0 ns
tOEH OE HIGH hold time 0 ns
tWP WE pulse width 50 ns
tWPH(8) WE HIGH recovery (page write only) 50 ns
tDV Data valid 1µs
tDS Data setup 50 ns
tDH Data hold 0 ns
tDW(8) Delay to next write after polling is true 10 µs
tBLC Byte load cycle 0.15 100 µs
Address
tAS
tWC
tAH
tOES
tDS tDH
tOEH
CE
WE
OE
Data In
Data Out
HIGH Z
Data Valid
tCS tCH
tWP
X28HC256
14 FN8108.1
May 17, 2006
CE Controlled Write Cycle
Page Write Cycle
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a
polling operation.
(10)The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Address
tAS
tOEH
tWC
tAH
tOES
tCS
tDS tDH
tCH
CE
WE
OE
Data In
Data Out HIGH Z
Data Valid
tCW
WE
OE(9)
Last Byte
Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Byte n+2
tWP
tWPH
tBLC
tWC
CE
Address(10)
I/O
*For each successive write within the page write operation, A7–A15 should be the same or
writes to an unknown address could occur.
X28HC256
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third pa rties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www .intersil.com
FN8108.1
May 17, 2006
DATA Polling Timing Diagram(11)
Toggle Bit Timing Diagram(11)
Note: (11)Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Address An
DIN = X
tWC
tOEH tOES
CE
WE
OE
I/O7
tDW
AnAn
DOUT = X DOUT = X
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z
*
*
* I/O6 beginning and ending state will vary, depending upon actual tWC.
X28HC256
X28HC256
Printer Friendly Version
256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM
Datasheets,
Related Docs
& Simulations
Description
Key
Features
Parametric
Data
Related
Devices
Ordering Information
Part No.
Design-In
Status
Temp.
Package
MSL
Price
US $
X28HC256D-12
Active
Comm
28 Ld CerDIP
N/A
33.33
X28HC256D-90
Active
Comm
28 Ld CerDIP
N/A
X28HC256DI-12
Active
Ind
28 Ld CerDIP
N/A
28.18
X28HC256DI-12C7517
Active
Ind
28 Ld CerDIP
N/A
X28HC256DI-15
Active
Ind
28 Ld CerDIP
N/A
22.22
X28HC256DI-15C7846
Active
Ind
28 Ld CerDIP
N/A
X28HC256DI-15C7856
Active
Ind
28 Ld CerDIP
N/A
X28HC256DI-15C7921
Active
Ind
28 Ld CerDIP
N/A
X28HC256DI-90
Active
Ind
28 Ld CerDIP
N/A
30.00
X28HC256DM-12
Active
Mil
28 Ld CerDIP
N/A
X28HC256DM-15
Active
Mil
28 Ld CerDIP
N/A
29.41
X28HC256DM-90
Active
Mil
28 Ld CerDIP
N/A
47.06
X28HC256DMB-12
Active
Mil
28 Ld CerDIP
N/A
41.18
X28HC256DMB-15
Active
Mil
28 Ld CerDIP
N/A
35.29
X28HC256DMB-90
Active
Mil
28 Ld CerDIP
N/A
52.94
X28HC256EI-12
Active
Ind
32 Ld CLCC
N/A
94.44
X28HC256EM-90
Active
Mil
32 Ld LCC
N/A
76.47
X28HC256EMB-12
Active
Mil
32 Ld LCC
N/A
80.14
X28HC256EMB-15
Active
Mil
32 Ld LCC
N/A
55.29
X28HC256EMB-90
Active
Mil
32 Ld LCC
N/A
82.35
X28HC256FI-90
Active
Ind
28 Ld FlatPack
N/A
X28HC256FM-90
Active
Mil
28 Ld FlatPack
N/A
X28HC256FMB-12
Active
Mil
28 Ld FlatPack
N/A
103.11
X28HC256FMB-15
Active
Mil
28 Ld FlatPack
N/A
96.47
X28HC256FMB-90
Active
Mil
28 Ld FlatPack
N/A
161.11
X28HC256J-12
Active
Comm
32 Ld PLCC
3
4.74
X28HC256J-12T1
Active
Comm
32 Ld PLCC T+R
3
4.74
X28HC256J-15
Active
Comm
32 Ld PLCC
3
3.89
X28HC256J-15T1
Active
Comm
32 Ld PLCC T+R
3
3.89
X28HC256J-15T2
Active
Comm
32 Ld PLCC T+R
3
3.89
X28HC256J-90
Active
Comm
32 Ld PLCC
3
11.11
X28HC256J-90T1
Active
Comm
32 Ld PLCC T+R
3
11.11
X28HC256JI-12
Active
Ind
32 Ld PLCC
3
7.62
X28HC256JI-12T1
Active
Ind
32 Ld PLCC T+R
3
7.62
X28HC256JI-15
Active
Ind
32 Ld PLCC
3
4.44
X28HC256JI-15T1
Active
Ind
32 Ld PLCC T+R
3
4.44
X28HC256JI-15T2
Active
Ind
32 Ld PLCC T+R
3
4.44
X28HC256JI-90
Active
Ind
32 Ld PLCC
3
6.67
X28HC256JI-90T1
Active
Mil
32 Ld PLCC T+R
3
6.67
X28HC256JIZ-12
Active
Ind
32 Ld PLCC
3
7.62
X28HC256JIZ-12T1
Active
Ind
32 Ld PLCC T+R
3
7.62
X28HC256JIZ-15
Active
Ind
32 Ld PLCC
3
4.44
X28HC256JIZ-15T1
Active
Ind
32 Ld PLCC T+R
3
4.44
X28HC256JIZ-90
Active
Ind
32 Ld PLCC
3
6.67
X28HC256JIZ-90T1
Active
Ind
32 Ld PLCC T+R
3
6.67
X28HC256JM-15
Active
Mil
32 Ld PLCC
3
27.60
X28HC256JM-15T1
Active
Mil
32 Ld PLCC T+R
3
27.60
X28HC256JM-90
Active
Mil
32 Ld PLCC
3
30.59
X28HC256JM-90T1
Active
Mil
32 Ld PLCC T+R
3
30.59
X28HC256JM-90T2
Active
Mil
32 Ld PLCC T+R
3
30.59
X28HC256JZ-12
Active
Comm
32 Ld PLCC
3
4.74
X28HC256JZ-12T1
Active
Comm
32 Ld PLCC T+R
3
4.74
X28HC256JZ-15
Active
Comm
32 Ld PLCC
3
3.89
X28HC256JZ-15T1
Active
Comm
32 Ld PLCC T+R
3
3.89
X28HC256JZ-90
Active
Comm
32 Ld PLCC
3
11.11
X28HC256JZ-90T1
Active
Comm
32 Ld PLCC T+R
3
11.11
X28HC256KI-12
Active
Ind
28 Ld PGA
N/A
18.72
X28HC256KI-15
Active
Ind
28 Ld PGA
N/A
18.33
X28HC256KM-12
Active
Mil
28 Ld PGA
N/A
35.29
X28HC256KM-15
Active
Mil
28 Ld PGA
N/A
32.94
X28HC256KM-90
Active
Mil
28 Ld PGA
N/A
39.41
X28HC256KMB-12
Active
Mil
28 Ld CSP
N/A
58.82
X28HC256KMB-15
Active
Mil
28 Ld CSP
N/A
52.94
X28HC256KMB-90
Active
Mil
28 Ld CSP
N/A
82.35
X28HC256P-12
Active
Comm
28 Ld PDIP
N/A
6.67
X28HC256P-15
Active
Comm
28 Ld PDIP
N/A
5.56
X28HC256P-90
Active
Comm
28 Ld PDIP
N/A
8.33
X28HC256PI-12
Active
Ind
28 Ld PDIP
N/A
7.78
X28HC256PI-15
Active
Ind
28 Ld PDIP
N/A
6.11
X28HC256PIZ-12
Active
Ind
28 Ld PDIP
N/A
7.78
X28HC256PIZ-15
Active
Ind
28 Ld PDIP
N/A
6.11
X28HC256PIZ-90
Active
Ind
28 Ld PDIP
N/A
17.71
X28HC256PM-15
Active
Mil
28 Ld PDIP
N/A
12.20
X28HC256PZ-12
Active
Comm
28 Ld PDIP
N/A
6.67
X28HC256PZ-15
Active
Comm
28 Ld PDIP
N/A
5.56
X28HC256PZ-90
Active
Comm
28 Ld PDIP
N/A
8.33
X28HC256S-12
Active
Comm
28 Ld SOIC
3
9.14
X28HC256S-12T1
Active
Comm
28 Ld SOIC T+R
3
9.14
X28HC256S-90
Active
Comm
28 Ld SOIC
3
10.83
X28HC256S-90T1
Active
Comm
28 Ld SOIC T+R
3
10.83
X28HC256SI-12
Active
Ind
28 Ld SOIC
3
10.00
X28HC256SI-12T1
Active
Ind
28 Ld SOIC T+R
3
10.00
X28HC256SI-15
Active
Ind
28 Ld SOIC
3
5.56
X28HC256SI-15T1
Active
Ind
28 Ld SOIC T+R
3
5.56
X28HC256SI-20T1
Active
Ind
28 Ld SOIC T+R
3
X28HC256SI-90
Active
Ind
28 Ld SOIC
3
11.11
X28HC256SI-90T1
Active
Ind
28 Ld SOIC T+R
3
11.11
X28HC256SIZ-12
Active
Ind
28 Ld SOIC
3
10.00
X28HC256SIZ-90
Active
Ind
28 Ld SOIC
3
11.11
X28HC256SM-12
Active
Mil
28 Ld SOIC
3
18.29
X28HC256SM-12T1
Active
Mil
28 Ld SOIC T+R
3
18.29
X28HC256SM-12T2
Active
Mil
28 Ld SOIC T+R
3
X28HC256SM-15
Active
Mil
28 Ld SOIC
3
X28HC256SZ-12
Active
Comm
28 Ld SOIC
3
9.14
X28HC256EM-12
Coming Soon
Comm
32 Ld LCC
N/A
X28HC256PI-90
Coming Soon
Ind
28 Ld PDIP
N/A
X28HC256DI-15C7871
InActive
Ind
28 Ld CerDIP
N/A
X28HC256DMB-70
InActive
Mil
28 Ld CerDIP
N/A
X28HC256EI
InActive
Ind
32 Ld CLCC
N/A
X28HC256JI-20
InActive
Ind
32 Ld PLCC
3
4.11
X28HC256PI
InActive
Ind
28 Ld PDIP
N/A
X28HC256SI
InActive
Ind
28 Ld SOIC
5
The price listed is the manufacturer's suggested retail price for quantities between 100 and
999 units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
Description
The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated
with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only
nonvolatile memory.
The X28HC256 supports a 128-byte page write operation, effectively providing a 24μs/byte write
cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The
X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end
of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection
feature for protecting against inadvertent writes during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an
inherent data retention of 100 years.
Key Features
Access time: 70ns
Simple byte and page write
Single 5V supply
No external high voltages or VP-P control circuits
Self-timed
No erase before write
No complex programming algorithms
No overerase problem
Low power CMOS
Active: 60mA
Standby: 500μA
Software data protection
Protects data against system level inadvertent writes
High speed page write capability
Highly reliable Direct Write™ cell
Endurance: 1,000,000 cycles
Data retention: 100 years
Early end of write detection
DATA polling
Toggle bit polling
Pb-free plus anneal available (RoHS compliant)
Related Documentation
Datasheet(s):
256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM
Technical Homepage:
Digital ICs
Parametric Data
Organization
32kx8-Bit
Access Time (ns)
70
Active Current Max. (mA)
60
Standby Current Max. (μA)
500
Related Devices
Parametric Table
X28C010
5V, Byte Alterable E2PROM
X28C512
5V, Byte Alterable EEPROM
X28C513
5V, Byte Alterable EEPROM
X28HC64
64K, 8K x 8 Bit; 5 Volt, Byte Alterable EEPROM
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