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7/29/03
SO-8
Top View
8
1
2
3
45
6
7
D
D
D
DG
S
A
S
S
A
IRF7493
HEXFET® Power MOSFET
Notes through are on page 9
PD - 94654B
lHigh frequency DC-DC converters
Benefits
Applications
lLow Gate-to-Drain Charge to Reduce
Switching Losses
lFully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
lFully Characterized Avalanche Voltage
and Current
VDSS RDS(on) max Qg (typ.)
80V 15m:@VGS=10V 35nC
Absolute Maximum Rat ings
Parameter Units
VDS Drain-to-Sourc e V ol tage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drai n Current , VGS @ 10V
ID @ TC = 70°C Continuous Drai n Current , VGS @ 10V A
IDM Pulsed Drai n Current
c
PD @TC = 25°C Maximum Power Dissipation
f
W
PD @TC = 70°C Maximum Power Dissipation
f
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Storage Temperat ure Range
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Lead ––– 20
RθJA Junction-to-Ambient
f
––– 50
Max.
9.3
7.4
74
± 20
80
-55 to + 150
2.5
0.02
1.6
IRF7493
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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-S ource Breakdown Voltage 80 ––– ––– V
∆ΒVDSS
/
∆TJ Break down V ol tage Temp. Coeffi cient ––– 0.074 ––– mV/ ° C
RDS(on) Static Drai n-t o -S ource On-Resist ance ––– 11.5 15 mΩ
VGS(th) Gate Threshol d V ol tage 2.0 ––– 4.0 V
IDSS Drain-to-S ource Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs Forward Transconductance 13 ––– ––– S
QgTotal Gate Charge ––– 35 53
Qgs Gate-to-Source Charge ––– 5.7 –––
Qgd Gate-to-Drain Charge ––– 12 –––
td(on) Turn-On Delay Time ––– 8.3 –––
trRise Time ––– 7.5 –––
td(off) Turn-Off Del ay Ti m e ––– 30 ––– ns
tfFall Time ––– 12 –––
Ciss Input Capacit ance ––– 1510 –––
Coss Output Capacit ance ––– 320 ––– pF
Crss Reverse Transfer Capacitance ––– 130 –––
Coss Output Capacit ance ––– 1130 –––
Coss Output Capacit ance ––– 210 –––
Crss eff. Eff ective Out put Capacitance ––– 320 –––
Avalanche Characteristics
Parameter Units
EAS Single Pul se Avalanc he E nergy
d
mJ
IAR Avalanche Current
c
A
Diode Characteristics
Parameter Min. Typ. Max. Units
ISContinuous S ource Current ––– ––– 9.3
(Body Diode) A
ISM Pulsed S ource Current ––– ––– 74
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Rec overy Time ––– 37 56 ns
Qrr Reverse Rec overy Charge ––– 52 78 nC
RG = 6.2Ω
Conditions
VGS = 10V
Max.
180
5.6
VGS = 0V, VDS = 0V to 64V
g
Conditions
VGS = 0V, ID = 250µA
Reference t o 25° C, ID = 1mA
VGS = 10V, ID = 5.6A
e
TJ = 25°C, IF = 5.6A , VDD = 15V
di/dt = 100A/µs
e
TJ = 25°C, IS = 5.6A , VGS = 0V
e
showing the
integral rev erse
p-n juncti on di ode.
Typ.
–––
–––
VGS = 10V
VGS = 0V
VDS = 25V
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 64V, ƒ = 1.0MHz
VDD = 40V,
e
ID = 5.6A
MOSFET symbol
VDS = VGS, ID = 250µA
VDS = 80V, VGS = 0V
VDS = 64V, VGS = 0V, TJ = 125°C
ƒ = 1.0MHz
VDS = 15V, ID = 5. 6A
VDS = 40V
VGS = 20V
VGS = -20V
ID = 5.6A
IRF7493
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
ID, Drain-to-Source Current (A)
3.5V
20µs PULSE WIDTH
Tj = 25°C
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
ID, Drain-to-Source Current (A)
3.5V
20µs PULSE WIDTH
Tj = 150°C
VGS
TOP 15V
10V
8.0V
5.5V
5.0V
4.5V
4.0V
BOTTOM 3.5V
VGS
TOP 15V
10V
8.0V
5.5V
5.0V
4.5V
4.0V
BOTTOM 3.5V
3.0 4.0 5.0 6.0
VGS, Gat e-t o-Source Voltage (V)
0.10
1.00
10.00
100.00
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 150°C
VDS = 25V
20µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 9. 3A
VGS = 10V
IRF7493
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Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage Fig 8. Maximum Safe Operating Area
110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + C gd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 102030405060
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 64V
VDS= 40V
VDS= 16V
ID= 5.6A
0.2 0.4 0.6 0.8 1.0 1.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 150°C
VGS = 0V
0 1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIM ITED BY RDS(on)
100µsec
IRF7493
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
25 50 75 100 125 150
TC , Case Temperature (°C)
0
2
4
6
8
10
ID , Drain Current (A)
1E-005 0.0001 0.001 0.01 0.1 110 100
t1 , Rect angular Pulse Durati on (sec)
0.01
0.1
1
10
100
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGL E PU LSE
( THERM AL R ESPO N SE )
IRF7493
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Fig 13. On-Resistance Vs. Gate Voltage
Fig 12. On-Resistance Vs. Drain Current
Fig 14a&b. Basic Gate Charge Test Circuit
and Waveform
Fig 15a&b. Unclamped Inductive Test circuit
and Waveforms Fig 15c. Maximum Avalanche Energy
Vs. Drain Current
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VGS
Q
G
Q
GS
Q
GD
V
G
Charge
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
4.0 8.0 12.0 16.0
VGS, Gate -t o -Source Voltage (V)
0.010
0.020
0.030
RDS(on), Drain-to -Source On Resistance (Ω)
ID = 5. 6A
25 50 75 100 125 150
Starting TJ, Junction Tem perat ure (° C)
0
100
200
300
400
500
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 2.5A
4.5A
BOTTOM 5.6A
0 20406080
ID , Drain Current (A)
0.011
0.012
0.013
RDS (on) , Drain-to-Source On Resistance (Ω)
VGS = 10V
IRF7493
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Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 17. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF7493
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SO-8 Package Details
SO-8 Part Marking
EXAMPLE: THIS IS AN IRF7101 (MOSFET)
INTERNATIONAL
RECTIFIER
LOGO
F7101
YWW
XXXX
PART NUMBER
LOT CODE
WW = WEEK
Y = LAST DIGIT OF THE YEAR
DATE CODE (YWW)
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
7
K x 45°
8X L 8X c
y
0.25 [.010] C AB
e1 A
A1
8X b
C
0.10 [.004]
4312
F OOT PRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.27 [.050]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. D IMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSIO N: MILLIM ETER
3. DIMENSIONS ARE SHOWN IN MILLIM ETERS [INCHES].
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
8X 1.78 [.070]
IRF7493
www.irf.com 9
Repetitive rating; pulse width limited by
max. junction temperature.
Notes:
Starting TJ = 25°C, L = 12mH
RG = 25Ω, IAS = 5.6A.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLI NG D IME NS I O N : MILLIMETE R.
2. ALL DIMENSIONS AR E SHOWN IN MILLIMET E RS(I NCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.7/03
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
