NE570DR2G - ON Semiconductor

May, 2006 − Rev. 4 1Publication Order Number:

NE570/D

NE570

Compandor

The NE570 is a versatile low cost dual gain control circuit in which

either channel may be used as a dynamic range compressor or

expandor. Each channel has a full−wave rectifier to detect the average

value of the signal, a linerarized temperature−compensated variable

gain cell, and an operational amplifier.

The NE570 is well suited for use in cellular radio and radio

communications systems, modems, telephone, and satellite

broadcast/receive audio systems.

Features

•Complete Compressor and Expandor in One IC

•Temperature Compensated

•Greater than 110 dB Dynamic Range

•Operates Down to 6.0 VDC

•System Levels Adjustable with External Components

•Distortion may be Trimmed Out

•Pb−Free Packages are Available*

Applications

•Cellular Radio

•Telephone Trunk Comandor

•High Level Limiter

•Low Level Expandor − Noise Gate

•Dynamic Noise Reduction Systems

•Voltage−Controlled Amplifier

•Dynamic Filters

MAXIMUM RATINGS

Rating Symbol Value Unit

Maximum Operating Voltage VCC 24 VDC

Operating Ambient Temperature Range TA0 to +70 °C

Operating Junction Temperature TJ150 °C

Power Dissipation PD400 mW

Thermal Resistance, Junction−to−Ambient RqJA 105 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

DG CELL IN

RECT IN

VREF

1.8 V

THD TRIM

RECT CAP

INVERTER IN

OUTPUT

−

R2 20 kW

R1 10 kW

VARIABLE

GAIN

30 kW

20 kW

Figure 1. Block Diagram

RECTIFIER

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

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PIN CONNECTIONS

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

(Top View)

SOIC−16 WB

D SUFFIX

CASE 751G

RECT_IN_1 RECT_CAP_2

RECT_CAP_1

DG_CELL_IN_1

INV_IN_1

GND

RES_R3_1

OUTPUT_1

THD_TRIM_1

RECT_IN_2

DG_CELL_IN_

VCC

INV_IN_2

RES_R3_2

OUTPUT_2

THD_TRIM_2

MARKING

DIAGRAM

NE570D

AWLYYWWG

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

Plastic Small Outline Package

;

16 Leads; Body Width 7.5 mm

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PIN FUNCTION DESCRIPTION

Pin Symbol Description

1RECT CAP 1 External Capacitor Pinout for Rectifier 1

2RECT IN 1 Rectifier 1 Input

3DG CELL IN 1 Variable Gain Cell 1 Input

4 GND Ground

5INV. IN 1 Inverted Input 1

6RES. R3 1 R3 Pinout 1

7OUTPUT 1 Output 1

8THD TRIM 1 Total Harmonic Distortion Trim 1

9THD TRIM 2 Total Harmonic Distortion Trim 2

10 OUTPUT 2 Output 2

11 RES. R3 2 R3 Pinout 2

12 INV. IN 2 Inverted Input 2

13 VCC Positive Power Supply

14 DG CELL IN 2 Variable Gain Cell 2 Input

15 RECT IN 2 Rectifier 2 Input

16 RECT CAP 2 External Capacitor Pinout for Rectifier 2

ELECTRICAL CHARACTERISTICS VCC = +15 V, TA = 25 °C; unless otherwise stated.

Characteristic Test Conditions Symbol Min Typ Max Unit

Supply Voltage VCC 6.0 − 24 V

Supply Current No Signal ICC − 4.3 4.8 mA

Output Current Capability IOUT ±20 − − mA

Output Slew Rate SR − ±0.5 − V/ms

Gain Cell Distortion (Note 1) Untrimmed − 0.3 1.0 %

Trimmed − 0.05 − %

Resistor Tolerance −±5±15 %

Internal Reference Voltage 1.7 1.8 1.9 V

Output DC Shift (Note 2) Untrimmed − ±90 ±150 mV

Expandor Output Noise No signal, 15 Hz to 20 kHz

(Note 3) − 20 45 mV

Unity Gain Level (Note 4) −1.0 0 +1.0 dBm

Gain Change (Notes 1 and 5) TA = 0°C to +70°C − ±0.1 ±0.2 dB

Reference Drift (Note 5) TA = 0°C to +70°C − ±5.0 ±10 mV

Resistor Drift (Note 5) TA = 0°C to +70°C − +8.0, −5.0 − %

Tracking Error (measured relative to value at unity gain)

equals [VO − VO (unity gain)] dB − V2 dBm Rectifier Input VCC = +6.0 V

V2 = +6.0 dBm, V1 = 0 dB

V2 = −30 dBm, V1 = 0 dB −

−±0.2

+0.2 −

−0.5, +1.0 dB

Channel Separation − 60 − dB

1. Measured at 0 dBm, 1.0 kHz.

2. Expandor AC input change from no signal to 0 dBm.

3. Input to V1 and V2 grounded.

4. 0 dB = 775 mVRMS.

5. Relative to value at TA = 25°C.

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CIRCUIT DESCRIPTION

The NE570 compandor building blocks, as shown in the

block diagram, are a full−wave rectifier , a variable gain cell,

an operational amplifier and a bias system. The arrangement

of these blocks in the IC result in a circuit which can perform

well with few external components, yet can be adapted to

many diverse applications.

The full−wave rectifier rectifies the input current which

flows from the rectifier input, to an internal summing node

which is biased at VREF. The rectified current is averaged on

an external filter capacitor tied to the CRECT terminal, and

the average value of the input current controls the gai n o f t he

variable gain cell. The gain will thus be proportional to the

average value of the input signal for capacitively−coupled

voltage inputs as shown in the following equation. Note that

for capacitively−coupled inputs there is no offset voltage

capable of producing a gain error. The only error will come

from the bias current of the rectifier (supplied internally)

which is less than 0.1 mA.

GT|VIN *VREF |avg

GT|V

IN |avg

The speed with which gain changes to follow changes in

input signal levels is determined by the rectifier filter

capacitor. A small capacitor will yield rapid response but

will not fully filter low frequency signals. Any ripple on th e

gain control signal will modulate the signal passing through

the variable gain cell. In an expander or compressor

application, this would lead to third harmonic distortion, so

there i s a trade−off to be made between fast attack and decay

times and distortion. For step changes in amplitude, the

change in gain with time is shown by this equation.

t+10kW CRECT

G(t) +(Ginitial *Gfinal)e

t)Gfinal

The variable gain cell is a current−in, current−out device

with the ratio IOUT/IIN controlled by the rectifier. IIN is the

current which flows from the DG input to an internal

summing node biased at VREF. The following equation

applies for capacitively−coupled inputs. The output current,

IOUT, is fed to the summing node of the op amp.

IIN +VIN *VREF

R2+VIN

A compensation scheme built into the DG cell

compensates for temperature and cancels out odd harmonic

distortion. The only distortion which remains is even

harmonics, and they exist only because of internal offset

voltages. The THD trim terminal provides a means for

nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally

compensated) has the non−inverting input tied to VREF, and

the inverting input connected to the DG cell output as well

as brought out externally. A resistor, R 3, is brought out from

the summing node and allows compressor or expander gain

to be determined only by internal components.

The output stage is capable of ±20 mA output current.

This allows a +13 dBm (3.5 VRMS) output into a 300 W load

which, with a series resistor and proper transformer, can

result in +13 dBm with a 600 W output impedance.

A bandgap reference provides the reference voltage for all

summing nodes, a regulated supply voltage for the rectifier

and DG cell, and a bias current for the DG cell. The low

tempco of this type of reference provides very stable biasing

over a wide temperature range.

The typical performance characteristics illustration

shows the basic input−output transfer curve for basic

compressor or expander circuits.

+20

+10

−10

−20

−30

−40

−50

−60

−70

−80

−40 −30 −20 −10 0 +10

COMPRESSOR OUTPUT LEVEL

EXPANDOR INPUT LEVEL (dBm)

COMPRESSOR INPUT LEVEL OR EXPANDOR OUTPUT LEVEL (dBm)

Figure 2. Basic Input−Output Transfer Curve

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2, 15

4 1, 16 5, 12 8, 9

7, 10

6, 11

VCC = 15 V

VREF

10 mF0.1 mF

200 pF

8.2 kW2.2 mF

−

30 kW

20 kW

10 kW

20 kW

2.2 mF

3, 14

2.2 mF

Figure 3. Typical Test Circuit

INTRODUCTION

Much interest has been expressed in high performance

electronic g ain control ci rcuits. For n on−critical a pplications ,

an integrated circuit operational transconductance amplifier

can b e u s ed, b ut w hen h i gh−performance is r equired, o ne has

to resort to complex discrete circuitry with many expensive,

well−matched components. This paper describes an

inexpensive i ntegrated c ircuit, t he N E570 Compandor , w hich

offers a pair of high performance gain control circuits

featuring low dis torti on (<0.1 %), high s ignal−to−noise ratio

(90 dB), and wide dynamic range (110 dB).

CIRCUIT BACKGROUND

The NE570 C ompandor wa s originally de signed to s atis fy

the requirements of the telephone system. When several

telephone channels are m ultiplexed o nto a c ommon li ne, t he

resulting signal−to−noise ratio is poor and companding is

used t o all ow a w ider dynamic r ange t o b e p assed through the

channel. Figure 4 graphically shows what a compandor can

do for t he signal−to− noi se r atio o f a restricted dynami c r a nge

channel. T he i nput level r ange o f + 20 dB to − 80 dB is shown

undergoing a 2 −to−1 c ompress ion w here a 2 .0 dB i nput l evel

change i s c ompress ed i nto a 1 .0 dB o utput l evel c hange b y t he

compressor. The original 100 dB of dynamic range is thus

compressed to a 50 dB range for transmission through a

restricted dynamic range channel. A complementary

expansion on the receiving end restores the original signal

levels and reduces the channel noise by as much as 45 dB.

The significant circuits in a compressor or expander are

the rectifier and the gain control element. The phone system

requires a simple full−wave averaging rectifier with good

accuracy, since the rectifier accuracy determines the (input)

output level tracking accuracy. The gain cell determines the

distortion and noise characteristics, and the phone system

specifications here are very loose. These specs could have

been met with a simple operational transconductance

multiplier, or OTA, but the gain of an OTA is proportional

to temperature and this is very undesirable. Therefore, a

linearized transconductance multiplier was designed which

is insensitive to temperature and offers low noise and low

distortion performance. These features make the circuit

useful in audio and data systems as well as in

telecommunications systems.

INPUT

LEVEL

COMPRESSION

EXPANSION

OUTPUT

LEVEL

NOISE

+20

0 dB

−40

−80

−20

0 dB

−40

−80

Figure 4. Restricted Dynamic Range Channel

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BASIC CIRCUIT HOOK−UP AND OPERATION

Figure 5 shows the block diagram of one half of the chip,

(there are two identical channels on the IC). The full−wave

averaging rectifier provides a gain control current, I G, for the

variable gain (DG) cell. The output of the DG cell is a current

which is fed to the summing node of the operational

amplifier. Resistors are provided to establish circuit gain and

set the output DC bias.

7, 10

OUTPUT

−

20 kW

VREF

1.8 V

5, 12

INV. INR3

6, 11

20 kW

30 kW

VCC: PIN 13

GND: PIN 4

CRECT

1, 16

8, 9

THD_TRIM

10 kW

RECT_IN

2, 15

3, 14

DG_CELL_IN

Figure 5. Chip Block Diagram (1 of 2 Channels)

The circuit is intended for use in single power supply

systems, so the internal summing nodes must be biased at

some voltage above ground. An internal band gap voltage

reference provides a very stable, low noise 1.8 V reference

denoted V REF. The non−inverting input of the op amp is tied

to V REF, and the summing nodes of the rectifier and DG cell

(located at the right of R1 and R2) have the same potential.

The THD_TRIM pin is also at the VREF potential.

Figure 6 shows how the circuit is hooked up to realize an

expander. The input signal, VIN, is applied to the inputs of

both the rectifier and the DG cell. When the input signal

drops by 6.0 dB, the gain control current will drop b y a factor

of 2, and so the gain will drop 6 dB. The output level at VOUT

will thus drop 12 dB, giving us the desired 2−to−1

expansion.

VOUT

−

R4VREF

*CRECT

VIN

*CIN1

*CIN2

* EXTERNAL COMPONENTS

GAIN = 2 R3 VIN (Avg.)

R1 R2 IB

IB = 140 mA

NOTES:

Figure 6. Basic Expander

Figure 7 shows the hook−up for a compressor. This is

essentially a n expander placed in the feedback loop of the op

amp. The DG cell is set−up to provide AC feedback only, so

a separate DC feedback loop is provided by the two RDC and

CDC. The values of RDC will determine the DC bias at the

output of the op amp. The output will bias to:

VOUT DC +ǒ1)RDC1 )RDC2

R4ǓVREF

VOUT DC +ǒ1)RDC TOT

30 kWǓ1.8 V

The output of the expander will bias up to:

VOUT DC +ǒ1)R3

R4ǓVREF

VOUT DC +ǒ1)20 kW

30 kWǓ1.8 V +3.0 V

The output will bias to 3.0 V when the internal resistors

are used. External resistors may be placed in series with R3,

(which will af fect the gain), or in parallel with R4 to raise the

DC bias to any desired value.

VOUT

−

R4VREF

*RDC

*CDC

VIN

*CIN

* EXTERNAL COMPONENTS

GAIN =

IB = 140 mA

NOTES:

*RDC

*CRECT

*CF

Figure 7. Basic Compressor

ǒR1R2IB

3VIN(avg.)Ǔ1

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CIRCUIT DETAILS−RECTIFIER

Figure 8 shows the concept behind the full−wave

averaging rectifier. The input current to the summing node

of the op amp, VIN/R1, is supplied by the output of the op

amp. If we can mirror the op amp output current into a

unipolar current, we will have an ideal rectifier. The output

current is averaged by R5, CR, which set the averaging time

constant, and then mirrored with a gain of 2 to become IG,

the gain control current.

Figure 9 shows the rectifier circuit in more detail. The op

amp is a one−stage op amp, biased so that only one output

device is on at a time. The non−inverting input, (the base of

Q1), which is shown grounded, is actually tied to the internal

1.8 V VREF. The inverting input is tied to the op amp output,

(the emitters of Q5 and Q6), and the input summing resistor

R1. The single diode between the bases o f Q5 and Q6 assures

that only one device is on at a time. To detect the output

current o f t he o p a mp, w e s imply u se t he c ollector c urrents o f

the output devices Q5 and Q6. Q6 will conduct when the

input swings positive and Q5 conducts when the input

swings negative. Th e col le c t o r curr e nt s wil l be i n erro r b y t h e

α of Q5 or Q6 on negative or positive signal swings,

respectively. ICs such as this have typical NPN β’s of 200

and PNP β’s of 40. The α’s of 0.995 and 0.975 will produce

errors of 0.5% on negative swings and 2.5% on positive

swings. The 1.5% average of these errors yields a mere

0.13 dB gain error.

At very low input signal levels the bias current of Q2,

(typically 50 nA), will become significant as it must be

supplied b y Q 5. Another low level error can be caused by DC

coupling into the rectifier. I f an of fset voltage exists between

the VIN input pin and the base of Q2, an error current of

VOS/R1 will be generated. A mere 1.0 mV of offset will

cause an input current of 100 nA, which will produce twice

the error of the input bias current. For highest accuracy, the

rectifier should be coupled capacitively. At high input levels

the β of the PNP Q6 will begin to suffer, and there will be an

increasing error until the circuit saturates. Saturation can be

avoided by limiting the current into the rectifier input to

250 mA. If necessary, an external resistor may be placed in

series with R1 to limit the current to this value. Figure 10

shows the rectifier accuracy versus input level at a frequency

of 1.0 kHz.

−

VIN

I = VIN/R1V+

10 kW

Figure 8. Rectifier Concept

10 kW

Q8Q9

10 kWVIN

V+

V−

I1I2

NOTE:

IG = 2

VIN avg

Figure 9. Simplified Rectifier Schematic

ERROR GAIN dB

−1 −40 −20 0

RECTIFIER INPUT dBm

Figure 10. Rectifier Accuracy

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At very h igh frequencies, the re sponse of the rectifi e r will

fall of f. T he r oll−off w ill be more pronounced at l ow er i nput

levels d ue t o t he i ncreasing a mount o f g ain r equired t o s witch

between Q5 or Q6 conducting. The rectifier frequency

response for input levels of 0 dBm, −20 dBm, and −40 dBm

is shown i n F igure 11. The response at all three level s is flat

to well above the audio range.

10 k 1 MEG

INPUT = 0 dBm

−20 dBm

−40 dBm

FREQUENCY (Hz)

GAIN ERROR (dB)

Figure 11. Rectifier Frequency Response

vs. Input Level

VARIABLE GAIN CELL

Figure 12 is a diagram of the variable gain cell. This is a

linearized two−quadrant transconductance multiplier. Q1,

Q2 and the op amp provide a predistorted drive signal for the

gain control pair, Q 3 and Q4. The gain is controlled by IG and

a current mirror provides the output current.

V+

V−

NOTE:

IOUT =IG

20 kW

VIN

IIN

I2 ( = 2 I1 )

280 mA

−

140 mA

IIN =VIN

Figure 12. Simplified DG Cell Schematic

The op amp maintains the base and collector of Q1 at

ground potential (VREF) by controlling the base of Q2. The

input current IIN (= VIN/R2) is thus forced to flow through

Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has

been set at twice the value of I1, the current through Q2 is:

I2*(I1)IIN) +I1*IIN +IC2.

The op amp has thus forced a linear current swing between

Q1 and Q2 by providing the proper drive to the base of Q2.

This drive signal will be linear for small signals, but very

non−linear for large signals, since it is compensating for the

non−linearity o f the dif ferential pair, Q1 and Q2, under large

signal conditions.

The key to the circuit is that this same predistorted drive

signal is applied to the gain control pair, Q3 and Q4. When

two differential pairs of transistors have the same signal

applied, their collector current ratios will be identical

regardless of the magnitude of the currents. This gives us:

IC1

IC2 +IC4

IC3 +I1)IIN

I1*IIN

plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3

will yield the multiplier transfer function,

IOUT +IG

I1IIN +VIN

This equation is linear and temperature−insensitive, but it

assumes ideal transistors.

0.34

−6 0 +6

4 mV

3 mV

2 mv

1 mV

INPUT LEVEL (dBm)

% THD

VOS = 5 mV

Figure 13. DG Cell Distortion vs. Offset Voltage

If the transistors are not perfectly matched, a parabolic,

non−linearity is generated, which results in second

harmonic distortion. Figure 13 gives an indication of the

magnitude of the distortion caused by a given input level and

offset voltage. The distortion is linearly proportional to the

magnitude of the offset and the input level. Saturation of the

gain cell occurs at a +8.0 dBm level. At a nominal operating

level of 0 dBm, a 1.0 mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than

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this, which means our overall o ffsets are typically about mV.

The distortion is not affected by the magnitude of the gain

control current, and it does not increase as the gain is

changed. This second harmonic distortion could be

eliminated by making perfect transistors, but since that

would be difficult, we have had to resort to other methods.

A trim pin has been provided to allow trimming of the

internal offsets to zero, which effectively eliminated second

harmonic distortion. Figure 14 shows the simple trim

network required.

3.6 V

VCC

20 kW

6.2 kW

To THD Trim

≈200 pF

Figure 14. THD Trim Network

Figure 15 shows the n ois e p erformance o f t he DG cell. T he

maximum output level before clipping occurs in the gain cell

is plotted along with the output noise in a 20 kHz bandwidth.

Note that the noise drops as the gain is reduced for the first

20 dB of gain reduction. At high gains, the signal to noise

ratio is 90 dB, and the total dynamic range from maximum

signal to minimum noise is 110 dB.

VCA GAIN (dB)

+20

OUTPUT (dBm)

−20

−40

−60

−80

−100

−40 −20 0

MAXIMUM

SIGNAL LEVEL

NOISE IN

20 kHz BW

90 dB

110 dB

Figure 15. Dynamic Range

Control signal feedthrough is generated in the gain cell by

imperfect device matching and mismatches in the current

sources, I 1 and I2. When no input signal is present, changing

IG will cause a small output signal. The distortion trim is

effective in nulling out any control signal feedthrough, but

in general, the null for minimum feedthrough will be

different than the null in distortion. The control signal

feedthrough can be trimmed independently of distortion by

tying a current source to the DG input pin. This effectively

trims I1. Figure 16 shows such a trim network.

R−SELECT FOR

3.6 V470 kWTO PIN 3 OR 14

100 kW

VCC

Figure 16. Control Signal Feedthrough

OPERATIONAL AMPLIFIER

The main op amp shown in the chip block diagram is

equivalent to a 741 with a 1.0 MHz bandwidth. Figure 17

shows the basic circuit. Split collectors are used in the input

pair to reduce gM, so that a small compensation capacitor of

just 10 pF may be used. The output stage, although capable

of output currents in excess of 20 mA, is biased for a low

quiescent current to conserve power. When driving heavy

loads, this leads to a small amount of crossover distortion.

OUT

I1I2

Q1D2

−IN +IN

Q3Q4

Figure 17. Operational Amplifier

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ORDERING INFORMATION

Device Package

Plastic Small Outline Package;

16 Leads; Body Width 7.5 mm

Temperature Range Shipping†

NE570D SOIC−16 WB 0°C to +70°C47 Units / Rail

NE570DG SOIC−16 WB

(Pb−Free) 0°C to +70°C47 Units / Rail

NE570DR2 SOIC−16 WB 0°C to +70°C1000 Tape & Reel

NE570DR2G SOIC−16 WB

(Pb−Free) 0°C to +70°C1000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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PACKAGE DIMENSIONS

SOIC−16 WB

CASE 751G−03

ISSUE C

14X

B16X

SEATING

PLANE

0.25 B S

16 9

hX 45_

0.25

H8X

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

EXCESS OF THE B DIMENSION AT MAXIMUM

MATERIAL CONDITION.

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D10.15 10.45

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

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