60910HKIM 20100427-S00009 No.A1744-1/9
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
June, 2013
LC72725KVS
Overview
The LC72725KVS is ICs that implement the sign al processing required by th e European Broadcasting Union RDS
(Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast
Data System) standard. These ICs include band-pass filter, demodulator,and data buffer on chip. RDS data can be
read out from this on-chip memory by external clock input in slave operation mode.
Functions
• Bandpass filter : Switched capacitor filter (SCF)
• RDS Demodulation : 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.
• Buffer : 128 bit (about 100ms) can be restored in the on-chip data buffer.
• Data output : Master or slave output mode can be selected.
• RDS-ID : Detect RDS signal which can be reset by RST signal input.
• Standby control : Crystal oscillator can be stopped.
• Fully adjustment free
• Low Voltage
Ordering number : ENA1744
Ordering number : ENA1744
CMOS IC
RDS(RBDS) Demodulation IC
LC72725KVS
No.A1744-2/9
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = 0V
Parameter Symbol Pin Name Conditions Ratings Unit
Maximum supply voltage VDD max VDDd, VDDa VDDa≤VDDd+0.3V -0.3 to +6.5 V
Maximum input voltage VIN1 max TEST, MODE, RST -0.3 to +6.5 V
VIN2 max XIN, RDCL -0.3 to VDDd+0.3 V
VIN3 max MPXIN, CIN -0.3 to VDDa+0.3 V
Maximum output voltage VO1 max RDS-ID(READY) -0.3 to +6.5 V
VO2 max XOUT, RDDA, RDCL -0.3 to VDDd+0.3 V
VO3 max FLOUT -0.3 to VDDa+0.3 V
Maximum output current IO1 max XOUT, FLOUT, RDDA, RDCL +3.0 mA
IO2 max RDS-ID(READY) +20.0 mA
Allowable power dissipation Pd max (Ta≤85°C) 100 mW
Operating temperature Topr VDD = 3.0V to 5.5V -40 to +85 °C
Storage temperature Tstg -40 to +125 °C
Allowable Operating Ranges at Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Parameter Symbol Pin Name Conditions Ratings unit
min typ max
Supply voltage VDD V
DDd, VDDa Ta = -40 to + 85°C 3.0 5.5 V
Input high-level voltage VIH1 TEST, MODE, RST 0.7VDDd 6.5V
VIH2 RDCL 0.7VDDd V
DDdV
Input low-level voltage VIL TEST, MODE, RST,
RDCL 0 0.3VDDdV
Output voltage VO1 RDDA, RDCL V
DDdV
VO2 RDS-ID(READY) 6.5 V
Input amplitude VIN MPXIN f = 57±2kHz 1.6 50 mVrms
VXIN XIN 400 1500 mVrms
Guaranteed crystal
oscillator frequencies Xtal XIN, XOUT CI≤120Ω 4.332 MHz
Crystal oscillator operating
range TXtal XIN, XOUT Fo = 4.332MHz ±100 ppm
RDCL setup time tCS RDCL, RDDA 0 μs
RDCL high-level time tCH RDCL 0.75 μs
RDCL low-level time tCL RDCL 0.75 μs
Data output ti me tDC RDCL, RDDA 0.75 μs
READY output time tRC RDCL, READY 0.75 μs
READY low-level time tRL READY 107 ms
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Cond itions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC72725KVS
No.A1744-3/9
Electrical Characteristics at Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Parameter Symbol Pin Name Conditions Ratings unit
min typ max
Internal feedback
resistance Rf XIN 1.0 MΩ
Hysteresis VHIS TEST, MODE, RST,
RDCL 0.1VDDd V
Out put low- level voltage VOL1 RDDA, RDCL I = 2mA 0.4 V
VOL2 RDS-ID(READY) I = 8mA 0.4 V
Output high-level voltage VOH RDDA, RDCL I = -2mA VDDd-0.54 V
Input high-level current IIH1 TEST, MODE, RST,
RDCL VI = 6.5V 5.0 μA
IIH2 XIN VI = V DDd 2.0 11 μA
Input low-level current IIL1 TEST, MODE, RST,
RDCL VI = 0V 5.0 μA
IIL2 XIN VI = 0V 2.0 11 μA
Output off leakage
current IOFF RDS-ID(READY) VO = 6.5V 5.0 μA
Current drain IDD V
DDd+VDDa VDDd+VDDa
(VDDd = VDDa = 3.3V) 1.5 2.5 3.5 mA
Bandpass Filter Characteristics at Ta = 25°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Parameter Symbol Pin Name Conditions Ratings unit
min typ max
Input resistance Rmpxin MPXIN-VSSa f = 57k H z 100 kΩ
Rcin CIN-VSSa f = 57kHz 100 kΩ
Center frequency fc FLOUT 56.5 57.0 57.5 kHz
-3dB band width BW-3dB FLOUT 2.5 3.0 3.5 kHz
Gain Gain MPXIN-FLOUT f = 57kHz 28 31 34 dB
Stop band attenuation Att1 FLOUT Δf = ±7kHz 30 dB
Att2 FLOUT f<45kHz, f>70kHz 40 dB
Att3 FLOUT f<20kHz 50 dB
Reference voltage output Vref Vref VDDa = 3V 1.5 V
LC72725KVS
No.A1744-4/9
Package Dimensions Pin Assignment
unit : mm (typ)
3178B
Block Diagram
LC72725KV
Top view
8 7 6 54321
9 10 11 1213141516
XOUT
TEST CIN
FLOUT
VSSa
VDDa
MPXIN
VREF
RDS-ID/READY RDCL
RDDA RST
MODE
VDDd
XIN
VSSd
REFERENCE
VOLTAGE
CIN
FLOUT VREF
VREF
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
SMOOTHING
FILTER
MPXIN
+3V
VDDa
VSSa
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5Hz)
+3V
VDDd
RDS-ID/
READY
RST
VSSd
DATA
DECODER
XOUTXIN
TEST
TEST
CLK(4.332MHz)
OSC
RAM
(128bit)
RDDA
RDCL
RDS-ID
DETECT
MODE
SANYO : SSOP16(225mil)
5.2
4.4
6.4
0.22
0.65
(0.33)
18
916
0.5
0.15
1.5max
0.1 (1.3)
LC72725KVS
No.A1744-5/9
Pin Descriptions
Pin No. Pin Name I/O Function Pin Circuit
3 VREF Output Reference voltage output (VDDa/2)
4 MPXIN Input Baseband (multiplexed) signal input
7 FLOUT Output Subcarrier output (filter output)
8 CIN Input Subcarrier input (comparator input)
5 VDDa - Analog system power supply (+3V) -
6 VSSa - Analog system ground -
14 XOUT Output Crystal oscillator output (4.332MHz)
13 XIN Input Crystal oscillator input
(external reference signal input)
9 TEST Test input
10 MODE Read out mode (0:master, 1:slave)
15 RST RDS-ID/RAM reset (active high)
2 RDDA Output RDS data output
16 RDCL I /O RDS clock output (master mode) /
RDS read out clock input (slave mode)
1 RDS-ID/
READY Output RDS reliability data output
(High:data with high RDS reliability
Low: data with low RDS reliability)
READY output (active high)
12 VDDd - Digital system power supply (+3V) -
11 VSSd - Digital system ground -
VDDa
VSSa
VDDa
VSSa
VDDa
VREF
VSSa
VDDd
XOUT
XIN
VSSd
S
VSSd
VSSd
VDDd
VSSd
S VSSd
VDDd
LC72725KVS
No.A1744-6/9
Input/Output Data Format
TEST MODE Circuit Operation Mode RDCL Pin RDS-ID/READY Pin
0 0 Master read out mode Clock output RDS-ID output
0 1 Slave read out mode Clock input READY output
1 0 Standby mode (crystal oscillator stopped) - -
1 1 IC test mode which is not available to user applications. - -
RST Pin
RST = 0 Normal operation
RST = 1 RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode)
RDS-ID/READY Pin
Master mode RDS-ID output (Active-high)
Slave mode READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
RDS-ID Output Timing
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
421
μ
s 421
μ
s
17
μ
s 17
μ
s
T
p
1
T
p
21
RDCL out
p
ut
RDDA out
p
ut
RDDA
RDCL
High/Low High/Low High/Low High/Low High/Low High/Low High/Low
RDS-ID
LC72725KVS
No.A1744-7/9
RST Operation in Master Mode
Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit
output is detected.
RDCL Operation in Slave Mode
Parameter Symbol Pin Name Conditions Ratings unit
min typ max
RDCL setup time tCS RDCL,RDDA 0 μs
RDCL high-level time tCH RDCL 0.75 μs
RDCL low-level time tCL RDCL 0.75 μs
Data output ti me tDC RDCL,RDDA 0.75 μs
READY output time tRC RDCL,READY 0.75 μs
READY high-level time tRH READY 107 ms
≈
RDCL
RDDA
RDSdetection circuit output
(IC internal)
RST Tp3≥250ns
≈≈
RDDA
RDCL
READY
tCH tCLtCS
tCS
tDC
tRC
tRH
≈
≈
≈
≈
LC72725KVS
No.A1744-8/9
Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be
low level.
2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next
read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped.
3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edg e of RDCL.
4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the
memory, READY signal goes high again.
5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a
reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied,
reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after
the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not
detected.
6. The readout mode may be switched between master and slave modes during readout.
Applications must observ e the following points to assure data continuity during this operation.
1) Data acquisition timing in master made
Data must be read on the falling edge of RDCL
2) Timing of the switch from master mode to slave mode
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE
high immediately.
Then, the microcontroller starts output b y setting the RDCL signal low.
The microcontroller RDCL output must start within 840μs (tms) after RDCL went low.
In this case, if the last data read in master mode was data item n, then data starting with item n+1
will be written to memory.
3) Timing of the switch from slave mode to master mode
After all data has been read from memory and READY has gone high, the application must then wait
until READY goes low once again the next time (timing A in the figure), immediately read out one bit of
data and input the RDCL clock.
Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set
MODE low.
The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the
figure).
nn+1n-1
n-2 mm+1 m+2
Timing A
tms
tsm
INPUT
OUTPUT INPUT
OUTPUT INPUT
OUTPUT
RDCL (microcontroller status)
RDCL (IC status)
RDCL
MODE
READ
Y
RDD
A
undefined
≈
≈≈
≈
≈
≈
≈
≈
≈
LC72725KVS
No.A1744-9/9
Sample Application Connection Circuit (for master mode operation)
Note: If the RST pin is unused, it must be connected to ground.
PS
XOUT
TEST VSSd
1
2
16
15
14
RDCL
RST
13
9
XIN
MODE
RST
RDCL
RDSID/READY
4.332MHz
VSSd
22pF
VSSd
22pF
CIN
FLOUT
VSSa VSSa
VDDa VDDa
8
7
6
5
4
+ 3
10
μ
F
VSSa
MPXIN MPXIN
560pF
0.1μF
330pF
VREF
VSSd
VDDd12
11
VSSd
0.1
μ
F
VDDd
VDDd
10kΩ
RDSID/READY
RDDA
RDDA
10
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