og RRECIINARY tax 1d: 5415 CY7C4281 CY7C4291 Features * High-speed, low-power, first-in first-out (FIFO) memories 64k x 9 (CY7C4281) 128k x 9 (CY7C4291) 0.5 micron CMOS for optimum speed/power High-speed 100-MHz operation (10 ns read/write cycle times) Low power lIec=40 mA Isp=2mA Fully asynchronous and simultaneous read and write operation Empty, Full, and programmable Almost Empty and Al- most Full status flags TTL compatible Output Enable (OE) pin Independent read and write enable pins Center power and ground pins for reduced noise Supports free-running 50% duty cycle clock inputs Width Expansion Capabilty 32-pin PLCC Pin-compatible density upgrade to CY7C42xX1 family . . . . . . . . ~ 64K/128Kx9 1 Meg Deep Sync FIFOs + Pin-compatible density upgrade to IDT72201/11/21/31/41/51 Functional Description The C7G4281/91 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide. The CY7C4281/91 are pin-compatible to the CY7C42X1 Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiorocessor interfaces, and commu- nications buffering. These FIFQs have 9-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-en- able pins (WENT, WEN2/LD). When WENTis LOW and WEN2/LD is HIGH, datais written into the FIFO on the rising edge of the WCLK signal. While WENT, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-run- ning read clock (RCLK} and two read enable pins (RENT, REN2). In addition, the CY7C4281/91 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks maybe tied together for single-clock operation or the two clocks may be run independently for asynchro- nous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by ex- pansion logic to direct the flow of data. Logic Block Diagram Dos WCLK WENTWE WRITE CONTROL OUTPUT Qo_8 4281-1 READ CONTROL RCLK RENT RENZ Cypress Semiconductor Corporation + 3901 North First Street + SanJose + CA95134 + 408-943-2600 January 1997 Revision August 18, 1997FRSECUMINE RY CY7C4281 CY7C4291 Pin Configuration PLCC Top View No ost In wo om aarenadn bZkdaddd Selection Guide aximum uency Zz aximum s Time (ns Minimum Cycle Time (ns) 4 3 2 1 323130 5 zo] AS 6 238] WENT 7 270 WCLK cy7caze1 6p WE N2TD 9 25H Yoo to CY7C4291 3H a, 14 23f] a; 12 ze] O; 13 217] Os 14 15 16 17 1819 20 inimum orEn et-Up (ns nimum or ns ; aximum 8 Active Power Supply Commercial 40 Current (loc1) (mA) Industrial 45 CY7C4281 cv7C4291 Density 64k x9 128k x9 Package 32-pin PLOG 32-pin PLOG Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage TEMPerature vascscscsessercncteeeronceesences Ambient erp erature with Power Applied... Supply Voltage to Ground Potential... see DC Voltage aPuedt to Outputs in High 7 State... ee seeaes 65C to +150C w BBC to +125C 0.5V to +7.0V wu 0.5V to Vog+0.5V Functional Description (continued ) The GY7C4281/91 provides four status pins: Empty, Full, Program- mable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty +7 and Full 7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags dencting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.5 CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. 10 20 40 40 45 45 DG Input Voltage... ci eeeeeeees 0.5V to V,,+0.5V Output Current into Gutputs (LOW)... ee 20 mA Static Discharge Voltage .......000 eects >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... een >200 mA Operating Range Ambient Range Temperature Vec Commercial 0C to +70C 5V + 10% Industrial!" 40C to 485C 5V + 10% Note: 1. Ty is the instant on case temperature.te ut FRSECUMINE RY CY7C4281 CY7C4291 s, tre a Be an Baa Pin Definitions Signal Name Description lO Description Do_g Data Inputs | | Data Inputs for 9-bit bus Qo_2 Data Outputs | Data Outputs for 9-bit bus WENT Write Enable 1 | | The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WENT is asserted and FF is HIGH. Ifthe FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WENT is LOW and WEN2/LD and FF are HIGH. WEN2/LD Write Enable 2 | | If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin Dual Mode Pin [7 Gag operates as a control to write or read the programmable flag offsets. WENT must be LOW and WEN2 must be HIGH to write data into the FIFQ. Data will not be written into the FIFO ifthe FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. RENT, RENZ | Read Enable | | Enables the device for Read operation. Both RENT and REN2 must be asserted to Inputs allow a read operation. WCLK Write Clock | | The rising edge clocks data into the FIFO when WENT is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off- set register. RCLK Read Clock | | The rising edge clocks data out of the FIFO when RENT and REN? are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register. EF Empty Flag | When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag | When FF is LOW the FIFO is full. FF is synchronized to WCLK. PAE Programmable | | When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro- Almost Empty grammed inte the FIFQ. PAE is synchronized to RCLK. PAF Programmable | | When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed Almost Full into the FIFO. PAF is synchronized to WCLK. RS Reset | | Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable | | When OE is LOW, the FIFOs data outputs drive the bus to which they are connected. If OE is HIGH, the FIFC's outputs are in High 2 (high-impedance) state.CY7C4281 PRSECIAINE SY CY7C4291 Electrical Characteristics Over the Qperating Range 742X1-10 | 7C42X1-15 | 7C42X1-25 | 7C42X1-35 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Voltage | Voc=Min., 2.4 2.4 2.4 2.4 Vv lou =2.0 mA VoL Output LOW Voltage | Voc=Min., 0.4 0.4 0.4 0.4 Vv lo, = 8.0 mA Vin Input HIGH Voltage 2.0 Voo 2.0 Veco 2.0 Voc 2.0 Voc Vv VIL Input LOW Voltage -0.5/ 068 |-05/ 08 |-05] 08 | 05] 08 Vv lie Input Leakage Voco= Max. -10 | +10 | -10 | +10 | -10 | +10 | -10 |] +10] BLA Current loz Output OFF, OE> Vin, -10 | +10 | -10 | +10 | -10 | +10 | -10 |] +10] LA lozH High Z Current Vss <= Vo< Vec loos! Active Power Supply Com 40 40 40 40 mA Current Ind 45 45 45 45 mA Isp i4l Average Standby Com mA Current Ind mA Capacitance!! Parameter Description Test Conditions Max. Unit Cry Input Capacitance Ta = 25C, f = 1 MHz, 5 pF Cout Output Capacitance Veo =5.0V 7 pF AC Test Loads and Waveforms 1 R1i1.ik 2 BV on ALL INPUT PULSES TT 3.0V CL Fe GND | ps INCLUDING = Equivalent to: Notes: Noo PR why JIG AND SCOPE 4281-4 THEVENIN EQUIVALENT 4209 OUTPUT #49 1.91V See the last page of this specification for Group A subgroup testing information. Input signals switch from O to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20Mhz, while data inputs switch at 10 MHz. Cutputs are unloaded. loc 1 (typical) = (20mA+(freq20MHz)*(0.7mA/MHz)) All inputs = Vere 0.2V, except WCLK and RCLK (which are at frequency = 0 MHZz). All outputs are unloaded. Tested initially and after any design or process changes that may affect these parameters. C, = 30 pF for all AC parameters except for ta.47. C, = 5pF forty. 4281-5CY7C4281 PRELIMINARY CY7C4291 Switching Characteristics Over the Operating Range 7C48X1-10 | 7C48X1-15 | 7C48X1-25 | 7C48X1-35 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit ts Clock Cycle Frequency 100 66.7 40 28.6 | MHz ta Data Access Time 2 8 2 19 2 15 2 20 ns tok Clock Cycle Time 10 15 25 35 ns teLKH Clock HIGH Time 45 6 10 14 ns teLKL Clock LOW Time 45 6 10 14 ns tos Data Set-Up Time 3 4 6 ns toy Data Hold Time 0.5 1 1 ns tens Enable Set-Up Time 3 4 6 ns teENH Enable Hold Time 0.5 1 1 ns tas Reset Pulse Width! 10 15 25 35 ns trss Reset Set-Up Time 8 10 15 20 ns trsA Reset Recovery Time 8 10 15 20 ns trsF Reset to Flag and Output Time 10 15 25 35 ns toz Output Enable to Cutput in Low 219 ns toe Output Enable to Cutput Valid 7 8 12 15 ns touz Output Enable to Cutput in High Z4 7 8 12 15 | ns twerr Write Clock to Full Flag 8 10 15 20 ns tREF Read Clock to Empty Flag 8 10 15 20 ns tear Clock to Programmable Almost-Full Flag 8 10 15 20 ns tpae Clock to Programmable Almost-Full Flag 8 19 15 20 ns tskewt Skew Time between Read Clock and Write 5 6 10 12 ns Clock for Empty Flag and Full Flag tskewe Skew Time between Read Clock and Write 10 15 18 20 ns Clock for Almost-Empty Flag and Almost-Full Flag Notes: 8. Pulse widths less than minimum values are not allowed. 9. Values guaranteed by design, not currently tested.CY7C4281 FRSECUMINE RY CY7C4291 Switching Waveforms Write Cycle Timing a tek he teLkH teLKL *} WCLK eNO ECCT CCCCC) I OOCCCOENO tus m teNH WENT k KZ No OFF FATION NX WEN2 L7 Ge RY NO OPERATION Le (if applicable) wer er FF A BK 10 tscew RCLK A ee A RENT, REN2 / 4281-6 Read Cycle Timing = toKL - pt toLkKH tco_KL -34 RCLK 7 Z \ f tens -* tENH RENT, RENZ OX V4 NO OPERATION QA I =_ tp EF -#+ = MK * tREF x j< ty, QO $$ {XXXx vAIDDATA \___ toz toe rt toHz OE 11 texews!" 1) J WCLK f \ WENT \ WEN2 f 4281-7 Notes: 10. tg<eyy is the minimum time between a rising RCLK edge and a rising WCLK ecige to guarantee that FF will go HIGH during the current dock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tg cy. then FF may net change state until the next WCLK rising edge. 11. tgceyy is the minimum time between a rising WCLK edge and arising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than ta eye, then EF may not change state until the next RCLK rising edge.CY7C4281 FRSECUMINE RY CY7C4291 Switching Waveforms (continued) Reset Timing"! RS WEN2/LD (141 EF,PAE Qy_ Qg Ope 91 OE=0 Notes: 12. The clocks (RCLK, WCLK) can be free-running during reset. 13. Atter reset, the outputs will be LOW if OE =0 andthree-state if OE=1. 14. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. 4281-8 Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers.CY7C4281 FRSECUMINE RY CY7C4291 Switching Waveforms (continued) First Data Word Latency after Reset with Read and Write WCLK Dp Dg DgFIRST VALID WRITE} WENT WEN2 (if applicable) RCLK EF RENT, REN2 O90 KXXOOK OK oz i toe > OE eK 4281-9 Notes: 15. Whentsxey = minimum specification, tea, (maximum) = ta c+ tsk eye. Whentgxeyyy < minimum specification, teg, (maximum) = either 2*ta, + tgKeyy Otol +tgkewd- The Latency Timing applies only at the Empty Boundary (EF = LOW). 16. The first word is available the cycle atter EF goes HIGH, always.FRSECUMINE RY Switching Waveforms (continued) Empty Flag Timing WCLK Dy Dg DATA WRITE 1 tENH WENT tENH WEN2 (if applicable) RCLK REN2 CY7C4281 CY7C4291 DATA WRITE 2 teNH tENH Qyp -Qz DATA IN OUTPUT REGISTER DATA READ 4261-10FRSECUMINE RY CY7C4281 CY7C4291 Switching Waveforms (continued) Full Flag Timing NO WRITE WCLK f \ 7 tskew1!"l texewt NO WRITE KH \___ 0] ba DATA WRITE os KKH FF vex twrr DATA WRITE KX XXOODOO twrr / WEN2 (if applicable) teNH RENT, tens RENZ LOW teNH teNS x ta Qy Qa DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 4281-11 10FRSECUMINE RY CY7C4281 CY7C4291 Switching Waveforms (continued) Programmable Almost Empty Flag Timing teLKH teLKL WCLK MN NI NY Vv jtens | teny = (fo WENT QQ, LZ WEN2 (if applicable) Jf fk SAN tENS: ten Note PAE 18 N+ 1 WORDS IN FIFO Note 19 te t 17] SKEW2 RCLK RENT, QS > / RENZ NK J 4281-12 Programmable Almost Full Flag Timing Note 20 leLkH fouKL vote mv \ fF MN VK [ews | Fen WEN2 Note [21 (if applicable) LLL nla AYA toys | tent Me tpAr FULL - MWORDS PAF FULL (M+1)WORDS IN FIFO 23 teicewe 22) be ete [par RENi, REN2 tens | ten Af 4281-13 Motes: 17. 18. PAE offset=n. is the minimum time between a rising WCLK and arising RCLK edge for PAE to change state during that clock cycle. Ifthe time between the edge of WCLK and the ae GRCLK is less than toeye: then PAE may not change state until the next RCLK. 19. If aread is preformed on this rising edge of the read clock, there will be Empty + (nt } words in the FIFO when PAE goes LOW 20. If awrite is performed on this rising edge of the write clack, there will be Full 21. PAF offset = (m-1} 22. i 384 m words for CY7C4281, 32,768 m words for CY4291. 23. lsc rwve isthe minimum time between a rising RCL 11 } words of the FIFO when PAF goes LOW. K edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK he rising edge of WCLK is less than tocyye, then PAF may not change state until the next WCLK.FRSECUMINE RY CY7C4281 CY7C4291 Switching Waveforms (continued) Write Programmable Registers e to.~ ax tou hee ol em tCLKL wouK FN NY NIV TK tens teNH WEN2/LD KY J tens N tps tpH 0-02 XOKOXOKOOK ROX OXXOX_ XXX XXX PAE OFFSET PAE OFFSET PAF OFFSET PAF OFFSET LSB MSB LSB MSB 4281-14 Read Programmable Registers i tol~ y4 toLKL teLKH ROLK FN NANAK SYK tens teeter tent WEN2/LD KY KW 7 7 TENS [ae RENT, PAF OFFSET REN2 \ MSB, E ty UNKNOWN Qs ROKKKKXK PAE OFFSET LSB YX PAE OFFSET MSB YX PAF OFFSE 4261-15 Architecture The CY7C4281/91 consists of an array of 64k to 128k words of 9 bits each (implemented by a dual-port array of SRAM cells}, a read pointer, a write pointer, control signals (RCLK, WCLK, RENT, REN2, WENT, WEN2, RS), and flags (EF, PAE, PAF, FF}. Resetting the FIFO Upen power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Qp_g) go LOW tper after the rising edge of RS. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaranteed to be valid tasr after RS is taken LOW. FIFO Operation When the WENT signal is active LOW , WEN2 is active HIGH, and FF is active HIGH, data present on the Dy_g pins is written into the FIFG on each rising edge of the WCLK signal. Similarly, when the REN7 and REN@ signals are active LOW and EF is active HIGH, data in the FIFQ memory will be presented on the Qo_g outputs. New data will be presented on each rising edge of RCLK while RENT and REN? are active. RENT and REN? must set up teys before RCLK for it to be a valid read function. WENT and WEN2 must occur teys before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Qg_g out- puts when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Qy_g outputs after tog. If devic- es are cascaded, the OE functicn will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO 12FRSECUMINE RY CY7C4281 CY7C4291 maintains the data of the last valid read on its Qg_g outputs even after additional reads occur. Write Enable 1 (WENT) - If the FIFO is configured for pro- grammable flags, Write Enable 1 (WENT) is the only write en- able control pin. In this configuration, when Write Enable 1 (WENT) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WGLK). Data is stored is the RAM array sequentially and in- dependently of any on-going read operation. Write Enable 2/Load (WEN2/LD) - This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. lf Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS=LOW)}, this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WENT) is LOW and Write Enable 2/Load (WEN2/LD} is HIGH, data can be loaded into the input register and RAM array on the LOW-+to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and independently of any on-go- ing read operation. Programming When WENG2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 9-bit offset registers contained in the CY7C4281/4291 for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WENT are LOW, the first LOW-to-HIGH transi- tion of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WENT are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WENT are LOW writes data to the empty LSB register again. Figure 7 shows the registers sizes and default values fer the various device types. 64k x9 128k x9 8 7 0 8 7 0 Empty Otiset (LSB) Reg Empty Offset (LSB) Reg Default Value = 007h Default Value = 007h 8.7 0 8 0 (MSB) (MSB)} Default Value= 000h Default Value = 000h 8.7 0 8 7 0 Full Offset (LSB) Reg Full Offset (LSB) Reg Default Value = 007h Default Value = 007h 8 7 0 8 0 (MSB) (MSB} Default Value= 900h Detault Value = 000h 4281-16 Figure 1. Offset Register Location and Default Values 13 It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write op- eration stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both RENT and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simulta- neously on the offset registers. Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as de- scribed in Table 7 or the default values are used, the programmable almost-empty flag (PAE) and programmable almest-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. Table 1. Writing the Offset Registers CD | WEN | weckle4 Selection 0 0 Empty Offset (LSB) ~~ f Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB)} _ 0 1 f No Operation 1 0 f Write Into FIFO 1 1 - No Operation The number formed by the empty offset least significant bit register and empty offset most significant bit register is re- ferred to as nand determines the operation of PAE. PAF is synchro- nized te the LOW-to-HIGH transition of RGLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition cf RCLK when the FIFO con- tains (n+1) or greater unread words. The number formed by the full offset least significant bit regis- ter and full offset most significant bit register is referred to as mand determines the operation of PAF PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4281 (64k m) and CY7C4291 (128k m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of avail- able memory lccations is greater than m.CY7C4281 FRECIMINSSY CY7C4291 Table 2. Status Flags Number of Words in FIFO CY7C4281 CY7C4291 FF PAF PAE EF 0 0 H H L L 1 to nl 1 to nl4l H H L H (n+1} to (65536 (m+1)} (n+1} to (131072 (m+1))} H H H H (65536 m)Il to 65535 131072 ml to 131071 H L H H 65536 131072 L L H H Notes: 22. Re POPO ata craseataltee 26. The same selection sequence applies to reading from the registers. RENT and REN@2 are enabled and a read is performed on the LOW+o-HIGH transition of RCLK. Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. A compos- ite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1s. Any word width can be attained by adding additional CY7C42X 1s. When the CY7C42X1 is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (See Fig- ure 4. Inthis configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets. Flag Operation The C7C4281/91 devices provide five flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when the device is full. Write opera- tions are inhibited whenever FF is LOW regardless of the state of WENT and WEN2/LD. FF is synchronized to WCLK, ie., itis exclu- sively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of RENT and REN2. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. RESET (RS) RESET (RS) DATAIN (D) ig, | 9 9 Y __ READ CLOCK (RCLK) WRITECLOCK (WCLK) _ nt - <aENADLE WRITE ENABLE 1 (WENT) - 1 (RENT) > > OUTPUT ENABLE (OE) WRITE ENABLE2/LOAD a (WEN2/D) PROGRAMMABLE(PAE) | C7C4281/91 CY7C4261/91 | EMPTY FLAG (EF) #1 PROGRAMMABLE(PAF) J FULL FLAG (FF) # 1 EMPTY FLAG (EF) #2 FF EFL__] - FF EF -_ g , DATAOQUT(Q) 48, FULLFLAG (FF) # 2 t / al Read Enable 2 (REN2) Read Enable 2 (REN2) 4281-17 Figure 2. Block Diagram of 64k x 9/128k x 9 Synchronous FIFO Memory Used in a Width Expansion ConfigurationCY7C4281 PEIN SY CY7C4291 Ordering Information 64kx9 1 Meg Deep Sync FIFO Speed Package Package Operating (ns) Ordering Code Name Type ange 10 CY7C4281-10JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial OY7C4281-10J1 J65 32-Lead Plastic Leaded Chip Carrier | Industrial 15 OY7C4281-15JNC J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4281-15J J65 32-Lead Plastic Leaded Chip Carrier | Industrial 25 CY7C4281-25JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4281-25J J65 32-Lead Plastic Leaded Chip Carrier | Industrial 35 CY7C4281-35JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4281-35J! J65 32-Lead Plastic Leaded Chip Carrier | Industrial 128kx9 1 Meg Deep Sync FIFO Speed Package Package Operating (ns) Ordering Code Name Type Range 10 CY7C4291-10JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4291-10J! J65 32-Lead Plastic Leaded Chip Carrier | Industrial 15 CY7C4291-15JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial OY7C4291-15u J65 32-Lead Plastic Leaded Chip Carrier | Industrial 25 OY7C4291-255C J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4291-25J1 J65 32-Lead Plastic Leaded Chip Carrier | Industrial 35 COY7C4291-35JC J65 32-Lead Plastic Leaded Chip Carrier | Commercial CY7C4291-35J J65 32-Lead Plastic Leaded Chip Carrier | Industrial Document #: 38-00578-A Package Diagram 32-Lead Plastic Leaded Chip Carrier J65 DIMENSIONS Ih INCHE> MIN, MAS, 0045 wr Kr a PIM bes TiP, poo doo = 2 al Phi S| Lau olm WAN, ou 430 W930 (a i rm =| TS or a ul un uw a J 0.050 PEF, O447 0.453 Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuliry other than circuliry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other nghts. Cypress Semiconductor does not authorize iis producis for use as critical components in life-support systems where a malfunction or failure may reasonably be expecied to result in significant injury to ihe user. The inclusion of Cypress Semiconductor products in life-support systems application implies that he manulacturer assumes all risk of such use and In doing so indemnilies Cypress Semiconductor against all charges.