DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT165
8-bit parallel-in/serial-out shift
register
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
FEATURES
•Asynchronous 8-bit parallel load
•Synchronous serial input
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q7and
Q7) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D0to
D7inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
Dsinput and shifts one place to the right
(Q0→Q1→Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q7output to the DSinput of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
•Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
CL= 15 pF; VCC = 5 V 16
15
11
14
17
11
ns
ns
ns
fmax maximum clock frequency 56 48 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per
package notes 1 and 2 35 35 pF
December 1990 3
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1PL asynchronous parallel load input (active LOW)
7Q7complementary output from the last stage
9Q
7
serial output from the last stage
2 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
10 Dsserial data input
11, 12, 13, 14, 3, 4, 5, 6 D0to D7parallel data inputs
15 CE clock enable input (active LOW)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑= LOW-to-HIGH clock transition
OPERATING MODES INPUTS Qn REGISTERS OUTPUTS
PL CE CP DSD0-D7Q0Q1-Q6Q7Q7
parallel load L
LX
XX
XX
XL
HL
HL - L
H - H L
HH
L
serial shift H
HL
L↑
↑l
hX
XL
Hq0-q5
q0-q5
q6
q6
q6
q6
hold “do nothing” H H X X X q0q1-q6q7q7
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 5
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CE, CP to Q7, Q7
52
19
15
165
33
28
205
41
35
250
50
43
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
PL to Q7, Q7
50
18
14
165
33
28
205
41
35
250
50
43
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
D7to Q7, Q7
36
13
10
120
24
20
150
30
26
180
36
31
ns 2.0
4.5
6.0
Fig.6
tTHL/ tTLH output transition
time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
tWclock pulse width
HIGH or LOW 80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
tWparallel load pulse
width; LOW 80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
trem removal time
PL to CP, CE 100
20
17
22
8
6
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.6
tsu set-up time
Dsto CP, CE 80
16
14
11
4
3
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
tsu set-up time
CE to CP;
CP to CE
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
tsu set-up time
Dnto PL 80
16
14
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
December 1990 6
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
thhold time
Dsto CP, CE
Dnto PL
5
5
5
6
2
2
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.6
thhold time
CE to CP
CP to CE
5
5
5
−17
−6
−5
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.6
fmax maximum clock
pulse frequency 6
30
35
17
51
61
5
24
28
4
20
24
MHz 2.0
4.5
6.0
Fig.6
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
December 1990 7
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
Dn
Ds
CP
CE
PL
0.35
0.35
0.65
0.65
0.65
December 1990 8
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CE, CP to Q7, Q7
17 34 43 51 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
PL to Q7, Q7
20 40 50 60 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
D7to Q7, Q7
14 28 35 42 ns 4.5 Fig.6
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
tWclock pulse width
HIGH or LOW 16 6 20 24 ns 4.5 Fig.6
tWparallel load pulse
width; LOW 20 9 25 30 ns 4.5 Fig.6
trem removal time
PL to CP, CE 20 8 25 30 ns 4.5 Fig.6
tsu set-up time
Dsto CP, CE 20 2 25 30 ns 4.5 Fig.6
tsu set-up time
CE to CP; CP to CE 20 7 25 30 ns 4.5 Fig.6
tsu set-up time
Dnto PL 20 10 25 30 ns 4.5 Fig.6
thhold time
Dsto CP, CE; Dnto PL 7−1 9 11 ns 4.5 Fig.6
thhold time
CE to CP, CP to CE 0−7 0 0 ns 4.5 Fig.6
fmax maximum clock pulse
frequency 26 44 21 17 MHz 4.5 Fig.6
December 1990 9
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to output (Q7or Q7) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
The changing to output assumes internal Q6
opposite state from Q7.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7or Q7) propagation
delays, the parallel load to clock (CP) and clock enable (CE) removal time.
The changing to output assumes internal Q6
opposite state from Q7.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the data input (Dn) to output (Q7or Q7) propagation delays when PL is LOW.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
December 1990 10
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clock
enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)
to the clock enable input (CE).
CE may change only from HIGH-to-LOW while CP
is LOW.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL).
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
