HY5S2A6C(L/S)F / HY5S26CF
4Banks x 2M x 16bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.9 / Sep. 02
DESCRIPTION
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs,
2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld
PCs.
The Hynix HY5S2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It
is organized as 4banks of 2,097,152x16.
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ
or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave).
And the Low Power SDRAM also provides for special programmable options including Partial Array Self
Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self
Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated
by a burst terminate command or can be interrupted and replaced by a new burst Read or Write com-
mand on any cycle(This pipelined design is not restricted by a 2N rule).
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve
maximum power reduction by removing power to the memory array within each SDRAM. By using this
feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and
giving up mother-board power-line layout flexibility.
FEATURES
• Standard SDRAM Protocol
• Internal 4bank operation
• Voltage : VDD = 1.8V, VDDQ = 1.8V
• LVCMOS compatible I/O Interface
• Low Voltage interface to reduce I/O power
• Low Power Features ( HY5S26CF series can’t support these features)
- PASR(Partial Array Self Refresh)
- TCSR(Temperature Compensated Self Refresh)
- Deep Power Down Mode
• CAS latency of 1, 2, or 3
• Packages : 54ball, 0.8mm pitch FBGA
• -25 ~ 85C Operation
128M SDRAM ORDERING INFORMATION
Part Number Clock
Frequency
CAS
Latency Organization Interface Package
HY5S2A6C(L/S)F-S
HY5S26CF-S
100MHz 3 4banks x 2Mb x 16 LVCMOS
54ball FBGA
HY5S2A6C(L/S)F-B
HY5S26CF-B
66Mhz 2 4banks x 2Mb x 16 LVCMOS
* HY5xxxxxx-B Series can support 40Mhz CL1 and 33Mhz CL1.
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 3
BALL CONFIGURATION
A
B
C
D
E
F
G
H
J
54 Ball
FBGA
0.8 mm
B a l l P i t c h
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8
CLK
VSS
UDQM
A11
CKE
NC A9
A8 A7 A6
VSS A5 A4
NC
1 2 3
A
B
C
D
E
F
G
H
J
VDDQ
VDDQ
VSSQ
VSSQ
VDD
DQ0 VDD
VDD
DQ2 DQ1
DQ4 DQ3
DQ6 DQ5
DQ7LDQM
/CAS /RAS /WE
A3 A2
A0 A1 A10
/CSBA0 BA1
7 8 9
9 8 7 3 2 1
< Top View >
< Bottom View >
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 4
BALL DESCRIPTION
BALL OUT SYMBOL TYPE DESCRIPTION
F2 CLK INPUT Clock : The system clock input. All other inputs are registered
to the SDRAM on the rising edge of CLK
F3 CKE INPUT Clock Enable : Controls internal clock signal and when deacti-
vated, the SDRAM will be one of the states among power
down, suspend or self refresh
G9 CS INPUT Chip Select : Enables or disables all inputs except CLK, CKE,
UDQM and LDQM
G7,G8 BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS activ-
ity
Selects bank to be read/written during CAS activity
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
A0 ~ A11 INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
F8, F7, F9 RAS, CAS,
WE
INPUT Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
F1, E8 UDQM,
LDQM
INPUT Data Mask:Controls output buffers in read mode and masks
input data in write mode
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
DQ0 ~
DQ15
I/O Data Input/Output:Multiplexed data input/output pin
A9, E7, J9, A1,
E3, J1
VDD/VSS SUPPLY Power supply for internal circuits
A7, B3, C7, D3,
A3, B7, C3, D7
VDDQ/
VSSQ
SUPPLY Power supply for output buffers
E2, G1 NC - No connection
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 5
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM
State Machine
Row
Pre
Decoders
Column
pre
Decoders
Extended
Mode
Register
Self refresh
logic & timer
TCSR, PASR
Internal Row
Counter
Row decoders
2Mx16 Bank3
2Mx16 Bank2
2Mx16 Bank1
2Mx16 Bank0
Row decoders
Row decoders
Row decoders
Column decoders
Memory
Cell
Array
refresh
Column
Active
CLK
CKE
CS
RAS
CAS
WE
U/LDQM
Address
Registers
Column Add
Counter
Mode
Register
Address buffers
Data Out
Control
Burst
Counter
Sense AMP & I/O Gate
I/O Buffer & Logic
A0
A1
DQ0
DQ15
A11
BA1
BA0
Row
Active
bank select
CAS Latency
Burst Length
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 6
BASIC FUNCTIONAL DESCRIPTION
Mode Register
CAS Latency
Burst Type
Burst Length
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0
0 0 0 CAS Latency BT Burst Length
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
A3 Burst Type
0 Sequential
1 Interleave
A2 A1 A0
Burst Length
A3 = 0 A3=1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 7
BASIC FUNCTIONAL DESCRIPTION (Continued)
Extended Mode Register
TCSR (Temperature Compensated Self Refresh)
PASR (Partial Array Self Refresh)
BA1 BA0 A11 A10A9A8A7A6A5A4A3A2A1A0
1 0 0 0
0 0 0 0 0 TCSR PASR
A4 A3 Temperature o C
0 0 70
0 1 45
1 0 15
1 1 85
A2 A1 A0 Self Refresh Coverage
0 0 0 All Banks
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One Eighth of Total Bank (Row Address MSB=0)
1 1 0 One Sixteenth of Total Bank (Row Address 2 MSBs=0)
1 1 1 Reserved
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 8
Power Up and Initialization
Like a Synchronous DRAM, Low Power SDRAM must be powered up and initialized in a predefined manner. Power must
be applied to VDD and VDDQ(simultaneously). The clock signal must be started at the same time. After power up, an initial
pause of 200 µsec is required. And a precharge all command will be issued to the LP SDRAM. Then, 8 or more Auto refresh
cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to
program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will
be issued to program specific mode of self refresh operation(PASR & TCSR). The following these cycles, the LP SDRAM
is ready for normal opeartion.
Programming the registers
Mode Register
The mode register contains the specific mode of operation of the LP SDRAM. This register includes the selection of a burst
length(1, 2, 4, 8, Full Page), a cas latency(1, 2, or 3), a burst type. The mode register set must be done before any activate
command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register
through the execution of mode register set command.
Extended Mode Register
The extended mode register contains the specific features of self refresh opeartion of the LP SDRAM. This register includes
the selection of partial arrays to be refreshed(half array, quarter array, etc.), tempearture range of the device(85, 70, 45,
15) for reducing current consumption during self refresh. The extended mode register set must be done before any activate
command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register
through the execution of extended mode register set command.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating
CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and
the value on the A0-A11 selects the row. This row remains active for column access until a precharge command is issued
to that bank. Read and write opeartions can only be initiated on this activated bank after the minimum tRCD time is passed
from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deas-
serting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the
sarting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row
will remain active for subsequent accesses.The length of burst and the CAS latency will be determined by the values pro-
grammed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and
deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the
row will remain active for subsequent accesses.
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 9
Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge
command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular
bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is
issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10
is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop
command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst
cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued,
data ouputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command
is issued, data inputs can’t be written with no clock delay.
Clock Suspend
The Clock Suspend command is used to suspend the internal clock of DRAM. During normal access mode, CKE is keeping
High. When CKE is low, it freezes the internal clock and extends data Read and Write operations.
Power Down
The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged
and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all
of the input buffer except CKE are gated off.
Auto Refresh
The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This com-
mand must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is “Don’t
care”, because the specific address bits is generated by internal refresh address counter.
Self Refresh
The Self Refresh command is used to retain cell data in the Low Power SDRAM. In the Self Refresh mode, the Low Power
SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command ex-
cept CKE is disabled(Low). The Low Power SDRAM can accomplish an special Self Refresh operation by the specific
modes(TCSR, PASR) programmed in extended mode registers. The Low Power SDRAM can control the refresh rate by the
temperature value of TCSR (Temperature Compensated Self Refresh) and select the memory array to be refreshed by the
value of PASR(Partial Array Self Refresh). The Low Power SDRAM can reduce the self refresh current(IDD6) by using these
two modes.
Deep Power Down
The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array
of the devices. For more information, see the special operation for Low Power consumption of this data sheet.
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 10
COMMAND TRUTH TABLE
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Function CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/
AP BA Note
Mode Register Set H X L L L L X Op Code 2
Extended Mode Register Set H X L L L L X Op Code 2
No Operation H X L H H H X X
Device Deselect H X H X X X X X
Bank Active H X L L H H X Row Address V
Read H X L H L HColumn L V
Read with Autoprecharge H X L H L H XColumn H V
Write H X L H L L XColumn L V
Write with Autoprecharge H X L H L L XColumn H V
Precharge All Banks H X L L H L X X H X
Precharge selected Bank H X L L H L X X L V
Burst stop H X L H H L X X
Data Write/Output Enable H X X X X
Data Mask/Output Disable H X X V X
Auto Refresh H H L L L H X X
Self Refresh Entry H L L L L H X X
Self Refresh Exit L H H X X X X X 1
L H H H
Precharge Power Down
Entry H L H X X X X X
L H H H
Precharge Power Down Exit L H H X X X X X
L H H H
Clock Suspend Entry H L H X X X X X
L V V V
Clock Suspend Exit L H X X X
Deep Power Down Entry H L L H H L X X
Deep Power Down Exit L H X X X
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 11
CURRENT STATE TRUTH TABLE (Sheet 1 of 3)
Current State
Command Action Notes
CS RAS CAS WE BA0,BA1 A11-A0 Description
idle
L L L L OP Code Mode Register Set Set the Mode Register 14
L L L H X XAuto or Self Refresh Start Auto or Self Refresh 5
L L H L BA XPrecharge No Operation
L L H H BA Row Add. Bank Activate Activate the specified bank
and row
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 4
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 4
L H H H X XNo Operation No Operation 3
H X X X X XDevice Deselect No Operation or Power Down 3
Row
Active
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge Precharge 7
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add.
A10
Write/WriteAP Start Write : optional
AP(A10=H)
6
L H L H BA Col Add.
A10
Read/ReadAP Start Read : optional
AP(A10=H)
6
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation
Read
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge Termination Burst: Start the
Precharge
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add.
A10
Write/WriteAP Termination Burst: Start
Write(optional AP)
8,9
L H L H BA Col Add.
A10
Read/ReadAP Termination Burst: Start
Read(optional AP)
8
L H H H X XNo Operation Continue the Burst
H X X X X XDevice Deselect Continue the Burst
Write
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge Termination Burst: Start the
Precharge
10
L L H H BA Row Add. Bank Activate ILLEGAL 4
L H L L BA Col Add.
A10
Write/WriteAP Termination Burst: Start
Write(optional AP)
8
L H L H BA Col Add.
A10
Read/ReadAP Termination Burst: Start
Read(optional AP)
8,9
L H H H X XNo Operation Continue the Burst
H X X X X XDevice Deselect Continue the Burst
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 12
CURRENT STATE TRUTH TABLE (Sheet 2 of 3)
Current State
Command Action Notes
CS RAS CAS WE BA0,BA1 A11-A0 Description
Read with
Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 4,12
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 12
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 12
L H H H X XNo Operation Continue the Burst
H X X X X XDevice Deselect Continue the Burst
Write with
Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 4,12
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 12
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 12
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Precharging
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge No Operation: Bank(s) idle
after tRP
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 4,12
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 4,12
L H H H X XNo Operation No Operation: Bank(s) idle
after tRP
H X X X X XDevice Deselect No Operation: Bank(s) idle
after tRP
Row
Activating
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 4,12
L L H H BA Row Add. Bank Activate ILLEGAL 4,11,12
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 4,12
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 4,12
L H H H X XNo Operation No Operation: Row Active
after tRCD
H X X X X XDevice Deselect No Operation: Row Active
after tRCD
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 13
CURRENT STATE TRUTH TABLE (Sheet 3 of 3)
Current State
Command Action Notes
CS RAS CAS WE BA0,BA1 A11-A0 Description
Write
Recovering
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 4,13
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add.
A10
Write/WriteAP Start Write: Optional
AP(A10=H)
L H L H BA Col Add.
A10
Read/ReadAP Start Read: Optional
AP(A10=H) 9
L H H H X XNo Operation No Operation: Row Active
after tDPL
H X X X X XDevice Deselect No Operation: Row Active
after tDPL
Write
Recovering
with
Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 4,13
L L H H BA Row Add. Bank Activate ILLEGAL 4,12
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 4,12
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 4,9,12
L H H H X X No Operation No Operation: Precharge
after tDPL
H X X X X X Device Deselect No Operation: Precharge
after tDPL
Refreshing
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 13
L L H H BA Row Add. Bank Activate ILLEGAL 13
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 13
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 13
L H H H X XNo Operation No Operation: idle after tRC
H X X X X XDevice Deselect No Operation: idle after tRC
Mode
Register
Accessing
L L L L OP Code Mode Register Set ILLEGAL 13,14
L L L H X XAuto or Self Refresh ILLEGAL 13
L L H L BA XPrecharge ILLEGAL 13
L L H H BA Row Add. Bank Activate ILLEGAL 13
L H L L BA Col Add.
A10
Write/WriteAP ILLEGAL 13
L H L H BA Col Add.
A10
Read/ReadAP ILLEGAL 13
L H H H X XNo Operation No Operation: idle after 2
clock cycles
H X X X X XDevice Deselect No Operation: idle after 2
clock cycles
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 14
Note :
1. H: Logic High, L: Logic Low, X: Don’t care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending
on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don’t satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 15
CKE Enable(CKE) Truth TABLE
Note : 1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting power down mode, a NOP (or Device Deselect) command is required on the first
positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be
entered from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first
positive edge of clock after CKE goes high and is maintained for a minimum 200µsec.
Current State
CKE Command
Action Notes
Previous
Cycle
Current
Cycle CS RAS CAS WE BA0,
BA1
A11-
A0
Self Refresh
H X X X X X X X INVALID 1
L H H X X X X XExit Self Refresh with Device
Deselect 2
L H L H H H X XExit Self Refresh with No Oper-
ation 2
L H L H H L X XILLEGAL 2
L H L H L X X X ILLEGAL 2
L H L L X X X XILLEGAL 2
L L X X X X X XMaintain Self Refresh
Power
Down
H X X X X X X XINVALID 1
L H H X X X X XPower Down mode exit, all
banks idle 2
L H L X X X X XILLEGAL 2
L L X X X X X XMaintain Power Down Mode
Deep
Power
Down
H X X X X X X XINVALID 1
L H X X X X X XDeep Power Down mode exit 5
L L X X X X X XMaintain Deep Power Down
Mode
All Banks Idle
H H H X X XRefer to the idle State section
of the Current State Truth Table 3
H H L H X X 3
H H L L H X 3
H H L L L H X XAuto Refresh
H H L L L L Op Code Mode Register Set 4
H L H X X X Refer to the idle State section
of the Current State Truth Table 3
H L L H X X 3
H L L L H X 3
H L L L L H X XEntry Self Refresh 4
H L L L L L Op Code Mode Register Set
L X X X X X X XPower Down 4
Any State
other than
listed above
H H X X X X X XRefer to operations of the Cur-
rent State Truth Table
H L X X X X X XBegin Clock Suspend next cycle
L H X X X X X XExit Clock Suspend next cycle
L L X X X X X XMaintain Clock Suspend
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 16
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
Ambient Temperature TA-25 ~ 85 oC
Storage Temperature TSTG -55 ~ 125 oC
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 3.6 V
Voltage on VDD relative to VSS VDD -1.0 ~ 2.6 V
Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 2.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 1 W
Soldering Temperature . Time TSOLDER 260 . 10 oC . Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA= -25 to 85 )
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 1.65 1.8 1.95 V1
Power Supply Voltage VDDQ 1.65 1.8 1.95 V1, 2
Input High Voltage VIH 0.8*VDDQ -VDDQ+0.3 V1, 2
Input Low Voltage VIL -0.3 - 0.3 V1, 2
Note : 1. All Voltages are referenced to VSS = 0V
2. VDDQ must not exceed the level of VDD
AC OPERATING TEST CONDITION (TA= -25 to 85, VDD = 1.8V, VSS = 0V) )
Parameter Symbol Value Unit Note
AC Input High/Low Level Voltage VIH / VIL 0.95*VDDQ/0.2 V
Input Timing Measurement Reference Level Voltage Vtrip 0.5*VDDQ V
Input Rise/Fall Time tR / tF 1 ns
Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V
Output Load Capacitance for Access Time Measurement CL pF 1
Note 1
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 17
CAPACITANCE (TA=25 C, f=1MHz, HY5xxxxxxF Seires)
DC CHARACTERISTICS I (TA= -25 to 85)
Note : 1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.
2. DOUT is disabled. VOUT= 0 to 1.95V.
3. IOUT = - 0.1mA
4. IOUT = + 0.1mA
Parameter Pin Symbol
-H -/P/S/B
Unit
MinMaxMinMax
Input capacitance CLK CI1 2.5 4.0 2.5 4.0 pF
A0~A11, BA0, BA1, CKE, CS,
RAS, CAS, WE, UDQM, LDQM CI2 1.5 4.0 1.5 4.0 pF
Data input/output capacitance DQ0 ~ DQ15 CI/O 4.0 6.0 4.0 6.0 pF
Parameter Symbol Min Max Unit Note
Input Leakage Current ILI -1 1 µA 1
Output Leakage Current ILO -1.5 1.5 µA 2
Output High Voltage VOH 0.95*VDDQ - V 3
Output Low Voltage VOL - 0.2 V 4
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 18
DC CHARACTERISTICS II (TA= -25 to 85)
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
- Normal Power : HY5S2A6CF Series
- Low Power : HY5S2A6CLF Series
- Super Low Power : HY5S2A6CSF Series
- Standard Part : HY5S26CF Series
Parameter Symbol Test Condition
Speed
Unit Note
-S -B
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 55 mA 1
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns 0.5 mA
IDD2PS CKE ≤ VIL(max), tCK = ∞0.5 mA
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
10
mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 5
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns 3
mA
IDD3PS CKE ≤ VIL(max), tCK = ∞3
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
20
mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 15
Burst Mode Operating
Current IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active 55 mA 1
Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 130 mA
Self Refresh Current IDD6 CKE ≤ 0.2V mA 2
Standby Current in Deep
Power Down Mode IDD7 CKE ≤ 0.2V 50 µA
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 19
DC CHARACTERISTICS III - Normal (IDD6) (VDD=1.8V, VDDQ=1.8V, VSS=0V)
DC CHARACTERISTICS III - Low Power (IDD6) (VDD=1.8V, VDDQ=1.8V, VSS=0V)
DC CHARACTERISTICS III - Super Low Power (IDD6) (VDD=1.8V, VDDQ=1.8V, VSS=0V)
DC CHARACTERISTICS III - Standard part (IDD6) (VDD=1.8V, VDDQ=1.8V, VSS=0V)
Te m p .
( oC)
Memory Array
Unit
4 Banks 2 Banks 1 Bank
85 250 180 140 µA
70 220 150 130 µA
-25~45 160 120 90 µA
Te m p .
( oC)
Memory Array
Unit
4 Banks 2 Banks 1 Bank
85 220 160 120 µA
70 200 130 100 µA
-25~45 130 100 80 µA
Te m p .
( oC)
Memory Array
Unit
4 Banks 2 Banks 1 Bank
85 180 140 100 µA
70 170 110 80 µA
-25~45 100 80 70 µA
Te m p .
( oC)
Memory Array
Unit
4 Banks
-25~85 < 450 µA
* HY5S2A6CF Series
* HY5S2A6CLF Series
* HY5S2A6CSF Series
* HY5S26CF Series
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 20
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to
the parameter.
2. Access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 0.2v. If tR > 1ns, then
(tR/2-0.5)ns should be added to the parameter.
Parameter Symbol
SB
Unit Note
Min Max Min Max
System Clock
Cycle Time
CAS Latency=3 tCK3 10 1000 15 1000 ns
CAS Latency=2 tCK2 12 15 ns
Clock High Pulse Width tCHW 3 - 3.5 - ns 1
Clock Low Pulse Width tCLW 3 - 3.5 - ns 1
Access Time From
Clock
CAS Latency=3 tAC3 - 7 - 9 ns 2
CAS Latency=2 tAC2 - - - 9 ns
Data-out Hold Time tOH 3 - 3 - ns
Data-Input Setup Time tDS 2 - 2 - ns 1
Data-Input Hold Time tDH 1 - 1 - ns 1
Address Setup Time tAS 2 - 2 - ns 1
Address Hold Time tAH 1 - 1 - ns 1
CKE Setup Time tCKS 2 - 2 - ns 1
CKE Hold Time tCKH 1 - 1 - ns 1
Command Setup Time tCS 2 - 2 - ns 1
Command Hold Time tCH 1 - 1 - ns 1
CLK to Data Output in Low-Z Time tOLZ 1 - 1 - ns
CLK to Data Output
in High-Z Time
CAS Latency=3 tOHZ3 3 6 3 9 ns
CAS Latency=2 tOHZ2 3 6 3 9 ns
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 21
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Note : 1. A new command can be given tRC after self refresh exit.
Parameter Symbol
SB
Unit Note
Min Max Min Max
RAS Cycle Time tRC 90 - 90 - ns
RAS to CAS Delay tRCD 30 - 30 - ns
RAS Active Time tRAS 60 100K 60 100K ns
RAS Precharge Time tRP 30 - 30 - ns
RAS to RAS Bank Active Delay tRRD 20 - 30
- ns
CAS to CAS Delay tCCD 1 - 1 - tCK
Write Command to Data-In Delay tWTL 0 - 0
- tCK
Data-in to Precharge Command tDPL 2 - 2 - tCK
Data-In to Active Command tDAL 2clk + 30ns
DQM to Data-Out Hi-Z tDQZ 2 - 2 - tCK
DQM to Data-In Mask tDQM 0 - 0 - tCK
MRS to New Command tMRD 2 - 2 - tCK
Precharge to Data
Output High-Z
CAS Latency=3 tPROZ3 3 -
3 -
tCK
CAS Latency=2 tPROZ2 2 2 tCK
Power Down Exit Time tDPE 1 - 1 - tCK
Self Refresh Exit Time tSRE 1 - 1 - tCK 1
Refresh Time tREF - 64 - 64 ms
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 22
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole mem-
ory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having /CS and /WE held low with /RAS and /CAS high at the rising edge of the
clock, while CKE is low. The following diagram illustrates deep power down mode entry.
Current State Command CKEn-1 CKEn CS RAS CAS WE
Idle Deep Power
Down Entry
H L L H H L
Deep Power
Down
Deep Power
Down Exit
L H X X X X
CLK
CKE
CS
RAS
CAS
WE
tRP
Precharge
if needed
Deep Power Down Entry
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 23
Deep Power Down Mode (Continued)
Deep Power Down Mode Exit Sequence
The Deep Power Down mode is exited by asserting CKE high.
After the exit, the following sequence is needed to enter a new command.
1. Maintain NOP input conditions for a minimum of 200µsec
2. Issue precharge commands for all banks of the device
3. Issue 8 or more auto refresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extended mode register
The following timing diagram illustrates deep power down mode exit sequence.
CLK
CKE
CS
RAS
CAS
WE
Deep Power Down
exit
All banks
precharge
Auto
refresh
Auto
refresh
Mode
Register
Set
Extended
Mode
Register
Set
New
Command
Accepted
Here
200µstRP tRC
HY5S2A6C(L/S)F / HY5S26CF
Rev. 0.9 / Sep. 02 24
PACKAGE INFORMATION
54 Ball 0.8mm pitch 8.3mm x 10.5mm FBGA (HY5xxxxxxF Series)
10.50
6.40
0.80
8.30
0.80
6.40
1.070
0.340
0.450
