C8051F127 50 MIPS, 128 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 C Core - 10-Bit ADC - 1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (3 C) - Memory - 8-Bit ADC - - 1 LSB INL; no missing codes Programmable throughput up to 500 ksps 8 external inputs Programmable amplifier gain: 4, 2, 1, 0.5 - Can synchronize outputs to timers for jitter-free waveform generation Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector - On-Chip JTAG Debug & Boundary Scan - 8448 bytes data RAM 128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface Digital Peripherals Two 12-Bit DACs - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 50 MIPS throughput with 50 MHz system clock Expanded interrupt handler 32 port I/O; all are 5 V tolerant Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using a timer or PCA Clock Sources On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Real-time instruction trace buffer IEEE1149.1 compliant boundary scan - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation On-chip programmable PLL: up to 50 MHz External oscillator: Crystal, RC, C, or Clock Supply Voltage: 2.7 to 3.6 V - Typical operating current: 25 mA at 50 MHz Typical stop mode current: <0.1 uA 64-Pin TQFP Temperature Range: -40 to +85 C VDD VDD VDD DGND DGND DGND Digital Power AV+ AGND Analog Power TCK TMS TDI TDO Boundary Scan JTAG Logic Debug HW XTAL1 XTAL2 VDD Monitor WDT External Oscillator Circuit System Clock Internal 2% Oscillator M/N PLL VREF VREF DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0CP1+ CP1- SFR Bus 8 256 Byte Branch Target Buffer Prefetch HW UART0 UART1 C R O S S B A R SMBus SPI Bus PCA Timers 0, 1, 2, 4 32 Reset RST MONEN 8 0 5 1 C o r e 128 kB FLASH 256 Byte RAM Timer 3 P0, P1, P2, P3 Latches Prog Gain TEMP SENSOR P0.0 P1 Drv P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P0.7 P1.7/AIN1.7 P2.7 P3.7 REFADC VDD 8 kB XRAM ADC 500 ksps (8-Bit) Prog Gain A M U X 8:1 External Data Memory Bus Bus Control C T L REFADC A M U X P0 Drv ADC 100 ksps (10-Bit) Address Bus Data Bus CP0 A d d r D a t a P4 Latch P4 DRV P5 Latch P5 DRV P6 Latch P6 DRV P7 Latch P7 DRV CP1 Precision Mixed Signal Copyright (c) 2004 by Silicon Laboratories 6.15.2004 C8051F127 50 MIPS, 128 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 50 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz Supply Current Oscillator off; VDD Monitor Enabled (shutdown) Oscillator off; VDD Monitor Disabled Clock Frequency Range INTERNAL CLOCKS Oscillator Frequency PLL Frequency A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate D/A CONVERTERS Resolution Differential Nonlinearity Guaranteed Monotonic Output Settling Time COMPARATORS Supply Current (each comparator) Response Time (CP+) - (CP-) = 100 mV MIN TYP MAX UNITS 3.6 50 V mA mA A A A MHz 25.0 50 MHz MHz 1 1 bits LSB LSB dB 100 ksps 1 10 bits LSB S 1.5 4.0 A S 2.7 25 0.5 16 10 <0.1 DC 24.0 48 24.5 49 10 59 61 12 C8051F120DK Development Kit Package Information D D1 MIN NOM MAX (mm) (mm) (mm) A E1 E - 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 64 PIN 1 DESIGNATOR 1 A2 e A b Precision Mixed Signal - 0.17 0.22 0.27 D - 12.00 - D1 - 10.00 - e - 0.50 - E - 12.00 - E1 - 10.00 - A1 Copyright (c) 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders