1
©2000 Integrated Device Technology, Inc.
JANUARY 2001
DSC-2692/15
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
Functional Block Diagram
Features
◆◆
◆◆
◆High-speed access
– Military: 25/35/55/100ns (max.)
– Commercial: 20/25/35/55/100ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
◆◆
◆◆
◆MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
◆◆
◆◆
◆On-chip port arbitration logic (IDT7132 only)
◆◆
◆◆
◆BUSY output flag on IDT7132; BUSY input on IDT7142
◆◆
◆◆
◆Battery backup operation —2V data retention (LA only)
◆◆
◆◆
◆TTL-compatible, single 5V ±10% power supply
◆◆
◆◆
◆Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available for
selected speeds
OEL
CEL
R/WL
I/OOL-I/O7L
BUSYL(1,2)
A10L
A0L
CEL
OEL
R/WL
CER
OER
R/WR
OER
CER
R/WR
I/OOR-I/O7R
BUSYR(1,2)
A10R
A0R
I/O
Control I/O
Control
Address
Decoder Address
Decoder
MEMORY
ARRAY
ARBITRATION
LOGIC
2692 drw 01
m
11 11
2
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.
The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM
or as a “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE”
Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate control,
address, and l/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
148
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IDT7132/
7142
PorC
P48-1(4)
&
C48-2(4)
48-Pin
DIP
Top
View(5)
2692 drw 02
GND
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
I/O7L
I/O6L
I/O5L
I/O4L
CER
CEL
OEL
A0L
BUSYL
R/WLR/WR
BUSYR
VCC
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O3L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
A10L A10R
,
IDT7132/42L48 or F
L48-1(4)
&
F48-1(4)
48-Pin LCC/ Flatpack
Top View(5)
INDEX
65432148 47 46 45 44 43
19 20 21 22 23 25 26 27 28 29 3024
42
41
40
39
38
37
36
35
34
33
32
31
7
8
9
10
11
12
13
14
15
16
17
18
2692 drw 03
GND
CER
CEL
OEL
A0L
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O3L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
BUSYL
R/WL
R/WR
BUSYR
VCC
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
I/O7L
I/O6L
I/O5L
I/O4LA10L
A10R
,
Capacitance(1) (TA = +25°C,f = 1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
Symbol Parameter Conditions(2) Max. Unit
CIN Inp u t Capac i tan ce V IN = 3dV 11 pF
COUT Outp ut Cap ac itanc e V OUT = 3dV 11 pF
2692 tbl 00
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
3
IDT7132/42J
J52-1(4)
52-Pin PLCC
Top View(5)
INDEX
N/C
GND
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/O7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O3L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
2692 drw 04
A
10L
V
CC
A
10R
I/O
6R
A
0L
OE
L
N/C
CE
L
CE
R
N/C
BUSY
L
R/W
L
R/W
R
BUSY
R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
I/O
7L
I/O
6L
I/O
5L
I/O
4L
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations(1,2,3) (con't.)
Symbol Rating Commercial
& Industrial Military Unit
VTERM(2) Te rminal Vo ltag e
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0 V
TBIAS Temperature
Under Bias -55 to +125 -65 to +135 oC
TSTG Storage
Temperature -65 to +150 -65 to +150 oC
IOUT DC Outp ut
Current 50 50 mA
2692 tbl 01
Grade Ambient
Temperature GND Vcc
Military -55OC to +125OC0V5.0V
+ 10%
Commercial 0OC to + 70OC0V5.0V
+ 10%
Industrial -40OC to + 85OC0V5.0V
+ 10%
26 92 t bl 02
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Inp u t Hig h Vo l tag e 2. 2 ____ 6.0(2) V
VIL Inp u t Lo w Vo l tag e -0. 5(1) ____ 0.8 V
26 92 t bl 03
4
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5,8) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC Package only
3. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Not available in DIP packages.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20(2)
7142X20(2)
Com'l Only
7132X25(7)
7142X25(7)
Com 'l &
Military
7132X35
7142X35
Com 'l &
Military
Sym bo l P arameter Test Con diti on Ver sion Typ. M ax. Typ. Max. T yp. Max. Uni t
ICC Dynamic Operating Current
(Bo th Po rts Active ) CEL = CER = VIL,
Outputs Disabled
f = fMAX(3)
COM'L SA
LA 110
110 250
200 110
110 220
170 80
80 165
120 mA
MIL &
IND SA
LA ____
____
____
____ 110
110 280
220 80
80 230
170
ISB1 Standb y Curre nt
(Bo th Po rts - TTL
Lev el Inpu ts )
CEL = CER = VIH,
f = fMAX(3) COM'L SA
LA 30
30 65
45 30
30 65
45 25
25 65
45 mA
MIL &
IND SA
LA ____
____
____
____ 30
30 80
60 25
25 80
60
ISB2 Standb y Curre nt
(One P ort - TTL
Lev el Inpu ts )
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled
f=fMAX(3)
COM'L SA
LA 65
65 165
125 65
65 150
115 50
50 125
90 mA
MIL &
IND SA
LA ____
____
____
____ 65
65 160
125 50
50 150
115
ISB3 Full Stand by Current (Bo th
Ports - All
CM OS Le ve l Inp uts )
CEL and CER > VCC -0.2V
VIN > VCC -0.2V or VIN < 0.2V, f = 0(4) COM'L SA
LA 1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
4mA
MIL &
IND SA
LA ____
____
____
____ 1.0
0.2 30
10 1.0
0.2 30
10
ISB4 Full Standb y Current
(One P ort - Al l
CM OS Le ve l Inp uts )
CE"A" < 0.2V andCE"B" > VCC -0.2V(6)
VIN > VCC - 0.2V o r V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L SA
LA 60
60 155
115 60
60 145
105 45
45 110
85 mA
MIL &
IND SA
LA ____
____
____
____ 60
60 155
115 45
45 145
105
2692 tbl 04a
7132X55
7142X55
Com 'l &
Military
7132X100
7142X100
Com 'l &
Military
Sym bo l P arameter Test Con di tion Ver sion Typ. Max. Typ. Max. Uni t
ICC Dynami c Op e rating
Current
(Bo th Po rts Active )
CEL = CER = VIL,
Outputs Disabled
f = fMAX(3)
COM'L SA
LA 65
65 155
110 65
65 155
110 mA
MIL &
IND SA
LA 65
65 190
140 65
65 190
140
ISB1 Standb y Curre nt
(Bo th Po rts - TTL
Lev el Inpu ts )
CEL = CER = VIH,
f = fMAX(3) COM'L SA
LA 20
20 65
35 20
20 55
35 mA
MIL &
IND SA
LA 20
20 65
45 20
20 65
45
ISB2 Standb y Curre nt
(One P ort - TTL
Lev el Inpu ts )
CE"A" = VIL and CE"B" = VIH(6)
Active Port Outputs Disabled
f=fMAX(3)
COM'L SA
LA 40
40 110
75 40
40 110
75 mA
MIL &
IND SA
LA 40
40 125
90 40
40 125
90
ISB3 Full Standb y Current
(Both Ports - All
CM OS Le ve l Inp uts )
CEL and CER > VCC -0.2V
VIN > VCC -0.2V or VIN < 0.2V, f = 0(4) COM'L SA
LA 1.0
0.2 15
41.0
0.2 15
4mA
MIL &
IND SA
LA 1.0
0.2 30
10 1.0
0.2 30
10
ISB4 Full Standb y Current
(One P ort - Al l
CM OS Le ve l Inp uts )
CE"A" < 0.2V and CE"B" > VCC -0. 2V(6)
VIN > VCC - 0.2V o r V IN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L SA
LA 40
40 100
70 40
40 95
70 mA
MIL &
IND SA
LA 40
40 110
85 40
40 110
80
2692 tbl 04b
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
5
Data Retention Characteristics (LA Version Only)
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
NOTE:
1. At Vcc < 2.0V leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
Data Retention Waveform
VCC
CE
4.5V 4.5V
DATA RETENTION MODE
tCDR tR
VIH VIH
VDR
VDR 2.0V
2692 drw 05
≥
,
Symbol Parameter Test Conditions
7132SA
7142SA 7132LA
7142LA
UnitMin. Max. Min. Max.
|ILI|Input Leakage Current(1) VCC = 5.5V,
VIN = 0V to VCC
___ 10 ___ 5µA
|ILO| Outp ut Le akag e Curre nt VCC = 5.5V,
CE = VIH, VOUT = 0V to VCC
___ 10 ___ 5µA
VOL Outp ut Lo w Voltag e IOL = 4mA ___ 0.4 ___ 0.4 V
VOL Op e n Drain Outp ut
Lo w Vo ltag e (BUSY, INT)IOL = 16mA ___ 0.5 ___ 0.5 V
VOH Outp ut Hig h Vo ltage IOH = -4mA 2.4 ___ 2.4 ___ V
2692 tbl 05
Symbol Parameter Test Condition Min. Typ.(1) Max. Unit
VDR VCC fo r D ata Rete nti o n V CC = 2. 0V 2.0 ___ ___ V
ICCDR Data Re te ntio n Curre nt CE
> VCC -0.2V
VIN > VCC -0. 2V o r
Mil. & Ind. ___ 100 4000 µA
Com'l. ___ 100 1500 µA
tCDR(3) Chip De s e le c t to Data Re te ntio n Time VIN < 0.2V 0___ ___ ns
tR(3) Op eratio n Re co ve ry Time tRC(2) ___ ___ ns
2692 tbl 06
6
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
5V
1250Ω
30pF*
775Ω
DATAOUT
5V
1250Ω
775Ω5pF*
DATAOUT
2692 drw 06
*100pF for 55 and 100ns versions
5V
1250Ω
30pF*
BUSY or INT
*100pF for 55 and 100ns versions
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig
Figure 1. AC Output Test Load
Figure 3. BUSY and INT
AC Output Test Load
AC Test Conditions
Inp ut P ul se Le v e ls
Inp ut Ri s e /Fall Tim e s
Inp ut Timi ng Re fe re nc e Le v e l s
Outp ut Re fe re nc e Le v e l s
Output Load
GND to 3.0V
5ns Max .
1.5V
1.5V
F ig ures 1, 2, and 3
2692 tbl 07
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,5)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20(2)
7142X20(2)
Com'l Only
7132X25(2)
7142X25(2)
Com 'l &
Military
7132X35
7142X35
Com 'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
RE AD CYCLE
tRC Read Cyc le Time 20 ____ 25 ____ 35 ____ ns
tAA Address Access Time ____ 20 ____ 25 ____ 35 ns
tACE Chip Enable Acce ss Time ____ 20 ____ 25 ____ 35 ns
tAOE Output Enable Access Time ____ 11 ____ 12 ____ 20 ns
tOH Output Hold from Address Change 3 ____ 3____ 3____ ns
tLZ Outp ut Low-Z Time (1,4) 0____ 0____ 0____ ns
tHZ Outp ut Hig h-Z Time(1,4) ____ 10 ____ 10 ____ 15 ns
tPU Chi p Enable to P o wer Up Ti me(4) 0____ 0____ 0____ ns
tPD Chi p Dis ab le to Po we r Do wn Tim e (4) ____ 20 ____ 25 ____ 35 ns
2 692 tbl 08 a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
UnitSymbol Parameter Min. Max. Min. Max.
RE AD CYCLE
tRC Read Cyc le Time 55 ____ 100 ____ ns
tAA Address Access Time ____ 55 ____ 100 ns
tACE Chip Enable Acce ss Time ____ 55 ____ 100 ns
tAOE Outp ut Enab le Ac ce ss Time ____ 25 ____ 40 ns
tOH Output Hold from Ad dre ss Change 3 ____ 10 ____ ns
tLZ Output Lo w-Z Time (1,4) 5____ 5____ ns
tHZ Outp ut Hig h-Z Time (1,4) ____ 25 ____ 40 ns
tPU Chip Enab le to Po wer Up Time(4) 0____ 0____ ns
tPD Chi p Disab le to Po wer Do wn Time (4) ____ 50 ____ 50 ns
2692 tbl 08b
8
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 2, Either Side(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
Timing Waveform of Read Cycle No. 1, Either Side(1)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATA VALID
tAA
tOH
DATA VALID
2692 drw 07
tBDDH(2,3)
BUSYOUT
CE
tHZ(5)
tLZ(4)
tPD(3)
VALID DATA
tPU
50%
OE
DATAOUT
CURRENT
ICC
ISS 50%
2692 drw 08
tLZ(4)
tHZ(5)
tACE
tAOE(3)
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5,6)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Symbol Parameter
7132X20(2)
7142X20(2)
Com'l Only
7132X25(2)
7142X25(2)
Com 'l &
Military
7132X35
7142X35
Com 'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
tWC Write Cycle Time(3) 20 ____ 25 ____ 35 ____ ns
tEW Chip Enab le to End -of-Write 15 ____ 20 ____ 30 ____ ns
tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns
tAS Address Set-up Time 0 ____ 0____ 0____ ns
tWP Write Pulse Width(4) 15 ____ 15 ____ 25 ____ ns
tWR Write Recove ry Time 0 ____ 0____ 0____ ns
tDW Data Vali d to E nd -o f-W rite 10 ____ 12 ____ 15 ____ ns
tHZ Outp ut Hig h-Z Time(1) ____ 10 ____ 10 ____ 15 ns
tDH Data Hold Time 0 ____ 0____ 0____ ns
tWZ Write E nable to Outp ut in Hig h-Z(1) ____ 10 ____ 10 ____ 15 ns
tOW O utput A c ti v e fro m E nd-o f-Wr ite(1) 0____ 0____ 0____ ns
2692 t bl 09
Symbol Parameter
7132X55
7142X55
Com 'l &
Military
7132X100
7142X100
Com 'l &
Military
UnitMin. Max. Min. Max.
WRI T E CYCLE
tWC Write Cycle Time(3) 55 ____ 100 ____ ns
tEW Chip Enab le to End -of-Write 40 ____ 90 ____ ns
tAW Address Valid to End-of-Write 40 ____ 90 ____ ns
tAS Add re ss Se t-up Time 0 ____ 0____ ns
tWP Write Pulse Width(4) 30 ____ 55 ____ ns
tWR Write Recovery Time 0 ____ 0____ ns
tDW Data Val id to E nd -o f-Write 20 ____ 40 ____ ns
tHZ Output High-Z Time(1) ____ 25 ____ 40 ns
tDH Data Hold Time 0 ____ 0____ ns
tWZ Write Enable to Output in Hig h-Z(1) ____ 30 ____ 40 ns
tOW Outp ut A c tiv e fro m End-o f-Wri te(1) 0____ 0____ ns
2692 tbl 10
10
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
tWC
ADDRESS
CE
R/W
DATAIN
tAS(6) tEW(2) tWR(3)
tDW tDH
tAW
2692 drw 10
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
tWC
ADDRESS
OE
CE
R/W
DATAOUT
DATAIN
tAS(6)
tOW
tDW tDH
tAW
tWP(2)
tHZ(7)
(4) (4)
tWZ(7)
tHZ(7)
2692 drw 09
tWR(3)
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,8)
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(1)
7142X20
(1)
Com'l Only
7132X25
(2)
7142X25
(2)
Com'l &
Military
7132X35
7142X35
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY
Tim ing (For Master IDT7132 Only)
t
BAA
BUSY
Access Time from Address
____
20
____
20
____
20 ns
t
BDA
BUSY
Disable Time from Address
____
20
____
20
____
20 ns
t
BAC
BUSY
Access Time from Chip Enable
____
20
____
20
____
20 ns
t
BDC
BUSY
Disable Time from Chip Enable
____
20
____
20
____
20 ns
t
WDD
Write Pulse to Data De lay
(2)
____
50
____
50
____
60 ns
t
WH
Write Ho ld A fter
BUSY
(6)
12
____
15
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
35
____
35
____
35 ns
t
APS
A rb itra tion P rio rity Se t-up Tim e
(3)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(4)
____
25
____
35
____
35 ns
BUSY
Tim ing (For Slave IDT7142 Only)
t
WB
Write to
BUSY
Inp ut
(5)
0
____
0
____
0
____
ns
t
WH
Write Ho ld A fter
BUSY
(6)
12
____
15
____
20
____
ns
t
WDD
Write Pulse to Data De lay
(2)
____
40
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
30
____
35
____
35 ns
2692 tbl 11a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Unit
BUSY
Timing (For Master IDT7132 Only)
t
BAA
BUSY
Access Time from Address
____
30
____
50 ns
t
BDA
BUSY
Disable Time from Address
____
30
____
50 ns
t
BAC
BUSY
Access Time from Chip Enable
____
30
____
50 ns
t
BDC
BUSY
Disable Time from Chip Enable
____
30
____
50 ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
WH
W rite Ho ld A fter
BUSY
(6)
20
____
20
____
ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
t
APS
A rb itratio n P rio rity S e t-up Tim e
(3)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(4)
____
50
____
65 ns
BUSY
Timing (For Slave IDT7142 Only)
t
WB
Write to
BUSY
Inp ut
(5)
0
____
0
____
ns
t
WH
W rite Ho ld A fter
BUSY
(6)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(2)
____
80
____
120 ns
t
DDD
Write Data Valid to Read Data Delay
(2)
____
55
____
100 ns
2692 tbl 11b
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(4)
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
BUSY"B"
2692 drw 12
R/W"A"
tWP
tWH(1)
tWB
R/W"B" (2)
(3)
,
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
DATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
(1)
2692 drw 11
t
BAA
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
Truth Tables
Table I. Non-Contention Read/Write Control(4)
NOTES:
1. A0L - A10L ≠ A0R - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and t DDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
tAPS(2)
ADDR
"A" and "B" ADDRESSES MATCH
tBAC tBDC
CE"B"
CE"A"
BUSY"A"
2692 drw 13
BUSY"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
tAPS(2)
ADDR"A"
ADDR"B"
2692 drw 14
tBAA tBDA
tRC or tWC
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Left or Right Port(1)
R/WCE OE D0-7 Function
X H X Z P o rt Dis ab l e d and in P owe r-Do wn M o de , ISB2 or ISB4
XHX ZCE
R = CE
L = VIH, Power-Down Mode, ISB1 or ISB3
LLXDATA
IN D ata o n Po rt Writte n into Me mo ry (2)
HLLDATA
OUT Data in Memory Output on Port(3)
X L H Z High Impedance Outputs
2692 tbl 12
14
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
The BUSY outputs on the IDT7132 RAM master are totem-pole type
outputs and do not require pull-up resistors to operate. If these RAMs are
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic,
one master part is used to decide which side of the SRAM array will
receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master,
use the BUSY signal as a write inhibit signal. Thus on the IDT7132/
IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132),
and the BUSY pin is an input if the part is a Slave (IDT7142) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Table II Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7132 (master). Both are inputs for
IDT7142 (slave). BUSYX outputs on the IDT7132 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
Functional Description
The IDT7132/IDT7142 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7132/IDT7142 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a busy indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
2692 drw 15
MASTER
Dual Port
SRAM
BUSYLBUSYR
CE
MASTER
Dual Port
SRAM
BUSYLBUSYR
CE
SLAVE
Dual Port
SRAM
BUSYLBUSYR
CE
SLAVE
Dual Port
SRAM
BUSYLBUSYR
CE
BUSYLBUSYR
DECODER
5V 5V
270Ω
270Ω
Inputs Outputs
Function
CELCERAOL-A10L
AOR-A10R
BUSYL(1) BUSYR(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhibit(3)
2 692 tbl 13
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
15
Ordering Information
IDT XXXX A999 A A
Device Type Power Speed Package Process/
Temperature
Range
BLANK
I
(1)
B
Commercial (0
°
Cto+70
°
C)
Industrial (-40
°
Cto+85
°
C)
Military (-55
°
Cto+125
°
C)
Compliant to MIL-PRF-38535 QML
P
C
J
L48
F
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20
25
35
55
100
Commercial PLCC Only
Commercial & Military
Commercial & Military
Commercial & Military
Commercial & Military
LA
SA Low Power
Standard Power
7132
7142 16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
Speed in nanoseconds
2692 drw 16
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/24/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
6/8/99: Changed drawing format
8/26/99: Page 14 Changed Busy Logic and Width Expansion copy
11/10/99: Replaced IDT logo
1/12/00: Pages 1 and 2 Moved full "Description" to page 2 and adjusted page layouts
Page 1 Added "(LAonly)" to paragraph
Page 2 Fixed P48-1 body package description
Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Page 6 Added asteriks to Figures 1 and 3 in drw 06
Page 14 Corrected part numbers
Changed ±500mV to 0mV in notes
