MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD16633B
312 OUTPUT TFT-LCD SORCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALES)
1998©
Document No. S13214EJ2V0DS00 (2nd edition)
Date Published July 1998 N CP(K)
Printed in Japan
DATA SHEET
The
µ
PD16633B is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values
γ
-corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as 9.8 VP-P, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source
driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 3.0
V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 9.8 VP-P min. (@VDD2 = 10.0 V)
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V)
• 312 outputs
• Apply for only dot inversion
• Display data inversion function (POL2 terminal.)
• Single bank arrangement is possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number Package
µ
PD16633BN-××× TCP (TA B package)
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
2
µ
µµ
µ
PD16633B
1. BLOCK DIAGRAM
50-bit bidirectional shift register
C1C2C51 C52
STHL
VDD1
VSS1CLK
STB
Data register
Latch
POL
Level shifter VDD2
D/A converter
V0-V9
Voltage follower output
VSS2
S1S2S3S312
STHR
R/L
D00-05
D10-15
D20-25
D30-35
D40-45
D50-55
POL2
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
6-bit D/A converter
Multi-
plexer
V
0
V
4
V
5
V
9
5
5
S
1
S
2
S
311
S
312
POL
3
µ
µµ
µ
PD16633B
3. PIN CONFIGURATION (
µ
µµ
µ
PD16633BN-×××
××××××
×××) (Copper Plated surface)
VSS2
VDD2
VSS1
R/L
POL
STB
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
STHL
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
CLK
STHR
D30
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
POL2
TEST
VDD1
VDD2
VSS2
S312
S311
S310
S309
S4
S3
S2
S1
Caution This figure does not specify the TCP package.
4
µ
µµ
µ
PD16633B
4. PIN FUNCTIONS
Pin Sy m bol Pin Name Descript i on
S1 to S312 Driver output The D/A converted 64-gray-scale anal og voltage is output.
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Display data input The display data is input with a width of 36 bit s, vi z., the gray scale data (6 bi t s)
by 6 dots (2 pi x el s).
DX0: LSB, DX5: MSB
R/L Shift di rection c ontrol
input These refer t o the start pulse i nput /output pi ns when driver I Cs are connected in
casc ade. The shift di rections of the shift regi sters are as follows.
R/L = H: STHR i nput, S1 →S312, STHL out put
R/L = L : STHL input, S312 →S1, STHR output
STHR Right shift start pul se
input/output R/L = H: Bec om es the start puls e i nput pin.
R/L = L : Becom es the s t art pulse out put pin.
STHL Left shift start pulse
input/output R/L = H: Bec om es the start puls e output pin.
R/L = L : Becom es the s t art pulse i nput pi n.
CLK Shift clock i nput Refers to t he shift regi ster’s shift clock input. The di splay dat a i s incorporat ed i nto
the data regis ter at the ri sing edge. A t the ris i ng edge of the 52nd cl ock after the
start pul se input, the start pulse out put reaches t he hi gh l evel, t hus becomi ng t he
start pul se of the next-lev el dri ver. The ini t i al -l evel driv er’ s 52nd cloc k becomes
valid as the next-l evel driver’ s start pulse i s input. I f 54th cl ock pulses are input
after input of the start puls e, input of di splay dat a i s halted aut om atical l y . The
contents of the shift regi ster are c l eared at the STB ’ s ri sing edge.
STB Latch input The contents of the data regist er are transferred to the lat ch circ ui t at the ri sing
edge. And, at the falling edge, t he gray scale volt age is supplied to t he driver. It
is necessary to ensure input of one pulse per hori z ontal period.
POL Polarity input POL = L ; The S2n–1 out put uses V0 to V4 as the ref erence supply;
The S2n output uses V5 to V9 as the ref erence supply.
POL = H; The S 2n–1 output uses V5 to V9 as the referenc e supply;
The S2n output uses V0 to V4 as the ref erence supply.
POL2 Data inv ers i on POL2 = H : Display data is i nverted.
POL2 = L : Displ ay data is not invert ed.
V0 to V9
γ
-correct ed power
supplies I nput the
γ
-correct ed power s uppl i es from out side by using operational am pl i fier.
Make sure to maintai n the foll owi ng rel at i onships. Duri ng the gray s c al e voltage
output, be sure to keep the gray s c al e l evel power suppl y at a constant l evel.
VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2
TEST Test pin TEST = H or Open: Standard m ode
TEST = L: Test mode Please i nput “H” l evel.
VDD1 Logic power suppl y 3.3 V ± 0.3 V
VDD2 Driver power suppl y 10.0 V to 13.5 V
VSS1 Logic ground Grounding
VSS2 Driver ground Grounding
5
µ
µµ
µ
PD16633B
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.47
µ
µµ
µ
F bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01
µ
µµ
µ
F is also advised between the
γ
γγ
γ
-corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
6
µ
µµ
µ
PD16633B
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios
between the LCD panel’s
γ
-corrected voltages and V0’ to V63’ and V0” to V63” are roughly equal; and their respective
resistance values are as shown on page 9. Among the 5-by-2
γ
-corrected voltages, input gray scale voltages of the
same polarity with respect to the common voltage, for the respective five
γ
-corrected voltages of V0 to V4 and V5 to
V9.Figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and
γ
-corrected voltages V0 to V9 and the input data. Be sure to maintain the
voltage relationships of VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2.
Figures 2-1 and 2-2 show the relationship between the input data and the output data. Table 1 shows the
resistance values of the resistor strings.
This driver IC is designed for single-sided mounting. Therefore, please do not use it for
γ
-corrected power supply
level inversion in double-sided mounting. Because the current flowing through ladder resistors r0 to r62 is small, its
use for double-sided mounting impairs the IC’s stable operation when the level of the
γ
-corrected power supply
terminal is inverted thus causing display failures.
Figure 1. Relationship Between Input Data and Output Voltage
3F3830282018100800 Input data (HEX)
(POL2 = L)
40 (Invalid)
0.1 V V
9
V
SS2
0.1 V V
0
V
DD2
V
1
V
2
V
3
V
4
V
COM
V
5
V
6
V
7
V
8
7
µ
µµ
µ
PD16633B
Figure 2-1. Relationship Between Input Data and Output Voltage: VDD2 > V0 > V1 > V2 > V3 > V4 > V5
Data DX5 DX4 DX3 DX2 DX1 DX0 Output Voltage
00H
01H
02H
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0’
V1’
V2’
V3’
V4’
V5’
V6’
V7’
V0
V1 + (V0 – V1) × 4500/5300
V1 + (V0 – V1) × 3700/5300
V1 + (V0 – V1) × 2900/5300
V1 + (V0 – V1) × 2200/5300
V1 + (V0 – V1) × 1500/5300
V1 + (V0 – V1) × 900/5300
V1 + (V0 – V1) × 400/5300
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V8’
V9’
V10’
V11’
V12’
V13’
V14’
V15’
V1
V2 + (V1 – V2) × 3600/4000
V2 + (V1 – V2) × 3300/4000
V2 + (V1 – V2) × 3000/4000
V2 + (V1 – V2) × 2700/4000
V2 + (V1 – V2) × 2400/4000
V2 + (V1 – V2) × 2200/4000
V2 + (V1 – V2) × 2000/4000
10H
11H
12H
13H
14H
15H
16H
17H
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V16’
V17’
V18’
V19’
V20’
V21’
V22’
V23’
V2 + (V1 – V2) × 1800/4000
V2 + (V1 – V2) × 1600/4000
V2 + (V1 – V2) × 1400/4000
V2 + (V1 – V2) × 1300/4000
V2 + (V1 – V2) × 1200/4000
V2 + (V1 – V2) × 1100/4000
V2 + (V1 – V2) × 1000/4000
V2 + (V1 – V2) × 900/4000
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V24’
V25’
V26’
V27’
V28’
V29’
V30’
V31’
V2 + (V1 – V2) × 800/4000
V2 + (V1 – V2) × 700/4000
V2 + (V1 – V2) × 600/4000
V2 + (V1 – V2) × 500/4000
V2 + (V1 – V2) × 400/4000
V2 + (V1 – V2) × 300/4000
V2 + (V1 – V2) × 200/4000
V2 + (V1 – V2) × 100/4000
20H
21H
22H
23H
24H
25H
26H
27H
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V32’
V33’
V34’
V35’
V36’
V37’
V38’
V39’
V2
V3 + (V2 – V3) × 2600/2700
V3 + (V2 – V3) × 2500/2700
V3 + (V2 – V3) × 2400/2700
V3 + (V2 – V3) × 2300/2700
V3 + (V2 – V3) × 2200/2700
V3 + (V2 – V3) × 2100/2700
V3 + (V2 – V3) × 2000/2700
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V40’
V41’
V42’
V43’
V44’
V45’
V46’
V47’
V3 + (V2 – V3) × 1900/2700
V3 + (V2 – V3) × 1800/2700
V3 + (V2 – V3) × 1700/2700
V3 + (V2 – V3) × 1600/2700
V3 + (V2 – V3) × 1500/2700
V3 + (V2 – V3) × 1400/2700
V3 + (V2 – V3) × 1300/2700
V3 + (V2 – V3) × 1200/2700
30H
31H
32H
33H
34H
35H
36H
37H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V48’
V49’
V50’
V51’
V52’
V53’
V54’
V55’
V3 + (V2 – V3) × 1100/2700
V3 + (V2 – V3) × 1000/2700
V3 + (V2 – V3) × 900/2700
V3 + (V2 – V3) × 800/2700
V3 + (V2 – V3) × 700/2700
V3 + (V2 – V3) × 600/2700
V3 + (V2 – V3) × 400/2700
V3 + (V2 – V3) × 200/2700
V
1
’
V
2
’
V
3
’
V
55
’
V
56
’
V
57
’
V
0
V
3
r
0
r
1
r
2
r
3
r
55
r
56
r
57
r
54
V
31
’
r
30
r
31
V
32
’
V
33
’
r
32
r
33
V
2
V
58
’
r
59
V
59
’
r
58
V
60
’
r
60
V
61
’
r
62
V
62
’
r
61
V
4
’
V
5
’
V
6
’
r
4
r
5
r
6
V
7
’
r
7
V
8
’
V
9
’
r
8
r
9
V
0
’
V
1
V
5
r
4-5
V
63
”
9 kΩ
V
4
V
63
’
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V56’
V57’
V58’
V59’
V60’
V61’
V62’
V63’
V3
V4 + (V3 – V4) × 2300/2500
V4 + (V3 – V4) × 2100/2500
V4 + (V3 – V4) × 1800/2500
V4 + (V3 – V4) × 1500/2500
V4 + (V3 – V4) × 1200/2500
V4 + (V3 – V4) × 800/2500
V4
Caution Between V4 and V5 terminal is connected by using the resistor (9 k Ω
ΩΩ
Ω) in the chip.
8
µ
µµ
µ
PD16633B
Figure 2-2. Relationship Between Input Data and Output Voltage: V4 > V5 > V6 > V7 > V8 > V9 > VSS2
Data DX5 DX4 DX3 DX2 DX1 DX0 Output Voltage
00H
01H
02H
03H
04H
05H
06H
07H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0”
V1”
V2”
V3”
V4”
V5”
V6”
V7”
V9
V9 + (V8 – V9) × 800/5300
V9 + (V8 – V9) × 1600/5300
V9 + (V8 – V9) × 2400/5300
V9 + (V8 – V9) × 3100/5300
V9 + (V8 – V9) × 3800/5300
V9 + (V8 – V9) × 4400/5300
V9 + (V8 – V9) × 4900/5300
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V8”
V9”
V10”
V11”
V12”
V13”
V14”
V15”
V8
V8 + (V7 – V8) × 400/4000
V8 + (V7 – V8) × 700/4000
V8 + (V7 – V8) × 1000/4000
V8 + (V7 – V8) × 1300/4000
V8 + (V7 – V8) × 1600/4000
V8 + (V7 – V8) × 1800/4000
V8 + (V7 – V8) × 2000/4000
10H
11H
12H
13H
14H
15H
16H
17H
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V16”
V17”
V18”
V19”
V20”
V21”
V22”
V23”
V8 + (V7 – V8) × 2200/4000
V8 + (V7 – V8) × 2400/4000
V8 + (V7 – V8) × 2600/4000
V8 + (V7 – V8) × 2700/4000
V8 + (V7 – V8) × 2800/4000
V8 + (V7 – V8) × 2900/4000
V8 + (V7 – V8) × 3000/4000
V8 + (V7 – V8) × 3100/4000
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V24”
V25”
V26”
V27”
V28”
V29”
V30”
V31”
V8 + (V7 – V8) × 3200/4000
V8 + (V7 – V8) × 3300/4000
V8 + (V7 – V8) × 3400/4000
V8 + (V7 – V8) × 3500/4000
V8 + (V7 – V8) × 3600/4000
V8 + (V7 – V8) × 3700/4000
V8 + (V7 – V8) × 3800/4000
V8 + (V7 – V8) × 3900/4000
20H
21H
22H
23H
24H
25H
26H
27H
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V32”
V33”
V34”
V35”
V36”
V37”
V38”
V39”
V7
V7 + (V6 – V7) × 100/2700
V7 + (V6 – V7) × 200/2700
V7 + (V6 – V7) × 300/2700
V7 + (V6 – V7) × 400/2700
V7 + (V6 – V7) × 500/2700
V7 + (V6 – V7) × 600/2700
V7 + (V6 – V7) × 700/2700
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V40”
V41”
V42”
V43”
V44”
V45”
V46”
V47”
V7 + (V6 – V7) × 800/2700
V7 + (V6 – V7) × 900/2700
V7 + (V6 – V7) × 1000/2700
V7 + (V6 – V7) × 1100/2700
V7 + (V6 – V7) × 1200/2700
V7 + (V6 – V7) × 1300/2700
V7 + (V6 – V7) × 1400/2700
V7 + (V6 – V7) × 1500/2700
30H
31H
32H
33H
34H
35H
36H
37H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V48”
V49”
V50”
V51”
V52”
V53”
V54”
V55”
V7 + (V6 – V7) × 1600/2700
V7 + (V6 – V7) × 1700/2700
V7 + (V6 – V7) × 1800/2700
V7 + (V6 – V7) × 1900/2700
V7 + (V6 – V7) × 2000/2700
V7 + (V6 – V7) × 2100/2700
V7 + (V6 – V7) × 2300/2700
V7 + (V6 – V7) × 2500/2700
V
63
”
V
62
”
V
61
”
V
33
”
V
32
”
V
31
”
V
2
”
V
4
V
7
V
9
r
4-5
r
62
r
61
r
60
r
32
r
31
r
30
r
2
r
0
r
33
V
57
”
r
56
V
56
”
V
55
”
r
55
r
54
V
6
V
1
”
r
1
V
0
”
V
4
"
r
4
V
3
”
r
3
V
6
”
r
6
V
5
”
r
5
V
7
”
r
7
V
9
”
r
9
V
8
”
r
8
V
8
V
60
”
V
59
”
V
58
”
r
59
r
58
V
63
’
V
5
r
57
9 kΩ
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V56”
V57”
V58”
V59”
V60”
V61”
V62”
V63”
V6
V6 + (V5 – V6) × 200/2500
V6 + (V5 – V6) × 400/2500
V6 + (V5 – V6) × 700/2500
V6 + (V5 – V6) × 1000/2500
V6 + (V5 – V6) × 1300/2500
V6 + (V5 – V6) × 1700/2500
V5
Caution Between V4 and V5 terminal is connected by using the resistor (9 k Ω
ΩΩ
Ω) in the chip.
9
µ
µµ
µ
PD16633B
Ladder Resistance Value (r0 to r62): Reference Value
Table 1. Resistance values of the resistor strings
Resistor
Name Resistance
Value (Ω)Resistor
Name Resistance
Value (Ω)
r
0
r
1
r
2
r
3
r
4
r
5
r
6
r
7
r
8
r
9
r
10
r
11
r
12
r
13
r
14
r
15
r
16
r
17
r
18
r
19
r
20
r
21
r
22
r
23
r
24
r
25
r
26
r
27
r
28
r
29
r
30
r
31
800
800
800
700
700
600
500
400
400
300
300
300
300
200
200
200
200
200
100
100
100
100
100
100
100
100
100
100
100
100
100
100
r
32
r
33
r
34
r
35
r
36
r
37
r
38
r
39
r
40
r
41
r
42
r
43
r
44
r
45
r
46
r
47
r
48
r
49
r
50
r
51
r
52
r
53
r
54
r
55
r
56
r
57
r
58
r
59
r
60
r
61
r
62
Total
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
200
200
200
200
200
300
300
300
400
800
14500
V
0
, V
9
V
1
, V
8
V
2
, V
7
V
4
, V
5
V
3
, V
6
V
2
, V
7
10
µ
µµ
µ
PD16633B
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits × 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
R/L = H (Right shift)
Output S1S2S3S4··· S311 S312
Data D00-D05 D10-D15 D20-D25 D30-D35 ··· D40-D45 D50-D55
R/L = L (Left shift)
Output S1S2S3S4··· S311 S312
Data D00-D05 D10-D15 D20-D25 D30-D35 ··· D40-D45 D50-D55
S2n–1 (Odd output), S2n (Even output) n = 1, 2, ······, 156
POL S2n–1 S2n
LV
0
to V4V5 to V9
HV
5
to V9V0 to V4
7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
STB
POL
S
2n-1
S
2n
Selected voltage of V
0
to V
4
Selected voltage of V
5
to V
9
Selected voltage of V
0
to V
4
Selected voltage of V
5
to V
9
Selected voltage of V
0
to V
4
Selected voltage of V
5
to V
9
Hi-zHi-zHi-z
11
µ
µµ
µ
PD16633B
8. CAUTIONS ABOUT FRAME INVERSION
In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity.
When write the same polarity twice, there are two cases as follows.
(1) last line output in n frame > first line output in (n+1) frame → Possible to write
(2) last line output in n frame < first line output in (n+1) frame → Not possible to write
µ
PD16633B has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both
ways.
STB
POL
S
2N
n frame last line (n+1) frame
first line (n+1) frame
second line
Discharge buffer Charge buffer
V
COM
Hi-zHi-zHi-z
STB
POL
S
2N
n frame last line (n+1) frame
first line (n+1) frame
second line
V
COM
Hi-zHi-zHi-z Hi-z
Vertical intervals
Vertical intervals
12
µ
µµ
µ
PD16633B
9. ELECTRIC SPECIFICATION
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter Symbol Rating Unit
Logic Part Supply V ol tage VDD1 –0.5 to +6.5 V
Driver Part Supply V ol tage VDD2 –0.5 to +15. 0 V
Logic Part Input Vol tage VI1 –0.5 to VDD1 + 0. 5 V
Driver Part Input Vol tage VI2 –0.5 to V DD2 + 0. 5 V
Logic Part Output Vol tage VO1 –0.5 to VDD1 + 0.5 V
Driver Part Output Vol tage VO2 –0.5 to VDD2 + 0.5 V
Operating Temperature Range TA–10 t o +75 °C
Storage Temperat ure Range Tstg –55 to +125 °C
Recommended Operating Condition (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Logic Part Supply V ol tage VDD1 3.0 3.3 3.6 V
Driver Part Supply V ol tage VDD2 10.0 10.5 13.5 V
High-Level I nput Voltage VIH 0.7VDD1 VDD1 V
Low-Level Input Voltage VIL VSS1 0.3VDD1 V
γ
-Corrected Vol tage V0 to V9VSS2 + 0.05 VDD2 – 0.05 V
Driver Part Output Voltage VOVSS2 + 0.1 VDD2 – 0.1 V
Maximum Clock Frequency fmax. 45 MHz
Electrical Specifications (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
± 0.3 V, VDD2 = 10.5 V ±
±±
± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input Leak Current IIL ±1.0
µ
A
High-Level Out put Voltage VOH STHR (STHL), I OH = 0 mA VDD1 – 0.1 V
Low-Level Output Voltage VOL STHR (S T HL), IOL = 0 mA 0.1 V
γ
-Corrected Suppl y Current I
γ
V0-V9 = 10 V V0, V90.3 0.5 mA
VVOH VX = 9 V, VOUT = 3 VNote –0.6 –0.3 mADriver Output Current
VVOL VX = 3 V, VOUT = 9 VNote 0.3 0.6 mA
Note VX refers to the output voltage of analog output pins S1 to S312.
VOUT refers to the voltage applied to analog output pins S1 to S312.
13
µ
µµ
µ
PD16633B
Electrical Specifications (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
± 0.3 V, VDD2 = 10.5 V ±
±±
± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Output Vol tage Deviat i onNote 1 ∆VOInput data ±5±20 mV
Average Output Volt age
VariationNote 2 ∆VAV Input data ±10 mV
Output Vol tage Range VOI nput data 0.1 VDD2 – 0.1 V
Logic Part Dynami c Current
Consumption IDD1 VDD1, No loads 1.6 10.0 mA
Driver Part Dynami c Current
Consumpti on 1Notes 3, 4 IDD21
V
DD2
= 10.5 V
±
0.5 V, No loads
4.4 8.0 mA
Driver Part Dynami c Current
Consumpti on 1Notes 3, 4 IDD22
V
DD2
= 13.5 V
±
0.5 V, No loads
6.4 10.0 mA
Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
2. The average output voltage variation refers to the average output voltage difference between chips.
The average output voltage refers to the average voltage between chips when the display data is the
same.
3. The STB cycle is defined to be 20
µ
s at fCLK = 40 MHz. The TYP. values refer to an all black or all white
input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern.
4. Refers to the current consumption per driver when cascades are connected under the assumption of
XGA single-sided mounting (10 units).
Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
± 0.3 V, VDD2 = 10.5 V ±
±±
± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Start Pulse Delay Time tPLH1 CL = 25 pF 10 15 ns
Driver Output Del ay Time 1 tPLH2 CL = 50 pF, RL = 50 k Ω6.6 11
µ
s
Driver Output Del ay Time 2 tPLH3 CL = 50 pF, RL = 50 k Ω10 17
µ
s
Driver Output Del ay Time 3 tPHL2 CL = 50 pF, RL = 50 k Ω6.4 11
µ
s
Driver Output Del ay Time 4 tPHL3 CL = 50 pF, RL = 50 k Ω9.1 17
µ
s
Input Capaci tance 1 CI1 STHR (STHL) excl uded,
TA = 25°C 6.4 15 pF
Input Capaci tance 2 CI2 STHR (STHL),
TA = 25°C 6.3 15 pF
14
µ
µµ
µ
PD16633B
Timing Requirement (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
± 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Clock P ul se Width PWCLK 22 ns
Clock Pulse Low Period PWCLK(H) 6ns
Clock Pulse Hi gh Period PWCLK(L) 6ns
Data Setup Time tSETUP1 6ns
Data Hold Ti m e tHOLD1 6ns
Start P ul s e Setup Time tSETUP2 6ns
Start Pulse Hold Time tHOLD2 6ns
POL2 Setup Tim e tSETUP3 6ns
POL2 Hold Time tHOLD3 6ns
Start Pulse Low P eri od t SPL 5ns
STB Pulse Width PWSTB 0.5
µ
s
Data Invalid Period tINV 1CLK
Last Data Timing tLDT 2CLK
CLK-STB Time tCLK-STB CLK ↑ → STB ↓5ns
STB-CLK Time tSTB-CLK STB ↓ → CLK ↓5ns
Time Between ST B and
Start Pulse tSTB-STH STB ↓ → STHR (L) ↑50 ns
POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑–5 ns
STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑5ns
15
µ
µµ
µ
PD16633B
10. SWITCHING CHARACTERISTICS WAVEFORM (R/L = H)
Unless otherwise specified, the input level is defined to be VILH = 0.5VDD1
STHR
(1st Dr.)
CLK V
DD1
V
SS1
D n0 to D n5
POL2
STHL
(1st Dr.)
STB
POL
1 2 3 52 53 54 513 514
1 2
t
SPL
t
SETUP2
t
HOLD2
INVALID
D
1
to D
6
D
7
to D
12
D
301
to
D
306
D
307
to
D
312
D
313
to
D
318
D
3067
to
D
3072
INVALID
D
1
to D
3
D
4
to D
6
t
SETUP1
t
HOLD1
INVALID INVALID
t
SETUP3
t
HOLD3
t
PLH1
t
INV
t
LDT
PW
STB
t
CLK-STB
t
STB-CLK
t
PHL3
t
PHL2
t
PLH2
t
PLH3
Hi-z
Target Voltage ± 0.1 V
DD2
t
POL-STB
t
STB-POL
V
out
PW
CLK (L)
PW
CLK
PW
CLK (H)
t
STB-STH
t
r
t
f
90 %
10 %
V
DD1
V
SS1
V
DD1
V
SS1
V
DD1
V
SS1
V
DD1
V
SS1
V
DD1
V
SS1
V
DD1
V
SS1
6 bit accuracy
16
µ
µµ
µ
PD16633B
11. RECOMMENDED MOUNTING CONDITIONS
When mounting this product, please make sure that the following recommended conditions are satisfied.
For packaging methods and conditions other than those recommended below, please contact NEC sales
personnel.
Mounting Condition Mounting Method Condition
Soldering
Heating tool 300 to 350°C, heating for 2 to 3 sec; pressure 100 g (per solder)
Thermocompression
ACF
(Adhesive
Conductive Film)
Temporary bonding 70 t o 100° C; pressure 3 to 8 kg/cm2; time 3 to 5 sec.
Real bonding 165 to 180°C; pressure 25 to 45 kg/cm2, time 30 to 40 secs.
(When using the ani sotropy conducti ve film SUMIZA C1003 of Sumit om o
Bakeli t e, Ltd)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Reference
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
17
µ
µµ
µ
PD16633B
[MEMO]
18
µ
µµ
µ
PD16633B
[MEMO]
19
µ
µµ
µ
PD16633B
[MEMO]
µ
µµ
µ
PD16633B
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
