DATA SHEET MOS INTEGRATED CIRCUIT PD16633B 312 OUTPUT TFT-LCD SORCE DRIVER (COMPATIBLE WITH 64 GRAY SCALES) The PD16633B is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as 9.8 VP-P, level inversion operation of the LCD's common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-LCD panels. FEATURES * Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter * Output dynamic range 9.8 VP-P min. (@VDD2 = 10.0 V) * CMOS level input * Input of 6 bits (gradation data) by 6 dots * High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V) * 312 outputs * Apply for only dot inversion * Display data inversion function (POL2 terminal.) * Single bank arrangement is possible (loaded with slim TCP) ORDERING INFORMATION Part Number Package PD16633BN-xxx TCP (TAB package) The TCP's external shape is customized. To order your TCP's external shape, please contact a NEC salesperson. Document No. S13214EJ2V0DS00 (2nd edition) Date Published July 1998 N CP(K) Printed in Japan (c) 1998 PD16633B 1. BLOCK DIAGRAM STHR R/L CLK STB STHL VDD1 VSS1 50-bit bidirectional shift register C1 C2 C51 C52 D00-05 D10-15 D20-25 D30-35 D40-45 D50-55 POL2 Data register POL Latch VDD2 Level shifter VSS2 D/A converter V0-V9 Voltage follower output S1 S2 S3 S312 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 Multiplexer V9 POL 2 S311 5 V0 V4 S2 6-bit D/A converter 5 S312 PD16633B 3. PIN CONFIGURATION (PD16633BN-xxx xxx) xxx (Copper Plated surface) VSS2 VDD2 VSS1 R/L POL STB D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 STHL V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 CLK STHR D30 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 POL2 TEST VDD1 VDD2 VSS2 S312 S311 S310 S309 S4 S3 S2 S1 Caution This figure does not specify the TCP package. 3 PD16633B 4. PIN FUNCTIONS Pin Symbol Pin Name Description S1 to S312 Driver output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 Display data input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB R/L Shift direction control input These refer to the start pulse input/output pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R/L = H : STHR input, S1 S312, STHL output R/L = L : STHL input, S312 S1, STHR output STHR Right shift start pulse input/output R/L = H : Becomes the start pulse input pin. R/L = L : Becomes the start pulse output pin. STHL Left shift start pulse input/output R/L = H : Becomes the start pulse output pin. R/L = L : Becomes the start pulse input pin. CLK Shift clock input Refers to the shift register's shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 52nd clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. The initial-level driver's 52nd clock becomes valid as the next-level driver's start pulse is input. If 54th clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB's rising edge. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L ; The S2n-1 output uses V0 to V4 as the reference supply; The S2n output uses V5 to V9 as the reference supply. POL = H; The S2n-1 output uses V5 to V9 as the reference supply; The S2n output uses V0 to V4 as the reference supply. POL2 Data inversion POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted. V0 to V9 -corrected power supplies Input the -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 TEST Test pin TEST = H or Open: Standard mode TEST = L: Test mode Please input "H" level. VDD1 Logic power supply 3.3 V 0.3 V VDD2 Driver power supply 10.0 V to 13.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 4 PD16633B Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert a 0.47 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the -corrected power supply terminals (V0, V1, V2, ***, V9) and VSS2. 5 PD16633B 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios between the LCD panel's -corrected voltages and V0' to V63' and V0" to V63" are roughly equal; and their respective resistance values are as shown on page 9. Among the 5-by-2 -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five -corrected voltages of V0 to V4 and V5 to V9 . Figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2. Figures 2-1 and 2-2 show the relationship between the input data and the output data. Table 1 shows the resistance values of the resistor strings. This driver IC is designed for single-sided mounting. Therefore, please do not use it for -corrected power supply level inversion in double-sided mounting. Because the current flowing through ladder resistors r0 to r62 is small, its use for double-sided mounting impairs the IC's stable operation when the level of the -corrected power supply terminal is inverted thus causing display failures. Figure 1. Relationship Between Input Data and Output Voltage VDD2 0.1 V V0 V1 V2 V3 V4 VCOM V5 V6 V7 V8 0.1 V V9 VSS2 00 08 10 18 20 28 30 38 3F Input data (HEX) (POL2 = L) 6 40 (Invalid) PD16633B Figure 2-1. Relationship Between Input Data and Output Voltage: VDD2 > V0 > V1 > V2 > V3 > V4 > V5 V0 V0' r0 V1' r1 V2' r2 V3' r3 V4' r4 V5' r5 V6' r6 V7' r7 V8' V1 r8 V9' r9 r30 V31' r31 V2 V32' r32 V33' r33 r54 V55' r55 V3 V56' r56 V57' r57 V58' r58 V59' r59 V60' r60 V61' r61 V62' r62 V4 V63' r4-5 V5 9 k V63" Data DX5 DX4 DX3 DX2 DX1 DX0 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V0 V1 + (V0 - V1) x 4500/5300 V1 + (V0 - V1) x 3700/5300 V1 + (V0 - V1) x 2900/5300 V1 + (V0 - V1) x 2200/5300 V1 + (V0 - V1) x 1500/5300 V1 + (V0 - V1) x 900/5300 V1 + (V0 - V1) x 400/5300 Output Voltage 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V8' V9' V10' V11' V12' V13' V14' V15' V1 V2 + (V1 - V2) x 3600/4000 V2 + (V1 - V2) x 3300/4000 V2 + (V1 - V2) x 3000/4000 V2 + (V1 - V2) x 2700/4000 V2 + (V1 - V2) x 2400/4000 V2 + (V1 - V2) x 2200/4000 V2 + (V1 - V2) x 2000/4000 10H 11H 12H 13H 14H 15H 16H 17H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V16' V17' V18' V19' V20' V21' V22' V23' V2 + (V1 - V2) x 1800/4000 V2 + (V1 - V2) x 1600/4000 V2 + (V1 - V2) x 1400/4000 V2 + (V1 - V2) x 1300/4000 V2 + (V1 - V2) x 1200/4000 V2 + (V1 - V2) x 1100/4000 V2 + (V1 - V2) x 1000/4000 V2 + (V1 - V2) x 900/4000 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V24' V25' V26' V27' V28' V29' V30' V31' V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x 20H 21H 22H 23H 24H 25H 26H 27H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V32' V33' V34' V35' V36' V37' V38' V39' V2 V3 + (V2 - V3) x 2600/2700 V3 + (V2 - V3) x 2500/2700 V3 + (V2 - V3) x 2400/2700 V3 + (V2 - V3) x 2300/2700 V3 + (V2 - V3) x 2200/2700 V3 + (V2 - V3) x 2100/2700 V3 + (V2 - V3) x 2000/2700 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V40' V41' V42' V43' V44' V45' V46' V47' V3 + (V2 - V3) x 1900/2700 V3 + (V2 - V3) x 1800/2700 V3 + (V2 - V3) x 1700/2700 V3 + (V2 - V3) x 1600/2700 V3 + (V2 - V3) x 1500/2700 V3 + (V2 - V3) x 1400/2700 V3 + (V2 - V3) x 1300/2700 V3 + (V2 - V3) x 1200/2700 30H 31H 32H 33H 34H 35H 36H 37H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V48' V49' V50' V51' V52' V53' V54' V55' V3 + (V2 - V3) x 1100/2700 V3 + (V2 - V3) x 1000/2700 V3 + (V2 - V3) x 900/2700 V3 + (V2 - V3) x 800/2700 V3 + (V2 - V3) x 700/2700 V3 + (V2 - V3) x 600/2700 V3 + (V2 - V3) x 400/2700 V3 + (V2 - V3) x 200/2700 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V56' V57' V58' V59' V60' V61' V62' V63' V3 V4 + (V3 - V4) x 2300/2500 V4 + (V3 - V4) x 2100/2500 V4 + (V3 - V4) x 1800/2500 V4 + (V3 - V4) x 1500/2500 V4 + (V3 - V4) x 1200/2500 V4 + (V3 - V4) x 800/2500 V4 800/4000 700/4000 600/4000 500/4000 400/4000 300/4000 200/4000 100/4000 Caution Between V4 and V5 terminal is connected by using the resistor (9 k ) in the chip. 7 PD16633B Figure 2-2. Relationship Between Input Data and Output Voltage: V4 > V5 > V6 > V7 > V8 > V9 > VSS2 V63' V4 r4-5 9 k V63" V5 r62 V62" r61 V61" r60 V60" r59 V59" r58 V58" r57 V57" r56 V6 V56" r55 V55" r54 r33 V33" r32 V7 V32" r31 V31" r30 r9 V9" r8 V8 V8" r7 V7" r6 V6" r5 V5" r4 V4" r3 V3" r2 V2" r1 V1" r0 V9 V0" Data DX5 DX4 DX3 DX2 DX1 DX0 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0" V1" V2" V3" V4" V5" V6" V7" V9 V9 + (V8 - V9) x 800/5300 V9 + (V8 - V9) x 1600/5300 V9 + (V8 - V9) x 2400/5300 V9 + (V8 - V9) x 3100/5300 V9 + (V8 - V9) x 3800/5300 V9 + (V8 - V9) x 4400/5300 V9 + (V8 - V9) x 4900/5300 Output Voltage 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V8" V9" V10" V11" V12" V13" V14" V15" V8 V8 + (V7 - V8) x 400/4000 V8 + (V7 - V8) x 700/4000 V8 + (V7 - V8) x 1000/4000 V8 + (V7 - V8) x 1300/4000 V8 + (V7 - V8) x 1600/4000 V8 + (V7 - V8) x 1800/4000 V8 + (V7 - V8) x 2000/4000 10H 11H 12H 13H 14H 15H 16H 17H 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V16" V17" V18" V19" V20" V21" V22" V23" V8 + (V7 - V8) x 2200/4000 V8 + (V7 - V8) x 2400/4000 V8 + (V7 - V8) x 2600/4000 V8 + (V7 - V8) x 2700/4000 V8 + (V7 - V8) x 2800/4000 V8 + (V7 - V8) x 2900/4000 V8 + (V7 - V8) x 3000/4000 V8 + (V7 - V8) x 3100/4000 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V24" V25" V26" V27" V28" V29" V30" V31" V8 + (V7 - V8) x 3200/4000 V8 + (V7 - V8) x 3300/4000 V8 + (V7 - V8) x 3400/4000 V8 + (V7 - V8) x 3500/4000 V8 + (V7 - V8) x 3600/4000 V8 + (V7 - V8) x 3700/4000 V8 + (V7 - V8) x 3800/4000 V8 + (V7 - V8) x 3900/4000 20H 21H 22H 23H 24H 25H 26H 27H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V32" V33" V34" V35" V36" V37" V38" V39" V7 V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V40" V41" V42" V43" V44" V45" V46" V47" V7 + (V6 - V7) x 800/2700 V7 + (V6 - V7) x 900/2700 V7 + (V6 - V7) x 1000/2700 V7 + (V6 - V7) x 1100/2700 V7 + (V6 - V7) x 1200/2700 V7 + (V6 - V7) x 1300/2700 V7 + (V6 - V7) x 1400/2700 V7 + (V6 - V7) x 1500/2700 30H 31H 32H 33H 34H 35H 36H 37H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V48" V49" V50" V51" V52" V53" V54" V55" V7 + (V6 - V7) x 1600/2700 V7 + (V6 - V7) x 1700/2700 V7 + (V6 - V7) x 1800/2700 V7 + (V6 - V7) x 1900/2700 V7 + (V6 - V7) x 2000/2700 V7 + (V6 - V7) x 2100/2700 V7 + (V6 - V7) x 2300/2700 V7 + (V6 - V7) x 2500/2700 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V56" V57" V58" V59" V60" V61" V62" V63" V6 V6 + (V5 - V6) x 200/2500 V6 + (V5 - V6) x 400/2500 V6 + (V5 - V6) x 700/2500 V6 + (V5 - V6) x 1000/2500 V6 + (V5 - V6) x 1300/2500 V6 + (V5 - V6) x 1700/2500 V5 100/2700 200/2700 300/2700 400/2700 500/2700 600/2700 700/2700 Caution Between V4 and V5 terminal is connected by using the resistor (9 k ) in the chip. 8 PD16633B Ladder Resistance Value (r0 to r62): Reference Value Table 1. Resistance values of the resistor strings V0, V9 V1, V8 V2, V7 Resistor Name Resistance Value () Resistor Name Resistance Value () r0 800 r32 100 r1 800 r33 100 r2 800 r34 100 r3 700 r35 100 r4 700 r36 100 r5 600 r37 100 r6 500 r38 100 r7 400 r39 100 r8 400 r40 100 r9 300 r41 100 r10 300 r42 100 r11 300 r43 100 r12 300 r44 100 r13 200 r45 100 r14 200 r46 100 r15 200 r47 100 r16 200 r48 100 r17 200 r49 100 r18 100 r50 100 r19 100 r51 100 r20 100 r52 100 r21 100 r53 200 r22 100 r54 200 r23 100 r55 200 r24 100 r56 200 r25 100 r57 200 r26 100 r58 300 r27 100 r59 300 r28 100 r60 300 r29 100 r61 400 r30 100 r62 r31 100 Total 800 14500 V2, V7 V3, V6 V4, V5 9 PD16633B 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) R/L = H (Right shift) Output S1 S2 S3 S4 *** S311 S312 Data D00-D05 D10-D15 D20-D25 D30-D35 *** D40-D45 D50-D55 R/L = L (Left shift) Output S1 S2 S3 S4 *** S311 S312 Data D00-D05 D10-D15 D20-D25 D30-D35 *** D40-D45 D50-D55 S2n-1 (Odd output), S2n (Even output) n = 1, 2, ******, 156 POL S2n-1 S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM STB POL S2n-1 Selected voltage of V0 to V4 Selected voltage of V5 to V9 Selected voltage of V0 to V4 S2n Selected voltage of V5 to V9 Hi-z 10 Selected voltage of V0 to V4 Hi-z Selected voltage of V5 to V9 Hi-z PD16633B 8. CAUTIONS ABOUT FRAME INVERSION In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. When write the same polarity twice, there are two cases as follows. (1) last line output in n frame > first line output in (n+1) frame Possible to write (2) last line output in n frame < first line output in (n+1) frame Not possible to write PD16633B has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both ways. STB n frame last line POL Discharge buffer Vertical intervals (n+1) frame first line (n+1) frame second line Charge buffer S2N VCOM Hi-z STB Hi-z Vertical intervals (n+1) frame first line n frame last line Hi-z (n+1) frame second line POL S2N VCOM Hi-z Hi-z Hi-z Hi-z 11 PD16633B 9. ELECTRIC SPECIFICATION Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 -0.5 to +6.5 V Driver Part Supply Voltage VDD2 -0.5 to +15.0 V Logic Part Input Voltage VI1 -0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 -0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 -0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 -0.5 to VDD2 + 0.5 V Operating Temperature Range TA -10 to +75 C Storage Temperature Range Tstg -55 to +125 C Recommended Operating Condition (TA = -10 to +75C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic Part Supply Voltage VDD1 3.0 3.3 3.6 V Driver Part Supply Voltage VDD2 10.0 10.5 13.5 V High-Level Input Voltage VIH 0.7VDD1 VDD1 V Low-Level Input Voltage VIL VSS1 0.3VDD1 V V0 to V9 VSS2 + 0.05 VDD2 - 0.05 V Driver Part Output Voltage VO VSS2 + 0.1 VDD2 - 0.1 V Maximum Clock Frequency fmax. 45 -Corrected Voltage MHz Electrical Specifications (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 10.5 V 0.5 V, VSS1 = VSS2 = 0 V) Parameter Input Leak Current Symbol Condition MIN. IIL High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA -Corrected Supply Current I Driver Output Current VVOH VVOL V0-V9 = 10 V V0, V9 VX = 9 V, VOUT = 3 V Note VX = 3 V, VOUT = 9 V Note MAX. Unit 1.0 A VDD1 - 0.1 0.3 Note VX refers to the output voltage of analog output pins S1 to S312. VOUT refers to the voltage applied to analog output pins S1 to S312. 12 TYP. V 0.1 V 0.3 0.5 mA -0.6 -0.3 mA 0.6 mA PD16633B Electrical Specifications (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 10.5 V 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 20 mV Output Voltage Deviation VO Input data 5 Average Output Voltage VariationNote 2 VAV Input data 10 Output Voltage Range VO Input data Logic Part Dynamic Current Consumption IDD1 VDD1, No loads Driver Part Dynamic Current Consumption 1Notes 3, 4 IDD21 Driver Part Dynamic Current Consumption 1Notes 3, 4 IDD22 Note 1 0.1 mV VDD2 - 0.1 V 1.6 10.0 mA VDD2 = 10.5 V 0.5 V, No loads 4.4 8.0 mA VDD2 = 13.5 V 0.5 V, No loads 6.4 10.0 mA Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 2. The average output voltage variation refers to the average output voltage difference between chips. The average output voltage refers to the average voltage between chips when the display data is the same. 3. The STB cycle is defined to be 20 s at fCLK = 40 MHz. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (10 units). Switching Characteristics (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 10.5 V 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Start Pulse Delay Time tPLH1 CL = 25 pF 10 15 ns Driver Output Delay Time 1 tPLH2 CL = 50 pF, RL = 50 k 6.6 11 s Driver Output Delay Time 2 tPLH3 CL = 50 pF, RL = 50 k 10 17 s Driver Output Delay Time 3 tPHL2 CL = 50 pF, RL = 50 k 6.4 11 s Driver Output Delay Time 4 tPHL3 CL = 50 pF, RL = 50 k 9.1 17 s Input Capacitance 1 CI1 STHR (STHL) excluded, TA = 25C 6.4 15 pF Input Capacitance 2 CI2 STHR (STHL), TA = 25C 6.3 15 pF 13 PD16633B Timing Requirement (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns) Parameter Clock Pulse Width Symbol Condition MIN. TYP. MAX. Unit PWCLK 22 ns Clock Pulse Low Period PWCLK(H) 6 ns Clock Pulse High Period PWCLK(L) 6 ns Data Setup Time tSETUP1 6 ns Data Hold Time tHOLD1 6 ns Start Pulse Setup Time tSETUP2 6 ns Start Pulse Hold Time tHOLD2 6 ns POL2 Setup Time tSETUP3 6 ns POL2 Hold Time tHOLD3 6 ns tSPL 5 ns PWSTB 0.5 s Data Invalid Period tINV 1 CLK Last Data Timing tLDT 2 CLK Start Pulse Low Period STB Pulse Width CLK-STB Time tCLK-STB CLK STB 5 ns STB-CLK Time tSTB-CLK STB CLK 5 ns Time Between STB and Start Pulse tSTB-STH STB STHR (L) 50 ns POL-STB Time tPOL-STB POL or STB -5 ns STB-POL Time tSTB-POL STB POL or 5 ns 14 1 tr 2 CLK 1 2 3 52 53 54 513 514 10 % tSETUP2 tHOLD2 tCLK-STB tSTB-CLK VSS1 tSPL VDD1 STHR (1st Dr.) VSS1 tSETUP1 D n0 to D n5 tf VDD1 90 % INVALID D1 to D6 D7 to D12 tSETUP3 tSTB-STH tHOLD1 D301 to D306 D307 to D312 D313 to D318 VDD1 D3067 to D3072 INVALID D1 to D3 D4 to D6 VSS1 tHOLD3 VDD1 POL2 INVALID INVALID VSS1 tPLH1 VDD1 STHL (1st Dr.) VSS1 tLDT tINV PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-z tPLH2 10. SWITCHING CHARACTERISTICS WAVEFORM (R/L = H) Unless otherwise specified, the input level is defined to be V ILH = 0.5VDD1 PWCLK (L) PWCLK PWCLK (H) Target Voltage 0.1 VDD2 6 bit accuracy tPHL2 tPHL3 15 PD16633B Vout PD16633B 11. RECOMMENDED MOUNTING CONDITIONS When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel. Mounting Condition Thermocompression Mounting Method Condition Soldering Heating tool 300 to 350C, heating for 2 to 3 sec; pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C; pressure 3 to 8 kg/cm ; time 3 to 5 sec. 2 Real bonding 165 to 180C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd) 2 Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E) 16 PD16633B [MEMO] 17 PD16633B [MEMO] 18 PD16633B [MEMO] 19 PD16633B No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5