General Description
The MAX19542 monolithic 12-bit, 170Msps analog-to-
digital converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with con-
version rates up to 170Msps while consuming only
907mW.
At 170Msps and an input frequency of 240MHz, the
MAX19542 achieves a spurious-free dynamic range
(SFDR) of 76.4dBc. The MAX19542 features an excel-
lent signal-to-noise ratio (SNR) of 65dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19542 ideal for wideband applica-
tions such as power-amplifier predistortion in cellular
base-station transceiver systems.
The MAX19542 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the out-
puts appear on two separate parallel ports at one-half
the sampling rate. See the
Modes of Operation
section.
The MAX19542 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-cou-
pled. The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 340MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differ-
ential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data for-
mat can be selected to be either two’s complement or
offset binary.
A pin-compatible, 12-bit, 125Msps version of the
MAX19542 is also available. Refer to the MAX19541
data sheet for more information.
The MAX19542 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the extended
(-40°C to +85°C) temperature range.
Applications
Base-Station Power Amplifier Linearization
Cable Head-End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
Features
o170Msps Conversion Rate
oSNR = 64.3dB, fIN = 100MHz at 170Msps
oSFDR = 73dBc, fIN = 100MHz at 170Msps
o±0.7 LSB INL, ±0.25 DNL (typ)
o907mW Power Dissipation at 170Msps
oOn-Chip Selectable Divide-by-2 Clock Input
oParallel or Demux Parallel Digital CMOS Outputs
oReset Option for Synchronizing Multiple ADCs
oData Clock Output
oOffset Binary or Two’s-Complement Output
oEvaluation Kit Available (MAX19542EVKIT)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
________________________________________________________________
Maxim Integrated Products
1
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
AVCC
AGND
AVCC
QFN
TOP VIEW
AVCC
OGND
OVCC
ORA
DA11
DA10
DA9
DA8
DA7
5253
DA6
DA5
AGND
AGND
AVCC
CLKP
CLKN
AVCC
AGND
OVCC
OGND
DB0
OVCC
DB2
DB1
DB3
DA0
ORB
OGND
OVCC
DCLKP
DCLKN
OVCC
DB11
DB10
DB9
35
36
37 DB8
DB7
DB6
NOTE: EXPOSED PAD CONNECTED TO AGND.
AGND
INN
INP
AGND
AVCC
DEMUX
RESET
AVCC
AVCC
AVCC
AGND
REFADJ
REFIO
AGND
48 DA1
AVCC
64
AGND
656667
+
ITL
AGND
AVCC
68
EP
T/B
2322212019 2726252418 2928 323130
DB4
DB5
3433
49
50 DA3
DA2
51 DA4
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
CLKDIV 17
MAX19542
Pin Configuration
Ordering Information
19-3464; Rev 1; 10/10
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX19542EGK+ -40°C to +85°C 68 QFN-EP*
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, TA= TMIN to TMAX, unless otherwise noted. TA≥+25°C guaranteed by production test, TA< +25°C
guaranteed by design and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC to AGND ......................................................-0.3V to +2.1V
OVCC to OGND .....................................................-0.3V to +2.1V
AVCC to OVCC .......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs (INP, INN) to AGND..........-0.3V to (AVCC + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V)
REFIO, REFADJ to AGND........................-0.3V to (AVCC + 0.3V)
All Digital Outputs to OGND....................-0.3V to (OVCC + 0.3V)
Maximum Current into Any Pin ....................................... ±50mA
ESD on All Pins (Human Body Model).............................±2000V
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C) ........ 3333mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity INL fIN = 10MHz (Note 1) -2.5 ±0.7 +2.5 LSB
Differential Nonlinearity DNL fIN = 10MHz, no missing codes (Note 1) -0.75 ±0.25 +0.75 LSB
Transfer Curve Offset VOS (Note 1) -3 +3 mV
Offset Temperature Drift 40 mV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range VFS (Note 1) 1300 1410 1510 mVP-P
Full-Scale Range Temperature
Drift 130 ppm/°C
Common-Mode Input Range VCM 1.365
±0.15 V
Input Capacitance CIN 3pF
Differential Input Resistance RIN 3.00 4.3 6.25 kΩ
Full-Power Analog Bandwidth FPBW 900 MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage VREFIO 1.22 1.245 1.27 V
Reference Temperature Drift 90 ppm/°C
REFADJ Input High Voltage VREFADJ Used to disable the internal reference VAVCC
- 0.3 V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate fSAMPLE 170 MHz
Minimum Sampling Rate fSAMPLE 20 MHz
Clock Duty Cycle Set by clock-management circuit 40 to 60 %
Aperture Delay tAD Figure 4 620 ps
Aperture Jitter tAJ 0.2 psRMS
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, TA= TMIN to TMAX, unless otherwise noted. TA≥+25°C guaranteed by production test, TA< +25°C
guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input
Amplitude (Note 2) 200 500 mVP-P
Clock Input Common-Mode
Voltage Range
1.15
±0.25 V
Clock Differential Input
Resistance RCLK 11
±25% kΩ
Clock Differential Input
Capacitance CCLK 5pF
DYNAMIC CHARACTERISTICS (at -2dBFS)
fIN = 10MHz 62.3 65
fIN = 100MHz 62.3 64.3
fIN = 180MHz 63.5
Signal-to-Noise Ratio SNR
fIN = 240MHz 63.3
dB
fIN = 10MHz 61.9 64.8
fIN = 100MHz 61.7 63.6
fIN = 180MHz 62.6
Signal-to-Noise and Distortion SINAD
fIN = 240MHz 63
dB
fIN = 10MHz 68.3 82
fIN = 100MHz 68.3 73
fIN = 180MHz 72.4
Spurious-Free Dynamic Range SFDR
fIN = 240MHz 76.4
dBc
fIN = 10MHz -85 -69.1
fIN = 100MHz -73 -68.7
fIN = 180MHz -72.4
Worst Harmonics
(HD2 or HD3)
fIN = 240MHz -76.4
dBc
Two-Tone Intermodulation
Distortion IMD100 fIN1 = 207.5MHz at -7dBFS,
fIN2 = 211.5MHz at -7dBFS, fSAMPLE = 170MHz -69 dBc
CMOS DIGITAL OUTPUTS (DA0–DA11, DB0–DB11, ORA, ORB)
Logic-High Output Voltage VOH VOVCC
- 0.1 V
Logic-Low Output Voltage VOL 0.1 V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B, DEMUX, ITL)
Digital Input-Voltage Low VIL 0.2 x
VAVCC V
Digital Input-Voltage High VIH 0.8 x
VAVCC V
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
4 _______________________________________________________________________________________
Note 1: Static linearity and offset parameters are computed from a straight line drawn between the end points of the code transition
transfer function. The full-scale range (FSR) is defined as 4096 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; TA= TMIN to TMAX.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
ELECTRICAL CHARACTERISTICS (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, DEMUX = 0, differential LVPECL clock input drive, 0.1µF capac-
itor on REFIO, internal reference, TA= TMIN to TMAX, unless otherwise noted. TA≥+25°C guaranteed by production test, TA< +25°C
guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Resistance RIN 46.5 kΩ
Input Capacitance CIN 5pF
TIMING CHARACTERISTICS
CLKP-to DA0–DA11 Propagation
Delay tPDL Figures 5, 6, and 7 2.5 ns
CLKP-to-DCLKP Propagation
Delay tCPDL Figures 5, 6, and 7 2.1 ns
DCLKP Rising Edge to
DA0–DA11
tPDL -
tCPDL Figures 5, 6, and 7 (Note 2) 180 400 710 ns
CMOS Output Rise Time tRISE 20% to 80%, CL = 5pF 1 ns
CMOS Output Fall Time tFALL 20% to 80%, CL = 5pF 1 ns
RESET Hold tHR Figure 4 100 ps
RESET Setup tSR Figure 4 500 ps
Output Data Pipeline Delay tLATENCY Figure 4 11 Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AVCC 1.7 1.8 1.9 V
Digital Supply Voltage Range OVCC 1.7 1.8 1.9 V
Analog Supply Current IAVCC fIN = 100MHz 480 520 mA
Digital Supply Current IOVCC fIN = 100MHz 24 31 mA
Analog Power Dissipation PDISS fIN = 100MHz 907 992 mW
Offset (Note 3) 1.8 mV/V
Power-Supply Rejection Ratio PSRR Gain (Note 3) 1.5 %FS/V
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
_______________________________________________________________________________________
5
FFT PLOT
(16,384-POINT DATA RECORD)
MAX19542 toc01
ANALOG INPUT FREQUENCY (MHz)
706040 5020 3010080
234567
AMPLITUDE (dB)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0fIN = 12.9599243MHz
fSAMPLE = 170.0043234MHz
AIN = -1.05dBFS
SNR = 65.923dB
SINAD = 65.822dB
SFDR = 88.137dBc
HD2 = -92.278dBc
HD3 = -88.96dBc
FFT PLOT
(16,384-POINT DATA RECORD)
MAX19542 toc02
ANALOG INPUT FREQUENCY (MHz)
706040 5020 3010080
2
3
4
56
7
AMPLITUDE (dB)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0fIN = 64.9863939MHz
fSAMPLE = 170.0043234MHz
AIN = -1.068dBFS
SNR = 65.921dB
SINAD = 65dB
SFDR = 74.007dBc
HD2 = -82.197dBc
HD3 = -79.515dBc
FFT PLOT
(16,384-POINT DATA RECORD)
MAX19542 toc03
ANALOG INPUT FREQUENCY (MHz)
706040 5020 3010080
23
4
5
6
7
AMPLITUDE (dB)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0fIN = 190.186111MHz
fSAMPLE = 170.0043234MHz
AIN = -1.03dBFS
SNR = 64.664dB
SINAD = 63.513dB
SFDR = 71.34dBc
HD2 = -77.559dBc
HD3 = -71.34dBc
FFT PLOT
(16,384-POINT DATA RECORD)
MAX19542 toc04
ANALOG INPUT FREQUENCY (MHz)
706040 5020 3010080
2
34
56
7
AMPLITUDE (dB)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0fIN = 241.008937MHz
fSAMPLE = 170.0043234MHz
AIN = -1.035dBFS
SNR = 64.01dB
SINAD = 63.521dB
SFDR = 74.963dBc
HD2 = -74.963dBc
HD3 = -82.606dBc
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc05
fIN (MHz)
SNR/SINAD (dB)
225200175150125100755025
58
61
64
67
70
55
0 250
SNR
SINAD
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc06
fIN (MHz)
SFDR (dBc)
225200175150125100755025
45
50
55
60
65
70
75
80
85
90
40
0250
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc07
fIN (MHz)
HD2/HD3 (dBc)
225200175150125100755025
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-120
0250
HD3
HD2
THD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc08
fIN (MHz)
THD (dBc)
225200175150125100755025
-95
-90
-85
-80
-75
-70
-65
-60
-100
0250
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
MAX19542 toc09
AIN (dBFS)
SNR/SINAD (dB)
-5-10-15-20-25
38
44
50
56
62
68
32
-30 0
SNR
SINAD
Typical Operating Characteristics
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential RL = 100Ω, TA= +25°C.)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
6 _______________________________________________________________________________________
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
MAX19542 toc10
AIN (dBFS)
SFDR (dBc)
-5-10-15-20-25
45
50
55
60
65
70
75
80
85
90
40
-30 0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
MAX19542 toc11
AIN (dBFS)
HD2/HD3 (dBc)
-5-10-15-20-25
-110
-100
-90
-80
-70
-60
-50
-120
-30 0
HD2
HD3
THD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 170.0043MHz, fIN = 64.9864MHz)
MAX19542 toc12
AIN (dBFS)
THD (dBc)
-5-10-15-20-25
-90
-80
-70
-60
-50
-100
-30 0
SNR/SINAD vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc13
fSAMPLE (MHz)
SNR/SINAD (dB)
18016040 60 80 120100 140
61
62
63
64
65
66
67
68
60
20 200
SNR
SINAD
SFDR vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc14
fSAMPLE (MHz)
SFDR (dBc)
18016040 60 80 120100 140
55
60
65
70
75
80
85
90
50
20 200
HD2/HD3 vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc15
fSAMPLE (MHz)
HD2/HD3 (dBc)
18016040 60 80 120100 140
-100
-105
-95
-85
-90
-80
-75
-70
-65
-60
-55
-50
-110
20 200
HD3
HD2
THD vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc16
fSAMPLE (MHz)
THD (dBc)
18016040 60 80 120100 140
-85
-80
-75
-70
-65
-60
-90
20 200
TWO-TONE IMD
(16,384-POINT DATA RECORD)
MAX19542 toc17
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
706040 5020 3010
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
080
fIN1 = 207.4936801MHz
fIN2 = 211.5611664MHz
fSAMPLE = 170.00432MHz
AIN1 = AIN2 = -7dBFS
IMD = -69dBc
2fIN2 - fIN1
2fIN1 - fIN2
fIN1 fIN2
INL vs. DIGITAL OUTPUT CODE
(512k-POINT DATA RECORD)
MAX19542 toc18
DIGITAL OUTPUT CODE
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
fIN = 13.008646MHz
Typical Operating Characteristics (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential RL = 100Ω, TA= +25°C.)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
_______________________________________________________________________________________
7
DNL vs. DIGITAL OUTPUT CODE
(512k-POINT DATA RECORD)
MAX19542 toc19
DIGITAL OUTPUT CODE
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
fIN = 13.008646MHz
GAIN BANDWIDTH PLOT
(fSAMPLE = 170.0043MHz, AIN = -1dBFS)
MAX19542 toc20
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
100
-6
-5
-4
-3
-2
-1
0
1
-7
10 1000
SNR/SINAD vs. TEMPERATURE
(fSAMPLE = 170MHz, AIN = -2dBFS)
MAX19542 toc21
TEMPERATURE (°C)
SNR/SINAD (dB)
603510-15
62
63
64
65
66
67
61
-40 85
fIN = 100MHz
SNR
SINAD
SFDR vs. TEMPERATURE
(fSAMPLE = 170MHz, AIN = -2dBFS)
MAX19542 toc22
TEMPERATURE (°C)
SFDR (dBc)
603510-15
70
69
71
73
72
75
74
76
77
78
68
-40 85
fIN = 100MHz
TOTAL POWER DISSIPATION vs. fSAMPLE
(fIN = 65.0165MHz, AIN = -1dBFS)
MAX19542 toc23
fSAMPLE (MHz)
PDISS (W)
16014040 60 80 100 120
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
0.800
20 180
FULL-SCALE ADJUSTMENT RANGE
vs. FULL-SCALE ADJUSTMENT RESISTANCE
MAX19542 toc24
RADJ (kΩ)
INTERNAL REFERENCE (V)
800600400200
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.14
0 1000
RADJ BETWEEN REFADJ AND REFIO
RADJ BETWEEN REFADJ AND GND
SNR/SINAD vs. SUPPLY VOLTAGE
(fIN = 64.9864MHz, AIN = -1dBFS)
MAX19542 toc25
SUPPLY VOLTAGE (V)
SNR/SINAD (dB)
2.01.91.81.7
60
62
64
66
68
58
1.6 2.1
AVCC = OVCC
SNR
SINAD
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
MAX19542 toc26
SUPPLY VOLTAGE (V)
VREFIO (V)
2.01.91.81.7
1.249
1.248
1.247
1.246
1.245
1.250
1.244
1.6 2.1
Typical Operating Characteristics (continued)
(VAVCC = VOVCC = 1.8V, VAGND = VOGND = 0V, fSAMPLE = 170MHz, AIN = -1dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential LVPECL clock input drive, 0.1µF capacitor on REFIO, internal reference, digital outputs dif-
ferential RL = 100Ω, TA= +25°C.)
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 6, 11–14,
20, 25, 62,
63, 65
AVCC
Analog Supply Voltage. Bypass each AVCC pin with a 0.1µF capacitor for best decoupling results.
Additional board decoupling might be required. See the Grounding, Bypassing, and Layout
Considerations section.
2, 5, 7, 10,
18, 19, 21,
24, 64, 66
AGND Analog Converter Ground. Connect the converter’s exposed pad (EP) to AGND.
3 REFIO
Reference Input/Output. Drive REFADJ high to allow an external reference source to be connected to
the MAX19542. Drive REFADJ low to activate the internal 1.23V bandgap reference. Connect a 0.1µF
capacitor from REFIO to AGND.
4
REFADJ
Reference Adjust Input. REFADJ allows for full-scale range adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FS range) or REFADJ and REFIO (increases
FS range). If REFADJ is connected to AVCC, the internal reference can be overdriven with an external
source connected to REFIO. If REFADJ is connected to AGND, the internal reference is used to
determine the full-scale range of the data converter.
8 INP Positive Analog Input Terminal
9 INN Negative Analog Input Terminal
15 RESET Active-High RESET Input. RESET controls the latency of the MAX19542. RESET has an internal
pulldown resistor. See the Reset Operation section.
16 DEMUX
Output-Mode-Select Input. Drive DEMUX low for the parallel output mode (full-rate CMOS outputs on
A ports only). Drive DEMUX high for the demux parallel or demux interleaved modes (half-rate outputs
on both ports A and B) depending on the state of the ITL input. See the Modes of Operation section.
17 CLKDIV
Clock-Divider Input. CLKDIV is an LVCMOS-compatible input that controls the sampling frequency
relative to the input clock frequency. CLKDIV has an internal pulldown resistor:
CLKDIV = 0: sampling frequency is 1/2 the input clock frequency.
CLKDIV = 1: sampling frequency is equal to the input clock frequency.
22 CLKN Complementary Clock Input. CLKN ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance.
23 CLKP True Clock Input. CLKP ideally requires an LVPECL-compatible input level to maintain the converter’s
excellent performance.
26, 45, 61
OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41,
44, 60 OVCC D i g i tal S up p l y V ol tag e. Byp ass O V C C w i th a 0.1µF cap aci tor for b est d ecoup l i ng r esul ts. Ad d i ti onal b oar d
d ecoup l i ng m i g ht b e r eq ui r ed . S ee the G r ound i ng , Byp assi ng , and Layout C onsi d er ati ons secti on.
29 DB0 Port B CMOS Digital Output Bit 0 (LSB)
30 DB1 Port B CMOS Digital Output Bit 1
31 DB2 Port B CMOS Digital Output Bit 2
32 DB3 Port B CMOS Digital Output Bit 3
33 DB4 Port B CMOS Digital Output Bit 4
34 DB5 Port B CMOS Digital Output Bit 5
35 DB6 Port B CMOS Digital Output Bit 6
36 DB7 Port B CMOS Digital Output Bit 7
37 DB8 Port B CMOS Digital Output Bit 8
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
38 DB9 Port B CMOS Digital Output Bit 9
39 DB10 Port B CMOS Digital Output Bit 10
40 DB11 Port B CMOS Digital Output Bit 11 (MSB)
42 DCLKN
Inverted CMOS Digital Clock Output. DCLKN provides a CMOS-compatible output level and can be
used to synchronize external devices to the converter clock. When DEMUX is high, the frequency at
DCLKN is half the sampling clock’s frequency.
43 DCLKP
True CMOS Digital Clock Output. DCLKP provides a CMOS-compatible output level and can be used
to synchronize external devices to the converter clock. When DEMUX is high, the frequency at DCLKP is
half the sampling clock’s frequency.
46 ORB Port B CMOS Digital Output Overrange
47 DA0 Port A CMOS Digital Output Bit 0 (LSB)
48 DA1 Port A CMOS Digital Output Bit 1
49 DA2 Port A CMOS Digital Output Bit 2
50 DA3 Port A CMOS Digital Output Bit 3
51 DA4 Port A CMOS Digital Output Bit 4
52 DA5 Port A CMOS Digital Output Bit 5
53 DA6 Port A CMOS Digital Output Bit 6
54 DA7 Port A CMOS Digital Output Bit 7
55 DA8 Port A CMOS Digital Output Bit 8
56 DA9 Port A CMOS Digital Output Bit 9
57 DA10 Port A CMOS Digital Output Bit 10
58 DA11 Port A CMOS Digital Output Bit 11 (MSB)
59 ORA Port A CMOS Digital Output Overrange
67 ITL Interleaved/Parallel-Select Input. Drive ITL low for the demux parallel mode. Drive ITL high for the demux
interleaved mode.
68 T/B
Output-Format-Select Input. T/B is an LVCMOS-compatible input that controls the digital output format
of the MAX19542. T/B has an internal pulldown resistor:
T/B = 1: binary output format.
T/B = 0: two’s-complement output format.
—EP
Exposed Pad. Connect EP to analog ground (AGND) for optimum performance. The exposed pad is
located on the backside of the chip. EP is internally connected to the die substrate.
MAX19542
Detailed Description—
Theory of Operation
The MAX19542 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption. Both positive (INP) and negative/comple-
mentary analog input terminals (INN) are centered
around a 1.365V common-mode voltage, and accept a
±350mV differential analog input voltage swing each,
resulting in a 1.41VP-P typical differential full-scale
signal swing.
Inputs INP and INN are buffered prior to entering each
track-and-hold (T/H) stage and are sampled when the
differential sampling clock signal transitions high. The
ADC following the first T/H stage then digitizes the sig-
nal, and controls a digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 12-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital
correction logic to generate the final output code. The
result is a 12-bit parallel digital output word in user-
selectable two’s complement or binary output formats
with CMOS-compatible output levels. See the functional
diagram (Figure 1) for a more detailed view of the
MAX19542’s architecture.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
10 ______________________________________________________________________________________
MAX19542
CLOCK-
DIVIDER
CONTROL
CLKDIV
CLOCK
MANAGEMENT
DCLKP
DA0–DA11, ORA
DB0–DB11, ORB
DCLKN
12 BITS
12 BITS
DEMUX
ITL
2.15kΩ2.15kΩ
CLKP
CLKN
INP
INN
CM
BUFFER
REFIO REFADJ
CMOS
DATA
PORTS
CLK
GENERATOR
REFERENCE
T/H 12-BIT PIPELINE
QUANTIZER
CORE
RESET
BUFFER
Figure 1. MAX19542 Functional Diagram
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX19542. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are pro-
gressing through the analog stages. The MAX19542
analog inputs are self-biased at a 1.365V common-
mode voltage and allow a 1.41VP-P differential input
voltage swing. Both inputs are self-biased through
2.15kΩresistors, resulting in a typical differential input
resistance of 4.3kΩ(Figure 2). It is recommended dri-
ving the analog inputs of the MAX19542 in an AC-cou-
pled configuration to achieve the best dynamic
performance. See the
Transformer-Coupled, Differential
Analog Input Drive
section for a detailed discussion of
this configuration.
On-Chip Reference Circuit
The MAX19542 features an internal 1.24V bandgap ref-
erence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determine the full-
scale range of the MAX19542. Bypass REFIO with a
0.1µF capacitor to AGND. To compensate for gain errors
or increase the ADC’s full-scale range, the voltage of this
bandgap reference can be indirectly adjusted by adding
an external resistor (e.g., 100kΩtrim potentiometer)
between REFADJ and AGND or REFADJ and REFIO.
See Figure 7 and the
Applications Information
section for
a detailed description of this process.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX19542 differentially
with an LVPECL-compatible clock to achieve the best
dynamic performance. The clock signal source must be
high-quality, low phase noise to avoid any degradation
in the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to typically 1.15V,
accept a typical 0.5VP-P differential signal swing, and
are usually driven in an AC-coupled configuration. See
the
Differential, AC-Coupled Clock Input
section for
more circuit details on how to drive CLKP and CLKN
appropriately.
The MAX19542 features an internal clock-management
circuit (duty-cycle equalizer). The clock-management
circuit ensures that the clock signal applied to inputs
CLKP and CLKN is processed to provide a near 50%
duty-cycle clock signal. This desensitizes the perfor-
mance of the converter to variations in the duty cycle of
the input clock source. Note that the clock duty-cycle
equalizer cannot be turned off externally.
Clock Outputs (DCLKP, DCLKN)
The MAX19542 features CMOS-complementary clock
outputs (DCLKP, DCLKN) to latch the digital output
data with an external latch or receiver. Additionally, the
clock outputs can be used to synchronize external
devices (e.g., FPGAs) to the ADC. There is a 2.1ns
delay time between the rising (falling) edge of CLKP
(CLKN) and the rising (falling) edge of DCLKP
(DCLKN). See Figure 4 for timing details.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 11
2.15kΩ
INP
2.15kΩ
AGND
INN
TO COMMON-MODE
INPUT
TO COMMON-MODE
INPUT
AVCC
Figure 2. Simplified Analog Input Architecture
MAX19542
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
1V
AVCC AVCC/2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCE-
SCALING
AMPLIFIER
REFIO
REFADJ*
0.1µF
*REFADJ CAN BE SHORTED TO AGND THROUGH A 1kΩ
RESISTOR OR POTENTIOMETER.
REFT
REFB
Figure 3. Simplified Reference Architecture
MAX19542
Divide-by-Two Clock Control (CLKDIV)
The MAX19542 offers a clock control line (CLKDIV) that
allows the reduction of clock jitter and phase noise in a
system as higher frequency oscillators usually exhibit
better phase noise and jitter characteristics. Connect
CLKDIV to OGND to enable the ADC’s internal divide-
by-2 clock divider, which allows the user to use an
oscillator of twice the maximum sampling frequency.
The sampling frequency now becomes 1/2 of the input
clock frequency. CLKDIV has an internal pulldown
resistor and can be left open for applications that
require this divide-by-2 mode. Connecting CLKDIV to
OVCC disables the divide-by-2 mode.
RESET Operation
The RESET input defines the pipeline latency of the
MAX19542. Drive RESET high to place the MAX19542
in reset mode with the CMOS outputs tri-stated. During
the time when RESET is high, no sample information is
available at the outputs. For pipeline latency, the first
sample is defined at the first rising edge of CLKP after
RESET goes low. The conversion information is avail-
able at the outputs after 11 clock cycles. Synchronize
RESET with the input clock of the device by observing
the minimum RESET hold (tHR) and RESET setup (tSR)
times (Figure 4). RESET is only used to control the
latency of the device and, in applications where this is
not critical, drive RESET low or leave unconnected.
RESET has an internal pulldown resistor.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
12 ______________________________________________________________________________________
CLKN
CLKP
RESET
N + 1 N + 11 N + 12N
tAD
tSR
tHR
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
INN
INP
tCL
tCH
Figure 4. RESET Timing Diagram
System Timing Requirements
Figures 5, 6, and 7 depict the relationship between the
clock input and output, analog input, sampling event,
and data output. The MAX19542 samples on the rising
(falling) edge of CLKP (CLKN). In all these figures,
CLKDIV is assumed to be high; otherwise, the sampling
events would occur at every other rising edge of CLKP.
Output data is latched on the next rising (falling) edge
of the DCLKP (DCLKN) clock, but has an internal laten-
cy of 11 input clock cycles.
Modes of Operation
The MAX19542 features three modes of operation. In
each mode of operation, the conversion data is output
in a different format.
Parallel Mode
Drive DEMUX low to place the MAX19542 in the parallel
mode. In this mode, the output clock has the same fre-
quency as the sampling frequency and conversion
data is output at full rate on parallel ports DA0–DA11.
Note that the sampling frequency may not be the same
as the input clock frequency. See the
Divide-by-Two
Clock Control (CLKDIV)
section. In parallel mode, sam-
ples are taken on the rising edge of CLKP. Conversion
data appears at the outputs on the rising edge of
DCLKP after the latency period of 11 clock cycles and
is stable for one clock period (Figure 5). If an overrange
condition occurs, it is reflected on the ORA port.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 13
Figure 5. Parallel Mode Timing Diagram
tPDL
tCPDL
tLATENCY
CLKN
CLKP
RESET
DCLKP
DCLKN
DA0–DA11, ORA
N + 1 N + 11 N + 12
N + 1
N + 1
N - 10N - 11 N
N
N
tAD
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
INN
INP
tCL
tCH
N - 11 N - 10 N - 1
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
14 ______________________________________________________________________________________
tPDL
tCPDL
tLATENCY
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
INN
INP
CLKN
CLKP
RESET
DCLKN
DCLKP
DA0–DA11, ORA
N + 12
N + 1 N + 3
N
N
N + 2
N + 2
N
DB0–DB11, ORB
DEMUX PARALLEL MODE
tCL
tCH
tAD
Figure 6. Demux Parallel Mode Timing Diagram
Demux Parallel Mode
Drive DEMUX high and ITL low to place the MAX19542
in the demux parallel mode. In this mode, the output
clock’s frequency is 1/2 the sampling frequency. The
sampling frequency may not be the same as the input
clock frequency. See the
Divide-by-Two Clock Control
(CLKDIV)
section. Each conversion starts with a sam-
pling event on the rising edge of CLKP. Conversion
data now appears on both DA0–DA11 and DB0–DB11.
The first conversion result is output on the A ports on
the rising edge of DCLKP after 12 input clock cycles
from the initial sampling event. The second conversion
result is output on the B ports on the rising edge of
DCLKP after 11 input clock cycles from the initial sam-
pling event. Both conversion results are output simulta-
neously (Figure 6). The conversion results on ports A
and B remain stable for one period of DCLKP after they
become valid. Thus, the overall throughput rate is the
same as in parallel mode; however, now each data line
is allowed to be valid for a longer time (two sampling
periods, one digital clock period). Overrange condi-
tions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
The demux interleaved mode is the recommended
demux mode of operation due to the fact that output
bus switching is more evenly distributed over sample
clock edges.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 15
Figure 7. Demux Interleaved Mode Timing Diagram
Demux Interleaved Mode
Drive DEMUX high and ITL high to place the
MAX19542 in the demux interleaved mode of operation.
In this mode, the output clock’s frequency is 1/2 the
sampling frequency. The sampling frequency may not
be the same as the input clock frequency. See the
Divide-by-Two Clock Control (CLKDIV)
section. Each
conversion starts with a sampling event on the rising
edge of CLKP. Conversion data now appears on both
DA0–DA11 and DB0–DB11. The first conversion result
is output on the A ports on the rising edge of DCLKP
after 12 input clock cycles from the initial sampling
event. The second conversion result is output on the B
ports on the rising edge of DCLKN after 12 input clock
cycles from the initial sampling event. In this way, the two
conversion results are interleaved with respect to each
other (Figure 7). The conversion results on ports A and B
remain stable for one period of DCLKP and DCLKN,
respectively, after they become valid. Overrange condi-
tions are reflected on the appropriate output port, ORA
or ORB, depending on which conversion they occur.
DEMUX INTERLEAVED MODE
tPDL
tCPDL
tLATENCY
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
INN
INP
CLKN
CLKP
RESET
DCLKN
DCLKP
DA0–DA11, ORA
N + 12
N + 1 N + 3
N
N
N + 2
N + 2
N
DB0–DB11, ORB
tCL
tCH
tAD
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
16 ______________________________________________________________________________________
Table 1. MAX19542 Digital Output Coding
INP ANALOG INPUT
VOLTAGE LEVEL
INN ANALOG INPUT
VOLTAGE LEVEL
OVERRANGE
ORA/ORB
BINARY
DIGITAL OUTPUT CODE
(D_11–D_0)
TWO’S-COMPLEMENT
DIGITAL OUTPUT CODE
(D_11–D_0)
> VREF + 0.35V < VREF - 0.35V 1 1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
VREF + 0.35V VREF - 0.35V 0 1111 1111 1111
(+FS)
0111 1111 1111
(+FS)
VREF VREF 0
1000 0000 0000 or
0111 1111 1111
(FS/2)
0000 0000 0000 or
1111 1111 1111
(FS/2)
VREF - 0.35V VREF + 0.35V 0 0000 0000 0000
(-FS)
1000 0000 0000
(-FS)
< VREF + 0.35V > VREF - 0.35V 1 00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
Digital Outputs
(DA0–DA11, DCLKP, DCLKN, ORA,
DB0–DB11, ORB) and Control Input
T
/B
Digital outputs DA0/DB0–DA11/DB11, DCLKP, DCLKN,
ORA/ORB are CMOS compatible, and data on DA0/DB
DA11/DB11 are presented in either binary or two’s-
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input that allows the user to select
the desired output format. Drive T/B high to select data
to be output in offset binary format and drive it low to
select data to be output in two’s complement format on
the 12-bit parallel bus. T/B has an internal pulldown
resistor and can be left unconnected in applications
using only two’s-complement output format. The CMOS
outputs are powered from a separate power supply that
can be operated between 1.7V and 1.9V.
The MAX19542 offers an additional differential output
pair (ORA, ORB) to flag overrange conditions, where
overrange is above positive or below negative full scale.
An overrange condition is identified with ORA/ORB tran-
sitioning high.
Note: Keep the capacitive load on the digital outputs as
low as possible. Use digital buffers on the digital out-
puts of the ADC when driving larger loads to improve
overall performance and reduce system timing con-
straints. Further improvements in dynamic performance
can be achieved by adding small series resistors
(100Ω) to the digital output paths, close to the ADC.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 17
MAX19542
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
1V
AVCC AVCC/2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCE-
SCALING
AMPLIFIER
REFIO
REFADJ
13kΩ TO
100kΩ
0.1µF
REFT
REFB
MAX19542
REFERENCE
BUFFER
ADC FULL SCALE = REFT-REFB
1V
AVCC AVCC/2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCE-
SCALING
AMPLIFIER
REFIO
REFADJ
0.1µF
13kΩ TO 100kΩ
REFT
REFB
Figure 8. Circuit Suggestions to Adjust the ADC’s Full-Scale Range (Simplified Schematic)
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX19542 supports a full-scale adjustment range
of ±10%. To decrease the full-scale range, an external
resistor value ranging from 13kΩto 1MΩcan be added
between REFADJ and AGND. A similar approach can
be taken to increase the ADCs full-scale range. Add a
variable resistor, potentiometer, or predetermined resis-
tor value between REFADJ and REFIO to increase the
full-scale range of the data converter. Figure 8 shows
the two possible configurations and their impact on the
overall full-scale range adjustment of the MAX19542.
Do not use resistor values of less than 13kΩto avoid
instability of the internal gain regulation loop for the
bandgap reference. Use the following formula to calcu-
late the percentage change of the reference voltage:
The percentage change is positive when RADJ is
added between REFADJ and REFIO, and is negative
when RADJ is added between REFADJ and GND.
Vx
k
R
REF ADJ
(%) . % =125 100 Ω
MAX19542
Differential, AC-Coupled, LVPECL-
Compatible Clock Input
The MAX19542 dynamic performance depends on a
very clean clock source. The phase noise floor of the
clock source has a negative impact on the SNR perfor-
mance. Spurious signals on the clock signal source
also affect the ADC’s dynamic range. The preferred
method of clocking the MAX19542 is differentially with
LVPECL-compatible input levels. The fast data transition
rates of these logic families minimize the clock-input cir-
cuitry’s transition uncertainty, thereby improving the SNR
performance. Apply a 50Ωreverse-terminated clock
signal source with low phase noise AC-coupled into a
fast differential receiver such as the MC100LVEL16
(Figure 9). The receiver produces the necessary
LVPECL output levels to drive the clock inputs of the
data converter.
Transformer-Coupled,
Differential Analog Input Drive
The MAX19542 provides the best SFDR and THD with
fully differential input signals and it is not recommend-
ed driving the ADC inputs in single-ended configura-
tion. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
each of the ADC inputs requires only half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solu-
tion to convert a single-ended source signal to a fully
differential signal, required by the MAX19542 for opti-
mum dynamic performance.
A secondary-side termination of a 1:1 transformer (e.g.,
Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω
±0.1% resistors (use tight resistor tolerances to mini-
mize effects of imbalance; 0.1% would be an ideal
choice) placed between top/bottom and center tap of
the transformer is recommended to maximize the
ADC’s dynamic range. This configuration optimizes
THD and SFDR performance of the ADC by reducing
the effects of transformer parasitics. However, the
source impedance combined with the shunt capaci-
tance provided by a PC board and the ADC’s parasitic
capacitance limit the ADC’s full-power input bandwidth
to approximately 600MHz.
To further enhance THD and SFDR performance at high
input frequencies (>100MHz), a second transformer
(Figure 10) should be placed in series with the single-
ended-to-differential conversion transformer. This trans-
former reduces the increase of even-order harmonics
at high frequencies.
For more detailed information on transformer termina-
tion methods, refer to the Application Note: Secondary-
Side Transformer Termination Improves Gain Flatness
in High-Speed ADCs from the Maxim website:
www.maxim-ic.com.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
18 ______________________________________________________________________________________
MC100LVEL16
VGND
AGND OGND
D_0–D_11, OR_
AVCC
VCLK
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
SINGLE-ENDED
INPUT TERMINAL
150Ω
150ΩCLKP
CLKN
OVCC
12
2
8
45
7
6
3
50Ω
510Ω
510Ω
MAX19542
INP
INN
Figure 9. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration
Single-Ended, AC-Coupled Analog Input
Although not recommended, the MAX19542 can be
used in single-ended mode (Figure 11). Analog signals
can be AC-coupled to the positive input INP through a
0.1µF capacitor and terminated with a 49.9Ωresistor to
AGND. Terminate the negative input with a 24.9Ωresis-
tor and AC ground it with a 0.1µF capacitor.
Grounding, Bypassing, and Board
Layout Considerations
The MAX19542 requires board layout design tech-
niques suitable for high-speed data converters. This
ADC provides separate analog and digital power sup-
plies. The analog and digital supply voltage inputs
AVCC and OVCC accept 1.7V to 1.9V input voltage
ranges. Although both supply types can be combined
and supplied from one source, it is recommended
using separate sources to cut down on performance
degradation caused by digital switching currents that
can couple into the analog supply network. Isolate ana-
log and digital supplies (AVCC and OVCC) where they
enter the PC board with separate networks of ferrite
beads and capacitors to their corresponding grounds
(AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor in
parallel with 10µF and 1µF ceramic capacitors.
Additionally, the ADC requires each supply pin to be
bypassed with separate 0.1µF ceramic capacitors
(Figure 12). Locate these capacitors directly at the
ADC supply pins or as close as possible to the
MAX19542. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter, to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. A major concern with this approach are the
dynamic currents that may need to travel long dis-
tances before they are recombined at a common
source ground, resulting in large and undesirable
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 19
AGND OGND
D_0–D_11, OR_
AVCC
INP
50Ω
25Ω
INN
OVCC
12
MAX19542
0.1µF
SINGLE-ENDED
INPUT TERMINAL
0.1µF
Figure 11. Single-Ended AC-Coupled Analog Input Configuration
AGND OGND
D_0–D_11, OR_
AVCC
INP
INN
OVCC
12
MAX19542
0.1µF
25Ω
25Ω
0.1µFADT1-1WT ADT1-1WT
10Ω
10Ω
SINGLE-ENDED
INPUT TERMINAL
Figure 10. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
MAX19542
ground loops. Ground loops can add to digital noise by
coupling back to the analog front end of the converter,
resulting in increased spur activity and a decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
effects of digital noise coupling, ground return vias can
be positioned throughout the layout to divert digital
switching currents away from the sensitive analog sec-
tions of the ADC. This does not require additional
ground splitting, but can be accomplished by placing
substantial ground connections between the analog
front end and the digital outputs.
The MAX19542 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The EP must be
soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow-soldering techniques.
Thermal efficiency is one of the factors for the selection
of a package with an exposed pad for the MAX19542.
The exposed pad improves thermal dissipation and
ensures a solid ground connection between the ADC
and the PC board’s analog ground layer.
Take considerable care when routing the digital output
traces for a high-speed, high-resolution data converter.
It is essential to keep trace lengths at a minimum and
place minimal capacitive loading—less than 5pF—on
any digital trace to prevent coupling to sensitive analog
sections of the ADC. Route high-speed digital signal
traces away from sensitive analog traces, and remove
digital ground and power planes from underneath digital
outputs. Keep all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX19542 are mea-
sured using the histogram method with a 10MHz input
frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX19542’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
20 ______________________________________________________________________________________
AGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
BYPASSING-ADC LEVEL BYPASSING-BOARD LEVEL
ANALOG POWER-
SUPPLY SOURCE
OGND
D_0–D_11, OR_
1µF10µF
0.1µF0.1µF
47µF
AVCC OVCC
12
MAX19542
AVCC
DIGITAL/OUTPUT
DRIVER POWER-
SUPPLY SOURCE
1µF10µF47µF
OVCC
Figure 12. Grounding, Bypassing, and Decoupling Recommendations for the MAX19542
Dynamic Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which defines
the sample-to-sample variation in the aperture delay.
Aperture jitter is measured in psRMS.
Aperture Delay
Aperture delay (tAD) is the time defined between the
620ps rising edge of the sampling clock and the instant
when an actual sample is taken (Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calcula-
tion and should be considered when determining the
SNR of an ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In the case of the MAX19542,
SINAD is computed from a curve fit.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion compo-
nent. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 2nd-order (or higher) inter-
modulation products. The individual input tone levels
are usually set to 7dB below full scale and intermodula-
tion products IM2 through IM5 are considered for the
IMD calculation. The various intermodulation products
are defined as follows:
•2nd-order intermodulation distortion (IM2):
fIN1 + fIN2, fIN2 - fIN1
•3rd-order intermodulation distortion (IM3):
2fIN1 + fIN2, 2fIN1 - fIN2, 2fIN2 + fIN1, 2fIN2 - fIN1
•4th-order intermodulation distortion (IM4):
3fIN1 + fIN2, 3fIN1 - fIN2, 3fIN2 + fIN1, 3fIN2 - fIN1
•5th-order intermodulation distortion (IM5):
4fIN1 + fIN2, 4fIN1 - fIN2, 4fIN2 + fIN1, 4fIN2 - fIN1
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
______________________________________________________________________________________ 21
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLKP
CLKN
Figure 13. Aperture Jitter/Delay Specifications
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
22 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
68 QFN-EP G6800+4 21-0122 90-0245
MAX19542
12-Bit, 170Msps ADC with CMOS
Outputs for Wideband Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
23
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/04 Initial release —
1 10/10 Updated Ordering Information and Electrical Characteristics 1, 3
