GNDDIG
VCCDIG
CHIP_EN
VCCMIX1
GND
GND
NC
NC
GND
MIXinp
MIXinn
VCCMIX2
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36 VCCBBI
GND
BBIoutn
BBIoutp
LOip
LOin
GND
BBQoutp
BBQoutn
GND
VCCBBQ
VCCLO
13 14 15 16 17 18 19 20 21 22 23 24
373839
40
4142
43
44
45
46
47
48
GND
GND
NC
MIXQoutn
GND
NC
REXT
VCCBIAS
GNDBIAS
NC
VCM
CLOCK
DATA
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
READBACK
NC
To Microcontroller
To Microcontroller
TRF371125
RFin
30 kW
To ADC I
To ADC Q
LOin
MIXQoutp
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
INTEGRATED IQ DEMODULATOR
Check for Samples: TRF371125
1FEATURES DESCRIPTION
2• Frequency Range: 700 MHz to 4000 MHz The TRF371125 is a highly linear and integrated
direct-conversion quadrature demodulator. The
• Integrated Baseband Programmable-Gain TRF371125 integrates balanced I and Q mixers, LO
Amplifier buffers, and phase splitters to convert an RF signal
• On-Chip Programmable Baseband Filter directly to I and Q baseband. The on-chip
• High Out-of-Band IP3: 24 dBm at 2400 MHz programmable-gain amplifiers allow adjustment of the
output signal level without the need for external
• High Out-of-Band IP2: 60 dBm at 2400 MHz variable-gain (attenuator) devices. The TRF371125
• Hardware and Software Power Down integrates programmable baseband low-pass filters
• Three-Wire Serial Interface that attenuate nearby interference, eliminating the
need for an external baseband filter.
• Single Supply: 4.5-V to 5.5-V Operation
• Silicon Germanium Technology Housed in a 7-mm × 7-mm QFN package, the
TRF371125 provides the smallest and most
APPLICATIONS integrated receiver solution available for high-
performance equipment.
• Multicarrier Wireless Infrastructure
• WiMAX
• High-Linearity Direct-Downconversion
Receiver
• LTE (Long Term Evolution)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VCCs
GND
Power
Down
CHIP_EN 3
6
41
17
16
7
MIXinp
Gain_B0
MIXQoutn
MIXQoutp
MIXinn
40
39
Gain_B1
Gain_B2
90°
0°
DCOffsetControlI
DCOffsetControlQ
PGA
PGA
ADCDriver
BBIoutp
LOip
BBQoutn
BBIoutn
VCM
BBQoutp
33
31
27
34
24
28
LOin
30
44
45 MIXIoutp
MIXIoutn
ADCDriver
DCOffsetControl
LPFADJControl
PGA ControlQ
SPI
CLOCK
DATA
48
47
46
37
STROBE
READBACK
B0385-01
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS(1)
SPECIFIED
PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT TEMPERATURE
LEAD DESIGNATOR(1) MARKING NUMBER MEDIA, QUANTITY
RANGE
TRF371125IRGZR Tape and Reel, 2500
TRF371125 QFN-48 RGZ –40°C to 85°C TRF371125 TRF371125IRGZT Tape and Reel, 500
FUNCTIONAL DIAGRAM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
2Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TRF371125
GNDDIG
VCCDIG
CHIP_EN
VCCMIX1
GND
GND
NC
NC
GND
MIXinp
MIXinn
VCCMIX2
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36 VCCBBI
GND
BBIoutn
BBIoutp
LOip
LOin
GND
BBQoutp
BBQoutn
GND
VCCBBQ
VCCLO
13 14 15 16 17 18 19 20 21 22 23 24
373839
40
4142
43
44
45
46
47
48
GND
GND
NC
MIXQoutp
MIXQoutn
GND
NC
REXT
VCCBIAS
GNDBIAS
NC
VCM
CLOCK
DATA
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
READBACK
NC
TRF371125
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
DEVICE INFORMATION
PIN ASSIGNMENTS
space
RGZ PACKAGE
QFN-48
(TOP VIEW)
PIN FUNCTIONS
PIN I/O DESCRIPTION
NO. NAME
1 GNDDIG Digital ground
2 VCCDIG Digital power supply
3 CHIP_EN I Chip enable
4 VCCMIX1 Mixer power supply
5 GND Ground
6 MIXinp I Mixer input: positive terminal
7 MIXinn I Mixer input: negative terminal
8 GND Ground
9 VCCMIX2 Mixer power supply
10 NC No connect
11 NC No connect
12 GND Ground
13 GND Ground
14 GND Ground
15 GND Ground
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PIN FUNCTIONS (continued)
PIN I/O DESCRIPTION
NO. NAME
16 MIXQoutp O Mixer Q output: positive terminal
17 MIXQoutn O Mixer Q output: negative terminal
18 NC No connect
19 NC No connect
20 REXT O Reference bias external resistor
21 VCCBIAS Bias block power supply
22 GNDBIAS Bias block ground
23 NC No connect
24 VCM I Baseband common-mode input voltage
25 VCCBBQ Baseband Q chain power supply
26 GND Ground
27 BBQoutn O Baseband Q (in quadrature) output: negative terminal
28 BBQoutp O Baseband Q (in quadrature) output: positive terminal
29 VCCLO Local oscillator power supply
30 Loin I Local oscillator input: negative terminal
31 Loip I Local oscillator input: positive terminal
32 GND Ground
33 BBIoutp O Baseband I (in-phase) output: positive terminal
34 BBIoutn O Baseband I (in-phase) output: negative terminal
35 GND Ground
36 VCCBBI Baseband I (in phase) power supply
37 NC No connect
38 READBACK O SPI readback data
39 Gain_B2 I PGA fast gain control bit 2
40 Gain_B1 I PGA fast gain control bit 1
41 Gain_B0 I PGA fast gain control bit 0
42 NC No connect
43 NC No connect
44 MIXIoutn O Mixer I output: negative terminal
45 MIXIoutp O Mixer I output: positive terminal
46 STROBE I SPI enable
47 DATA I SPI data input
48 CLOCK I SPI clock input
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Supply voltage range(2) –0.3 to 6 V
Digital I/O voltage range –0.3 to 6 V
Operating free-air temperature range, TA–40 to 85 °C
Operating virtual junction temperature range, TJ–40 to 150 °C
Storage temperature range, Tstg –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC Power supply voltage 4.5 5 5.5 V
Power supply voltage ripple 940 µVpp
TAOperating free-air temperature range –40 85 °C
TJOperating virtual junction temperature range –40 150 °C
THERMAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
Soldered slug, no airflow 26
RqJA Soldered slug, 200-LFM airflow 20.1
Thermal resistance, junction-to-ambient °C/W
Soldered slug, 400-LFM airflow 17.4
RqJA(2) 7-mm × 7-mm 48-pin PDFP 25
RqJB Thermal resistance, junction-to-board 7-mm × 7-mm 48-pin PDFP 12 °C/W
(1) Determined using JEDEC standard JESD-51 with high-K board
(2) 16 layers, high-K board
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
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ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA= 25°C (unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
DC PARAMETERS
ICC Total supply current 360 mA
Power-down current 2 mA
IQ DEMODULATOR AND BASEBAND SECTION
fRF Frequency range 700 4000 MHz
Gain range 22 24 dB
Gain step See(1) 1 dB
Pinmax Max. RF power input Before damage 25 dBm
OIP3 Output third-order intercept point Gain setting = 24(2) 30 dBVrms
P1dBmin Min. output compression point 1 tone(3) 3 dBVrms
Min. baseband low-pass filter cutoff
fmin 1–dB point(4) 700 kHz
frequency
Max. baseband low-pass filter cutoff
fmax 3–dB point(4) 15 MHz
frequency
fbypass Baseband low-pass filter cutoff frequency in 3–dB point(5) 30 MHz
bypass mode 1 × fC1
1.5 × fC8
2 × fC32
Baseband relative attenuation at LPF cutoff
Fsel dB
frequency (fC)(6) 3 × fC54
4 × fC75
5 × fC90
Image suppression –40 dB
Output BB attenuator 3 dB
Parallel resistance 1 kΩ
Output load impedance Parallel capacitance 20 pF
Measured at I- and Q-channel
Vcm Output, common-mode 1.5 V
baseband outputs
Second harmonic(7) –100 dBc
Baseband harmonic level Third harmonic(7) –93 dBc
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency 700 4000 MHz
LO input level See(8) –3 0 6 dBm
LO leakage At MIXinn/p at 0-dBm LO drive level –58 dBm
DIGITAL INTERFACE
VIH High-level input voltage 0.6 × VCC 5 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage 0.8 × VCC V
VOL Low-level output voltage 0.2 × VCC V
(1) Two consecutive gain settings
(2) Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
(3) Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
(4) Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to max bandwidth;
LPFADJ = 255 corresponds to minimum BW.
(5) Filter Ctrl setting equal to 0
(6) Attenuation relative to passband gain
(7) LO frequency set to 2.4 GHz. Power-in set to –40 dBm. Gain setting at 24. DC offset calibration engaged. Input signal set at 2.5-MHz
offset.
(8) LO power outside of this range is possible but may introduce degraded performance.
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA= 25°C(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fLO = 700 MHz
Gmax Maximum gain(2) Gain setting = 24 50 dB
NF Noise figure Gain setting = 24 8.5 dB
IIP3 Third-order input intercept point Gain setting = 24(3)(4) 14 dBm
IIP2 Second-order input intercept point Gain setting = 24(4)(5) 60 dBm
fLO = 1740 MHz
Gmax Maximum gain(2) Gain setting = 24 44 dB
NF Noise figure Gain setting = 24 11 dB
IIP3 Third-order input intercept point Gain setting = 24(3)(4) 22 dBm
IIP2 Second-order input intercept point Gain setting = 24(4)(5) 60 dBm
fLO = 1950 MHz
Gmax Maximum gain(2) Gain setting = 24 43 dB
NF Noise figure Gain setting = 24 12 dB
IIP3 Third-order input intercept point Gain setting = 24(3)(4) 23 dBm
IIP2 Second-order input intercept point Gain Setting = 24(4)(5) 60 dBm
fLO = 2025 MHz
Gmax Maximum gain(2) Gain setting = 24 42.5 dB
N3F Noise figure Gain setting = 24 12.5 dB
IIP3 Third-order input intercept point Gain setting = 24(3)(4) 22 dBm
IIP2 Second-order input intercept point Gain setting = 24(4)(5) 60 dBm
fLO = 2400 MHz
Gmax Maximum gain(2) Gain setting = 24 40 dB
NF Gain setting = 24 13.5 dB
Noise figure Gain setting = 16 15 dB
IIP3 Third-order input intercept point Gain setting = 24(3)(4) 24 dBm
IIP2 Second-order input intercept point Gain setting = 24(4)(5) 60 dBm
(1) For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO input. For frequency band between
2100 MHz and 2700 MHz the Murata balun LDB212G4005C-001 is used. Performance parameters adjusted for balun insertion loss.
Recommended baluns for respective frequency band is shown below:
700 MHz: Murata LDB21897M005C-001 (or equivalent)
1740 MHz: Murata LDB211G8005C-001 (or equivalent)
1950 MHz: Murata LDB211G9005C-001 (or equivalent)
2025 MHz: Murata LDB211G9005C-001 (or equivalent)
2500 MHz: Murata LDB212G4005C-001 (or equivalent)
3500 MHz: Johanson 3600BL14M050E (or equivalent)
(2) Gain defined as voltage gain from Mixin (Vrms) to either baseband output: BBI/Qout (Vrms)
(3) Two CW tones of –30 dBm at fRF1 = fLO ±(2 × fC) and fRF2 = fLO ±[(4 × fC) + 100 kHz] (fC= baseband filter 1-dB cutoff frequency).
(4) Because the 2-tone interferers are outside of the baseband filter bandwidth, the results are inherently independent of the gain setting.
Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best.
(5) Two CW tones at –30 dBm at fRF1 = fLO ±2 × fCand fRF2 = fLO ±[(2 × fC) + 100 kHz]; IM2 product measured at 100-kHz output frequency
(fC= baseband filter 1-dB cutoff frequency)
TIMING REQUIREMENTS
VCC = 5 V, LO power = 0 dBm, TA= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(CLK) Clock period 50 ns
tsu1 Setup time, data 10 ns
thHold time, data 10 ns
twPulse width, STROBE 20 ns
tsu2 Setup time, STROBE 10 ns
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TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Table of Graphs
Gain vs LO frequency(1)(2) Figure 1,Figure 2,Figure 3
Noise figure vs LO frequency(1)(2) Figure 4,Figure 5,Figure 6
IIP3 vs LO frequency(3)(4)(5) Figure 7,Figure 8,Figure 9
IIP2 vs LO frequency(3)(4)(5) Figure 10,Figure 11,Figure 12
Gain vs LO frequency Figure 13,Figure 14,Figure 15
IIP3 vs LO frequency(4)(5) Figure 16,Figure 17,Figure 18,Figure 19
IIP2 vs LO frequency(4)(5) Figure 20,Figure 21,Figure 22,Figure 23
Optimized IIP2 vs LO frequency(4)(5)(6) Figure 24
Optimized IIP3 vs LO frequency(4)(5)(6) Figure 25
Noise figure vs LO frequency Figure 26,Figure 27,Figure 28
OIP3 vs Frequency offset(7) Figure 29,Figure 30,Figure 31,Figure 32
Noise figure vs BB gain setting Figure 33
Gain vs BB gain setting Figure 34
Gain vs Frequency offset Figure 35,Figure 36
Gain vs Frequency offset (bypass mode) Figure 37,Figure 38
1-dB LPF corner frequency vs LPFADJ setting Figure 39
Relative LPF group delay vs Frequency offset(8) Figure 40
Image rejection vs BB frequency offset Figure 41
DC offset limit vs Temperature(9) Figure 42
Out-of-band P1dB vs Relative offset multiplier to corner frequency(10) Figure 43
(1) Measured with broadband Picosecond 5310A balun on the LO input and single ended connection on the RF input. Performance gain
adjusted for the 3 dB differential to single-ended insertion loss.
(2) Performance ripple due to impedance mismatch on the RF input.
(3) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the
measurement.
(4) Out-of-band intercept point is defined with tones that are at least 2 times farther out than the programmed LPF corner frequency that
generate an intermodulation tone that falls inside the LPF passband.
(5) Out-of-band intercept point is dependent on the demodulator performance and not the baseband circuitry; the measurement is taken at
max gain but is valid across all PGA settings.
(6) Optimized intercept point within the band 2.5 to 2.7 GHz is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff
Trim, Filter trim, Out Buff Trim to: 2, 3, 0, 1, 2, 1 respectively.
(7) Measured with filter in bypass mode to characterize the passband circuitry across baseband frequencies.
(8) Relative to the low frequency offset group delay in bypass mode.
(9) Idet set to 50 µA; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Clk Div set to 1024.
(10) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer
tone is increased until in-band tone compresses 1 dB.
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Product Folder Link(s): TRF371125
LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
34
36
38
40
42
44
46
48
50
52
G001
See Notes 1 and 2
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
34
36
38
40
42
44
46
48
50
52
G002
See Notes 1 and 2
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
34
36
38
40
42
44
46
48
50
52
G003
See Notes 1 and 2
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
6
8
10
12
14
16
18
20
22
G004
See Notes 1 and 2
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
6
8
10
12
14
16
18
20
22
G005
See Notes 1 and 2
VCC = 4.5V
VCC = 5 V
VCC = 5.5V
LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
500 1000 1500 2000 2500 3000 3500 4000
6
8
10
12
14
16
18
20
22
G006
See Notes 1 and 2
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 1. Figure 2.
Figure 3. Figure 4.
Figure 5. Figure 6.
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
10
12
14
16
18
20
22
24
26
28
30
32
34
36
500 1000 1500 2000 2500 3000 350 400
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
IIP3 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
10
12
14
16
18
20
22
24
26
28
30
32
34
36
G007
See Notes 3, 4 and 5
TRF371125
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 7.
10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
12
14
16
18
20
22
24
26
28
30
32
34
500 1000 1500 2000 2500 3000 350 400
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
IIP3 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
12
14
16
18
20
22
24
26
28
30
32
34
G008
See Notes 3, 4 and 5
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 8.
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
12
14
16
18
20
22
24
26
28
30
32
34
500 1000 1500 2000 2500 3000 350 400
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
LO Frequency (MHz)
IIP3 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
12
14
16
18
20
22
24
26
28
30
32
34
G009
See Notes 3, 4 and 5
TRF371125
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 9.
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IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
500 1000 1500 2000 2500 3000 350 400
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
IIP2 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
G010
See Notes 3, 4 and 5
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 10.
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IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
500 1000 1500 2000 2500 3000 350 400
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
IIP2 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
G011
See Notes 3, 4 and 5
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 11.
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IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
500 1000 1500 2000 2500 3000 350 400
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
LO Frequency (MHz)
IIP2 (dBm)
Q
500 1000 1500 2000 2500 3000 3500 4000
30
40
50
60
70
80
90
100
G012
See Notes 3, 4 and 5
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 12.
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LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
36
37
38
39
40
41
42
43
44
G013
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
36
37
38
39
40
41
42
43
44
G014
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
Gain (dB)
GAIN vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
36
37
38
39
40
41
42
43
44
G015
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 13. Figure 14.
Figure 15.
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
210 220 230 240 250 260 270
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
IIP3 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
See Notes 4 and 5
G016
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 16.
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
210 220 230 240 250 260 270
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
IIP3 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
See Notes 4 and 5
G017
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 17.
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Product Folder Link(s): TRF371125
IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
210 220 230 240 250 260 270
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
LO Frequency (MHz)
IIP3 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
See Notes 4 and 5
G018
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 18.
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IIP3 (dBm)
IIP3 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
210 220 230 240 250 260 270
LPFADJ = 0
LPFADJ = 24
LPFADJ = 82
LPFADJ = 142
LO Frequency (MHz)
IIP3 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
10
12
14
16
18
20
22
24
26
28
30
32
34
See Notes 4 and 5
G019
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 19.
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Product Folder Link(s): TRF371125
IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
210 220 230 240 250 260 270
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
IIP2 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
See Notes 4 and 5
G020
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 20.
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IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
210 220 230 240 250 260 270
VCC = 4.5V
VCC = 5V
VCC = 5.5V
LO Frequency (MHz)
IIP2 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
See Notes 4 and 5
G021
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 21.
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Product Folder Link(s): TRF371125
IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
210 220 230 240 250 260 270
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
LO Frequency (MHz)
IIP2 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
See Notes 4 and 5
G022
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 22.
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IIP2 (dBm)
IIP2 vs LO FREQUENCY
W
I
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
210 220 230 240 250 260 270
LPFADJ = 0
LPFADJ = 24
LPFADJ = 82
LPFADJ = 142
LO Frequency (MHz)
IIP2 (dBm)
Q
2100 2200 2300 2400 2500 2600 2700
20
30
40
50
60
70
80
90
100
See Notes 4 and 5
G023
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 23.
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Optimized IIP2 (dBm)
OPTIMIZED IIP2 vs LO FREQUENCY
W
I
2500 2525 2550 2575 2600 2625 2650 2675 2700
30
35
40
45
50
55
60
65
70
75
80
85
90
250 2520 2550 2575 2600 2625 2650 2675 270
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Optimized IIP2 (dBm)
Q
2500 2525 2550 2575 2600 2625 2650 2675 2700
30
35
40
45
50
55
60
65
70
75
80
85
90
See Notes 4, 5 and 6
G024
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 24.
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Optimized IIP3 (dBm)
OPTIMIZED IIP3 vs LO FREQUENCY
W
I
2500 2525 2550 2575 2600 2625 2650 2675 2700
12
14
16
18
20
22
24
26
28
30
32
34
250 2520 2550 2575 2600 2625 2650 2675 270
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Optimized IIP3 (dBm)
Q
2500 2525 2550 2575 2600 2625 2650 2675 2700
12
14
16
18
20
22
24
26
28
30
32
34
See Notes 4, 5 and 6
G025
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 25.
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LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
10
11
12
13
14
15
16
17
18
19
20
G026
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
10
11
12
13
14
15
16
17
18
19
20
G027
VCC = 4.5V
VCC = 5 V
VCC = 5.5V
LO Frequency (MHz)
Noise Figure (dB)
NOISE FIGURE vs LO FREQUENCY
2100 2200 2300 2400 2500 2600 2700
10
11
12
13
14
15
16
17
18
19
20
G028
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
Frequency Offset (MHz)
OIP3 (dBm)
OIP3 vs FREQUENCY OFFSET
32
34
36
38
40
42
44
46
48
50
0 5 10 15 20 25
G031
See Note 7
BB Gain = 12dB
BB Gain = 16dB
BB Gain = 20dB
BB Gain = 24dB
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 26. Figure 27.
Figure 28. Figure 29.
Figure 30. Figure 31.
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Frequency Offset (MHz)
OIP3 (dBm)
OIP3 vs FREQUENCY OFFSET
32
34
36
38
40
42
44
46
48
50
0 5 10 15 20 25
G032
See Note 7
3dB Attn On
3dB Attn Off
BB Gain Setting
Noise Figure (dB)
NOISE FIGURE vs BB GAIN SETTING
0 2 4 6 8 10 12 14 16 18 20 22 24
13
16
19
22
25
28
G033
3dB Attn On
3dB Attn Off
BB Gain Setting
Gain (dB)
GAIN vs BB GAIN SETTING
0 2 4 6 8 10 12 14 16 18 20 22 24
13
16
19
22
25
28
31
34
37
40
43
G034
3dB Attn On
3dB Attn Off
Frequency Offset (MHz)
Gain (dB)
GAIN vs FREQUENCY OFFSET
0.1 1 10 100
-100
-80
-60
-40
-20
0
20
G035
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
Frequency Offset (MHz)
Gain (dB)
GAIN vs FREQUENCY OFFSET
0.1 1 10 100
-5
-4
-3
-2
-1
0
1
2
3
4
5
G036
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
Frequency Offset (MHz)
Gain (dB)
GAIN vs FREQUENCY OFFSET
0.1 1 10 100 1000
-100
-80
-60
-40
-20
0
20
G037
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 32. Figure 33.
Figure 34. Figure 35.
Figure 36. Figure 37. Bypass Mode
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Frequency Offset (MHz)
Gain (dB)
GAIN vs FREQUENCY OFFSET
0.1 1 10 100
-5
-4
-3
-2
-1
0
1
2
3
4
5
G038
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
LPFADJ Setting
1-dB LPF Corner Frequency (MHz)
1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING
0 50 100 150 200 250
0
2
4
6
8
10
12
14
16
G039
Frequency Offset (MHz)
Relative LPF Group Delay (ns)
RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET
0.1 1 10 100
-100
0
100
200
300
400
500
G040
See Note 8 Bypass
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
BB Frequency Offset (MHz)
Image Rejection (dB)
IMAGE REJECTION vs BB FREQUENCY OFFSET
-25 -20 -15 -10 -5 0 5 10 15 20 25
-60
-50
-40
-30
-20
-10
0
G041
Temperature (°C)
DC Offset Limit (mV)
DC OFFSET LIMIT vs TEMPERATURE
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85
-60
-40
-20
0
20
40
60
G042
See Note 9
Relative Offset Multiplier to Corner Frequency
Out-of-Band P1dB (dBm)
OUT-OF-BAND P1dB vs
REL OFFSET MULTIPLIER to CORNER FREQUENCY
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-25
-20
-15
-10
-5
0
5
10
15
G043
See Note 10
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA= 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Figure 38. Bypass Mode Figure 39.
Figure 40. Figure 41.
Figure 42. Figure 43.
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CLOCK
DATA
Register Write
CLOCK
STROBE
READBACK
READBACK
DATA
tsu1
tsu2
th
tw
t(CLK)
1
Write
CLOCK
Pulse
st
32
Write
CLOCK
Pulse
nd 32
Read
CLOCK
Pulse
nd 33
Read
CLOCK
Pulse
rd
2
Read
CLOCK
Pulse
nd
1
Read
CLOCK
Pulse
st
32
Write
CLOCK
Pulse
nd
"EndofWrite
Cycle"Pulse
"EndofWrite
Cycle"Pulse
DB0 (LSB)
Address Bit 0
DB1
AddressBit1
DB2
AddressBit2
DB3
AddressBit3
DB29
READBACKDATA
Bit29
DB30
READBACKDATA
Bit30
DB31 (MSB)
READBACKDATA
Bit31
td
READBACK
Data Bit0
READ
BACK
Data
Bit1
READ
BACK
Data
Bit29
READBACK
Data Bit30
READBACK
Data Bit31
T0265-02
Latch
Enable
tsu2 tw
t(CL) t(CH)
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
REGISTER INFORMATION
SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF371125 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift
register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous
to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first
two bits (DB0–DB1) are the address to select the available internal registers.
READBACK Mode
The TRF371125 implements the capability to read back the content of the serial programming interface registers.
In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an
auto dc-offset calibration. Each readback is composed by two phases: writing followed by the actual reading of
the internal data (see timing diagram in Figure 44).
During the writing phase, a command is sent to the TRF371125 to set it in readback mode and to specify which
register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into
the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high
(end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the
READBACK pin.
Figure 44. Serial Programming Timing Diagram
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Table 1. Register Summary(1)
Bit # Reg 1 Reg 2 Bit # Reg 3 Reg 5 Bit # Reg 0
Bit0 Bit0 Bit0
Bit1 Register address Register address Bit1 Register address Register address Bit1 Register address
Bit2 Bit2 Bit2
Bit3 Bit3 Bit3
SPI bank addr SPI bank addr SPI bank addr SPI bank addr SPI bank addr
Bit4 Bit4 Bit4
Bit5 PWD RF En auto-cal Bit5 Bit5
Mix GM trim ID
Bit6 NU Bit6 Bit6
Bit7 PWD buf Bit7 Bit7
ILoadA Mix LO trim
Bit8 P Bit8 Bit8
Bit9 NU Bit9 Bit9
IDAC for dc offset LO trim
Bit10 PWD DC OFF DIG Bit10 Bit10
Bit11 NU Bit11 Bit11 NU
Mix buf trim
Bit12 Bit12 Bit12
Bit13 Bit13 Bit13
ILoadB Fltr trim
Bit14 BB gain Bit14 Bit14
Bit15 Bit15 Bit15
Out buf trim
Bit16 Bit16 Bit16
Bit17 Bit17 Bit17
QDAC for dc offset
Bit18 Bit18 Bit18
Bit19 Bit19 Bit19
QLoadA DC offset Q DAC
Bit20 Bit20 Bit20
LPFADJ
Bit21 Bit21 Bit21
Bit22 Bit22 Bit22
IDet
Bit23 Bit23 Bit23
Bit24 Cal sel Bit24 NU Bit24
Bit25 Bit25 Bit25
DC detector QLoadB
bandwidth
Bit26 CLK div ratio Bit26 Bit26
Bit27 Fast gain Bit27 Bit27 DC offset I DAC
Bit28 Gain sel Cal clk sel Bit28 Bit28
Bit29 Osc test Bit29 Bypass Bit29
Bit30 NU Osc trim Bit30 Bit30
Fltr ctrl
Bit31 En 3dB attn Bit31 Bit31
(1) Register 4 is not used.
Table 2. Register 1 Device Setup
REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 0 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1 SPI bank address
Bit4 ADDR<4> 0
Bit5 PWD_MIX 0 Mixer power down (Off = 1)
Bit6 NU 0 Not used
Bit7 PWD_BUF 1 Mixer out test buffer power down (Off = 1)
Bit8 PWD_FILT 0 Baseband filter power down (Off = 1)
Bit9 NU 0 Not used
Bit10 PWD_DC_OFF_DIG 1 DC offset calibration power down (Off = 1)
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Table 2. Register 1 Device Setup (continued)
REGISTER 1 NAME RESET VALUE WORKING DESCRIPTION
Bit11 NU 1 Not used
Bit12 BBGAIN_0 1 Baseband gain setting. Default = 15. Range is from 0 (minimum gain
Bit13 BBGAIN_1 1 setting) to 24 (maximum gain setting). See the Application Information
Bit14 BBGAIN_2 1 section for more information on gain setting and fast gain control
Bit15 BBGAIN_3 1 options.
Bit16 BBGAIN_4 0
Bit17 LPFADJ_0 0
Bit18 LPFADJ_1 0
Bit19 LPFADJ_2 0 Sets programmable low-pass filter corner frequency. Range = 255
Bit20 LPFADJ_3 0 (lowest corner frequency) to 0 (highest corner frequency). Default value
Bit21 LPFADJ_4 0 is 128.
Bit22 LPFADJ_5 0
Bit23 LPFADJ_6 0
Bit24 LPFADJ_7 1
Bit25 EN_FLT_B0 0 Selects dc offset detector filter bandwidth.
Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz}
Bit26 EN_FLT_B1 0
Bit27 EN_FASTGAIN 0 Enable external fast-gain control
Bit28 GAIN_SEL 0 Fast-gain control multiplier bit (×2 = 1)
Bit29 OSC_TEST 0 Enables osc out on readback pin if = 1
Bit30 NU 0 Not used
Bit31 EN 3dB Attn 0 Enables output 3-dB attenuator
EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff
frequencies of the detector bandwidth are summarized in the following table (see the Application Information
section for more detail on the dc offset calibration and the detector bandwidth).
EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQ NOTES
x 0 10 MHz Maximum bandwidth, bypass R, C
0 1 10 kHz Enable R
1 1 1 kHz Minimum bandwidth, enable R, C
Table 3. Register 2 Device Setup
REGISTER 2 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 0
Bit1 ADDR<1> 1 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1 SPI bank address
Bit4 ADDR<4> 0
Bit5 EN_AUTOCAL 0 Enable autocal when = 1; reset to 0 when done.
Bit6 IDAC_BIT0 0
Bit7 IDAC_BIT1 0
Bit8 IDAC_BIT2 0
Bit9 IDAC_BIT3 0 I-DAC bits to be set during manual dc offset cal
Bit10 IDAC_BIT4 0
Bit11 IDAC_BIT5 0
Bit12 IDAC_BIT6 0
Bit13 IDAC_BIT7 1
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Table 3. Register 2 Device Setup (continued)
REGISTER 2 NAME RESET VALUE WORKING DESCRIPTION
Bit14 QDAC_BIT0 0
Bit15 QDAC_BIT1 0
Bit16 QDAC_BIT2 0
Bit17 QDAC_BIT3 0 Q-DAC bits to be set during manual dc offset cal
Bit18 QDAC_BIT4 0
Bit19 QDAC_BIT5 0
Bit20 QDAC_BIT6 0
Bit21 QDAC_BIT7 1
Bit22 IDET_B0 1 Set reference current for digital calibration; Settings {00 to 11}
= {50 µA to 200 µA}. Setting 00 = highest resolution.
Bit23 IDET_B1 1
Bit24 CAL_SEL 1 DC offset calibration select. 0 = manual cal; 1 = autocal.
Bit25 Clk_div_ratio<0> 0 Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048,
Bit26 Clk_div_ratio<1> 0 16684}. A higher div ratio (slower clk) improves cal accuracy and
reduces speed.
Bit27 Clk_div_ratio<2> 0
Bit28 Cal_clk_sel 1 Select internal oscillator when 1, SPI clk when 0
Bit29 Osc_trim<0> 1 Internal oscillator frequency trimming; Setting {000} = ~300 kHz;
Bit30 Osc_trim<1> 1 Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz.
Bit31 Osc_trim<2> 0
Table 4. Register 3 Device Setup
REGISTER 3 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 1 Register address
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1 SPI bank address
Bit4 ADDR<4> 0
Bit5 ILOAD_a<0> 0
Bit6 ILOAD_a<1> 0
Bit7 ILOAD_a<2> 0 I mixer offset side A
Bit8 ILOAD_a<3> 0
Bit9 ILOAD_a<4> 0
Bit10 ILOAD_a<5> 0
Bit11 ILOAD_b<0> 0
Bit12 ILOAD_b<1> 0
Bit13 ILOAD_b<2> 0 I mixer offset side B
Bit14 ILOAD_b<3> 0
Bit15 ILOAD_b<4> 0
Bit16 ILOAD_b<5> 0
Bit17 QLOAD_a<0> 0
Bit18 QLOAD_a<1> 0
Bit19 QLOAD_a<2> 0 Q mixer offset side A
Bit20 QLOAD_a<3> 0
Bit21 QLOAD_a<4> 0
Bit22 QLOAD_a<5> 0
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Table 4. Register 3 Device Setup (continued)
REGISTER 3 NAME RESET VALUE WORKING DESCRIPTION
Bit23 QLOAD_b<0> 0
Bit24 QLOAD_b<1> 0
Bit25 QLOAD_b<2> 0 Q mixer offset side B
Bit26 QLOAD_b<3> 0
Bit27 QLOAD_b<4> 0
Bit28 QLOAD_b<5> 0
Bit29 Bypass 0 Engage filter bypass
Bit30 Fltr Ctrl_b<0> 1 Used to adjust for filter peaking response; set to 0 in bypass mode, 1
otherwise
Bit31 Fltr Ctrl_b<1> 0
I/Q Mixer Load A/B: these bits adjust the load on the mixer output. All values should be 0. No modification is
necessary.
Register 4: No programming required for Register 4
Table 5. Register 5 Device Setup
REGISTER 5 NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 1
Bit1 ADDR<1> 0 Register address
Bit2 ADDR<2> 1
Bit3 ADDR<3> 1 SPI bank address
Bit4 ADDR<4> 0
Bit5 MIX_GM_TRIM<0> 1 Mixer gm current trim
Bit6 MIX_GM_TRIM<1> 0
Bit7 MIX_LO_TRIM<0> 1 Mixer switch core VCM trim
Bit8 MIX_LO_TRIM<1> 0
Bit9 LO_TRIM<0> 1 LO buffers current trim
Bit10 LO_TRIM<1> 0
Bit11 MIX_BUFF_TRIM<0> 1 Mixer output buffer current trim
Bit12 MIX_BUFF_TRIM<1> 0
Bit13 FLTR_TRIM<0> 1 Filter current trim
Bit14 FLTR_TRIM<1> 0
Bit15 OUT_BUFF_TRIM<0> 1 Filter output buffer current trim
Bit16 OUT_BUFF_TRIM<1> 0
Bit17 0
Bit18 0
Bit19 0
Bit20 0
Bit21 0
Bit22 0
Bit23 0
Bit24 NU 0 Not used
Bit25 0
Bit26 0
Bit27 0
Bit28 0
Bit29 0
Bit30 0
Bit31 0
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Trims: the trim values allow for minor bias adjustments of internal stages. Generally it is recommended to leave
all trim values at the default value of 1. Linearity performance improvement over a small band of frequencies is
possible by selective adjustment of the trim values. Optimized intercept point within the band 2.5 GHz to 2.7 GHz
is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff Trim, Filter Trim, Out Buff Trim to:
2, 3, 0, 1, 2, 1, respectively.
Readback (Write Command)
0 0 0 1 0 Zero Fill
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
Zero fill Register address 1
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31
Reg 0:DAC/Device ID Readback
Register Address SPI Bank Addr ID NU
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
DC offset Q DAC DC offset I DAC
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31
Table 6. Register 0 Device Setup (Read-Only)
READBACK REGISTER NAME RESET VALUE WORKING DESCRIPTION
Bit0 ADDR<0> 0
Bit1 ADDR<1> 0 Select SPI reg 1 to 5
Bit2 ADDR<2> 0
Bit3 ADDR<3> 1 Select SPI bank 1 to 3
Bit4 ADDR<4> 0
Bit5 ID<0> 1 Version ID: 01 = –25
Bit6 ID<1> 0
Bit7 0
Bit8 0
Bit9 0
Bit10 0
Bit11 NU 0 Not used
Bit12 0
Bit13 0
Bit14 0
Bit15 0
Bit16 DC_OFFSET_Q<0> 0
Bit17 DC_OFFSET_Q<1> 0
Bit18 DC_OFFSET_Q<2> 0
Bit19 DC_OFFSET_Q<3> 0 DC offset DAC Q register
Bit20 DC_OFFSET_Q<4> 0
Bit21 DC_OFFSET_Q<5> 0
Bit22 DC_OFFSET_Q<6> 0
Bit23 DC_OFFSET_Q<7> 1
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 35
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Table 6. Register 0 Device Setup (Read-Only) (continued)
READBACK REGISTER NAME RESET VALUE WORKING DESCRIPTION
Bit24 DC_OFFSET_I<0> 0
Bit25 DC_OFFSET_I<1> 0
Bit26 DC_OFFSET_I<2> 0
Bit27 DC_OFFSET_I<3> 0 DC offset DAC I register
Bit28 DC_OFFSET_I<4> 0
Bit29 DC_OFFSET_I<5> 0
Bit30 DC_OFFSET_I<6> 0
Bit31 DC_OFFSET_I<7> 1
36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TRF371125
SPI
X
(x1,x2)
FastGainSelect
+Composite
PGA Setting
(min:0,max24)
Gain_B2
Gain_B1
Gain_B0
B0386-01
TRF371125
www.ti.com
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
APPLICATION INFORMATION
Gain Control
The TRF371125 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range
with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits<12,16>). Alternatively,
the PGA can be programmed by a combination of 5 bits programmed through the SPI and 3 parallel external bits
(pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly without having
to reprogram the SPI registers. The fast gain control multiplier bit (register 1, bit 28) sets the step size of each bit
to either 1 dB or 2 dB. This allows a fast gain reduction of 0 dB to 7 dB in 1-dB steps or 0 dB to 14 dB in 2-dB
steps.
The PGA gain control word (BBgain<0,4>) can be programmed to a setting between 0 and 24. This word is the
SPI programmed gain (register 1 bits<12,16>) minus the parallel external 3 bits as shown in Figure 45. Note that
the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain setting
to 17 and use the fast-gain control bits to protect the analog-to-digital converter in the event of a strong input
jammer signal.
Figure 45. PGA Gain Control Word
For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19.
Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to 101 (binary)
corresponding to 5-dB reduction.
Automated DC Offset Calibration
The TRF371125 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q
paths. The internal calibration requires a clock in order to function. The TRF371125 can use the internal
relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is
selected by setting the Cal_Sel_Clk (register 2, bit 28) to 1. The internal oscillator frequency is set through the
Osc_Trim bits (register 2, bits <29,31>). The frequency of the oscillator is detailed in Table 7; however, it is
expected the actual frequency of operation can vary plus or minus 35% due to process variations. The oscillator
frequency can be monitored on the READBACK pin when the Osc_Test register (Register 1, bit 29) is set to 1.
Table 7. Internal Oscillator Frequency Control
Osc_Trim<2> Osc_Trim<1> Osc_Trim<0> FREQUENCY
0 0 0 300 kHz
0 0 1 500 kHz
0 1 0 700 kHz
0 1 1 900 kHz
1 0 0 1.1 MHz
1 0 1 1.3 MHz
1 1 0 1.5 MHz
1 1 1 1.8 MHz
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): TRF371125
c
(Auto_Cal_Clk_Cycles) (Clk_Divider)
=Osc_Freq
´
t
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
The default setting of these registers corresponds to a 900-kHz oscillator frequency. This is sufficient for
autocalibration; modification is not required except for faster calibration convergence.
The output full-scale range of the internal dc offset correction DACs is programmable (IDET_B<0,1, register 2
bit<22,23>). The range is shown in Table 8.
Table 8. DC Offset Correction DAC Programmable Range
I(Q) Det_B0 I(Q) Det_B1 Full Scale
0 0 50 µA
0 1 100 µA
1 0 150 µA
1 1 200 µA
The I- and Q-channel output maximum dc offset correction range can be calculating by multiplying the values in
the table by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed
maximum correction range. For optimum resolution and best correction, the dc offset DAC range should be set to
50 µA with the PGA gain set for the nominal condition. The dc offset correction DAC output is affected by a
change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGA gain
during normal operation does not significantly impair the dc offset balance. For example, if the optimized
calibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains less than 10 mV
balance as the gain is adjusted ±7 dB.
The dc offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 2,
bit 24) is set to 1. At start-up, the internal registers are loaded at half scale corresponding to a decimal value of
128. The auto-cal is initiated by toggling the EN_AUTOCAL bit (register 2, bit 5) to 1. When the calibration is
over, this bit is automatically reset to 0. During calibration, the RF local oscillator must be applied. The dc offset
DAC state is stored in the internal registers and maintained as long as the power supply is kept on or until a new
calibration is started.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration
bandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cutoff
frequency of the RC low-pass filter in front of the detector (register 1, bits 25–26). EN_FLT_B0 controls the
resistor (bypass = 1) and EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff frequencies of
the detector bandwidth are summarized in Table 9. The speed of the clock can be slowed down by selecting a
clock divider ratio (register 2, bits 25–27).
Table 9. Detector Bandwidth Settings
EN_FLT_B1 EN_FLT_B0 TYPICAL 3-dB CUTOFF FREQUENCY NOTES
X 0 10 MHz Maximum bandwidth, bypass R, C
0 1 10 kHz Enable R
1 1 1 kHz Minimum bandwidth, enable R, C
The detector has more averaging time with a slower clock; hence, it is desirable to slow down the clock speed for
a given condition to achieve optimum results. For example, if there is no RF present on the RF input port, the
detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-128. The autocalibration
yields a dc offset balance between the differential baseband output ports (I and Q) that is less than 15 mV. Some
minor improvement may be obtained by increasing the averaging of the detector by increasing the clock divider
up to 256 or 1024.
On the other hand, if there is a modulated RF signal present at the input port, it is desirable to reduce the
detector bandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz
corner frequency. With the modulated signal present and with the detection bandwidth reduced, additional
averaging is required to get the optimum results. A clock divider setting of 1024 will yield optimum results.
Of course, an increase in the averaging is possible by increasing the clock divider at the expense of longer
converging time. The convergence time can be calculated by the following:
(1)
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Product Folder Link(s): TRF371125
c
(9) (1024)
= = 10.24 ms
900 kHz
´
t
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
The dc offset calibration converges in approximately nine cycles. For the case with a clock divider of 1024 and
with the nominal oscillator frequency of 900 kHz, the convergence time is:
(2)
Alternate Method for Adjusting DC Offset
The internal registers controlling the internal dc current DAC are accessible through the SPI, providing a user-
programmable method for implementing the dc offset calibration. To employ this option the CAL_SEL bit must be
set to 0. During this calibration, an external instrument monitors the output dc offset between the I/Q differential
outputs and programs the internal registers (IDAC_BIT<0,7> and QDAC_BIT<0,7> bits) to cancel the dc offset.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): TRF371125
M0177-01
Ø0.008 (0.203)
0.025 (0.635)
0.200 (5.08)
0.200 (5.08)
0.0125 (0.318)
Note: Dimensions are in inches (mm)
0.025 (0.635)
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
PCB Layout Guidelines
The TRF371125 device is fitted with a ground slug on the back of the package that must be soldered to the PCB
ground with adequate ground vias to ensure a good thermal and electrical connection. The recommended via
pattern and ground pad dimensions are shown in Figure 46. The recommended via diameter is 8 mils (0.2 mm).
The ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground.
Additional ground vias may be added if space allows. The no-connect (NC) pins can also be tied to the ground
plane.
Decoupling capacitors at each of the supply pins is recommended. The high-frequency decoupling capacitors for
the RF mixers (VCCMIX) should be placed close to their respective pins. The value of the capacitor should be
chosen to provide a low-impedance RF path to ground at the frequency of operation. Typically, this value is
around 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to their
respective pins as possible.
The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCB
layout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Q
output traces should be routed as differential pairs and their lengths all kept equal to each other. Decoupling
capacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines related
to the RF input and the LO input should also be routed as differential lines with their respective lengths kept
equal. If an RF balun is used to convert a single-ended input to a differential input, then the RF balun should be
placed close to the device. Implement the RF balun layout per the manufacturer’s guidelines to provide best gain
and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep the
characteristic impedance of the RF traces at a nominal 50 Ω.
Figure 46. PCB Layout Guidelines
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GNDDIG
VCCDIG
CHIP_EN
VCCMIX1
GND
GND
NC
NC
GND
MIXinp
MIXinn
VCCMIX2
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36 VCCBBI
GND
BBIoutn
BBIoutp
LOip
LOin
GND
BBQoutp
BBQoutn
GND
VCCBBQ
VCCLO
13 14 15 16 17 18 19 20 21 22 23 24
373839
40
4142
43
44
45
46
47
48
GND
GND
NC
MIXQoutn
GND
NC
REXT
VCCBIAS
GNDBIAS
NC
VCM
CLOCK
DATA
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
READBACK
NC
To Microcontroller
To Microcontroller
TRF371125
RFin
30 kW
To ADC I
To ADC Q
LOin
MIXQoutp
TRF371125
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
Application Schematic
The typical application schematic is shown in Figure 47. The RF bypass capacitors and coupling capacitors on
the supply pins should be adjusted to provide the best high-frequency bypass based on the frequency of
operation.
Figure 47. TRF371125 Application Schematic
The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports can
be converted with an RF balun that is centered at the band of interest. Linearity performance of the TRF371125
is dependent on the amplitude and phase balance of the RF balun; hence, care should be taken with the
selection of the balun device and with the RF layout of the device. The recommended RF balun devices are
listed in Table 10.
Table 10. RF Balun Devices
MANUFACTURER PART NUMBER FREQUENCY RANGE UNBALANCE IMPEDANCE BALANCE IMPEDANCE
Murata LDB21897M005C-001 897 MHz ±100 MHz 50 Ω50 Ω
Murata LDB211G8005C-001 1800 MHz ±100 MHz 50 Ω50 Ω
Murata LDB211G9005C-001 1900 MHz ±100 MHz 50 Ω50 Ω
Murata LDB212G4005C-001 2.3 GHz to 2.7 GHz 50 Ω50 Ω
Johanson 3600BL14M050E 3.3 GHz to 3.8 GHz 50 Ω50 Ω
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Product Folder Link(s): TRF371125
0
90
TRF371125
LNA
TRF3761
ADS62P42
14
14
TRF371125
SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
www.ti.com
Application for a High-Performance RF Receiver Signal Chain
The TRF371125 is the centerpiece component in a high performance direct downconversion receiver. The device
is a highly integrated direct downconversion demodulator that requires minimal additional devices to complete
the signal chain. A signal chain block diagram example is shown in Figure 48.
Figure 48. Block Diagram of Direct Downconvert Receiver
The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1- to 2-dB
noise figure (NF) performance. An RF band-pass filter (BPF) is selected at the frequency band of interest to
eliminate unwanted signals and images outside the band from reaching the demodulator. The TRF371125
incorporates the direct downconvert demodulation, baseband filtering, and baseband gain-control functions. An
external synthesizer, such as the TRF3761, is used to provide the local oscillator (LO) source to the TRF371125.
The differential outputs of the TRF3761 directly mate with LO input of the TRF371125. The quadrature outputs
(I/Q) of the TRF371125 directly drive the input to the analog-to-digital converter (ADC). A dual ADC like the
ADS62P42 14-bit 65-MSPS ADC mates perfectly with the differential I/Q output of the TRF371125. The
baseband output pins (pins 27, 28, 33, 34) can be connected directly to the corresponding input pins of typical
ADCs. The positive and negative terminal connections between the TRF371125 and the ADC can be swapped to
facilitate a clean routing layout. The swapped connection can be reversed by flipping the signals in the digital
domain, if desired. In addition, the common-mode output voltage generated by the ADC is fed directly into the
common-mode port (pin 24) to ensure the optimum dynamic range of the ADC is maintained.
EVALUATION TOOLS
An evaluation module is available to test the TRF371125 performance. The TRF371125EVM can be configured
with different baluns to enable operation in various frequency bands. The TRF371125EVM is available for
purchase through the Texas Instruments web site at www.ti.com.
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SLWS219B –JANUARY 2010–REVISED DECEMBER 2010
REVISION HISTORY
Changes from Revision A (March, 2010) to Revision B Page
• Corrected y-axis value in Figure 29 .................................................................................................................................... 27
• Corrected y-axis value in Figure 30 .................................................................................................................................... 27
• Corrected y-axis value in Figure 31 .................................................................................................................................... 27
• Corrected y-axis value in Figure 32 .................................................................................................................................... 27
Changes from Original (January, 2010) to Revision A Page
• Corrected product name discussed throughout document ................................................................................................... 1
• Added Evaluation Tools ...................................................................................................................................................... 42
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): TRF371125
PACKAGE OPTION ADDENDUM
www.ti.com 23-Nov-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TRF371125IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TRF371125IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TRF371125IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
TRF371125IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TRF371125IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
TRF371125IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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