CS4970x4 Data Sheet FEATURES High Definition Audio Decoder DSP Family with Dual 32-bit Engine Technology Multi-standard 32-bit high-definition audio decoding plus post-processing Supports high-definition audio formats including: -- Dolby Digital(R) Plus -- Dolby(R) TrueHD -- DTS-HD(R) High Resolution Audio -- DTS-HD Master AudioTM -- DTS ExpressTM 5.1 Supports legacy audio formats and a wide array of postprocessing -- Dolby Digital(R) EX, Dolby Pro Logic(R) II, IIx, IIz 7.1, Dolby Headphone(R) 2, Dolby Virtual Speaker(R) 2, Dolby Volume(R) (original), Dolby Volume 258 (lite), Audistry(R) -- DTS-ES 96/24TM Discrete 7.1, DTS-ESTM Discrete 7.1, DTS-ESTM Matrix 6.1, DTS Neo:6(R), DTS Neural SurroundTM DTS Surround Sensation Speaker -- MPEG-2 AACTM LC 5.1 -- SRS(R) Circle Surround(R) II, SRS Circle Surround Auto, SRS Circle Surround Decoder Optimized, SRS TruVolumeTM 7.1 (V 2.1.0.0), SRS TruSurround HD/HD4(R), SRS WOW HDTM, SRS CS HeadphoneTM, SRS Circle Cinema 3DTM, SRS Studio Sound HDTM -- THX(R) Ultra2TM, THX Select2TM Cirrus Logic's Applications Library -- Cirrus Original Multi-Channel Surround 2 (COMS2), Cirrus Band XpandeRTM, Cirrus Virtualization Technology (CVT), Cirrus Intelligent Room Calibration 2 (IRC2), Cirrus Bass Enhancement (CBE) -- Crossbar Mixer, Signal Generator -- Advanced Post-Processors including: 7.1 Bass Manager Quadruple Crossover, Tone Control, 11- Band Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4 Upsampler Serial Control 1 Serial Control 2 Up to 12 Channels of 32-bit Serial Audio Input Customer Software Security Keys 16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx Two SPITM/I2CTM ports Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial Flash Memory Support The CS4970x4 DSP family is an enhanced version of the CS4953xx DSP family with higher overall performance. In addition to all the mainstream audio processing codes in onchip ROM that the CS4953xx DSP offers, the CS4970x4 device family also supports the decoding of major high-definition audio formats. Additionally, the CS4970x4, a dual-core device, performs the high-definition audio decoding on the first core, leaving the second core available for audio post-processing and audio enhancement. The CS4970x4 device supports the most demanding audio post processing requirements. It provides an easy upgrade path to systems currently using the CS495xx or CS4953xx device with minor (or no) hardware and software changes. Ordering Information See page 27 for ordering information. Parallel Control GPIO Debug 12 Ch. Audio In / 6 Ch. SACD In STC Coyote 32-bit DSP A S/PDIF S/PDIF P X Y D M A Coyote 32-bit DSP B TMR1 TMR2 P X Y 16 Ch PCM Audio Out Ext. Memory Controller Preliminary Product Information http://www.cirrus.com PLL This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) 2014 Cirrus Logic, Inc. All Rights Reserved FEB 2014 DS752F1 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Table of Contents 1 Documentation Strategy ............................................................................................................4 2 Overview .....................................................................................................................................4 2.1 Migrating from CS495xx(3) to CS4970x4 ................................................................................................. 5 2.2 Licensing .................................................................................................................................................. 5 3 Code Overlays ............................................................................................................................5 4 Hardware Functional Description ............................................................................................6 4.1 Coyote DSP Core ..................................................................................................................................... 6 4.1.1 DSP Memory ...............................................................................................................................6 4.1.2 DMA Controller ............................................................................................................................7 4.2 On-chip DSP Peripherals ......................................................................................................................... 7 4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7 4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7 4.2.3 Serial Control Port 1 & 2 (I2C or SPI) ..........................................................................................7 4.2.4 External Memory Interface ..........................................................................................................7 4.2.5 General Purpose Input/Output (GPIO) ........................................................................................7 4.2.6 Phase-locked Loop (PLL)-based Clock Generator ......................................................................7 4.3 DSP I/O Description ................................................................................................................................. 8 4.3.1 Multiplexed Pins ..........................................................................................................................8 4.3.2 Termination Requirements ...........................................................................................................8 4.3.3 Pads ............................................................................................................................................8 4.4 Application Code Security ........................................................................................................................ 8 5 Characteristics and Specifications ..........................................................................................8 5.1 Absolute Maximum Ratings ...................................................................................................................... 8 5.2 Recommended Operating Conditions ...................................................................................................... 9 5.3 Digital DC Characteristics ........................................................................................................................ 9 5.4 Power Supply Characteristics .................................................................................................................. 9 5.5 Thermal Data (128-pin LQFP) ................................................................................................................ 10 5.6 Switching Characteristics--RESET ......................................................................................................... 11 5.7 Switching Characteristics -- XTI ............................................................................................................ 11 5.8 Switching Characteristics -- Internal Clock ............................................................................................ 12 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode ....................................................... 13 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode ................................................... 14 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode ...................................................... 15 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode .................................................... 16 5.13 Switching Characteristics -- Parallel Control Port - Intel Slave Mode ................................................. 16 5.14 Switching Characteristics -- Parallel Control Port - Motorola Slave Mode ......................................... 19 5.15 Switching Characteristics -- Digital Audio Slave Input Port ................................................................. 21 5.16 Switching Characteristics -- Digital Audio Output Port ........................................................................ 22 5.17 Switching Characteristics -- SDRAM Interface .................................................................................... 23 6 Ordering Information ...............................................................................................................27 7 Environmental, Manufacturing, and Handling Information .................................................27 8 Device Pin-Out Diagram ..........................................................................................................28 8.1 128-Pin LQFP Pin-Out Diagram ............................................................................................................. 28 9 Package Mechanical Drawings ...............................................................................................29 9.1 128-Pin LQFP Package Drawing ........................................................................................................... 29 10 Revision History .....................................................................................................................30 DS752F1 2 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family List of Figures Figure 1. RESET Timing .........................................................................................................................................11 Figure 2. XTI Timing ..............................................................................................................................................11 Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................13 Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................14 Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................15 Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................16 Figure 7. Parallel Control Port - IntelO Slave Mode Read Cycle ...........................................................................17 Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................18 Figure 9. Parallel Control Port - MotorolaO Slave Mode Read Cycle Timing ........................................................20 Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................20 Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................21 Figure 12. DAI Slave Timing Diagram ...................................................................................................................21 Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................22 Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ...........................................23 Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................24 Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................24 Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................25 Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................26 Figure 19. 128-Pin LQFP Pin-Out Diagram ...........................................................................................................28 Figure 20. 128-Pin LQFP Package Drawing ..........................................................................................................29 List of Tables Table 1. CS4970x4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. CS4970x4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DS752F1 3 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 1 Documentation Strategy The CS4970x4 data sheet describes the CS4970x4 family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS4970x4 family of processors. Table 1. CS4970x4 Related Documentation Document Name Description CS4970x4 Data Sheet This document A new consolidated documentation set that includes: CS495314/CS4970x4 System Designer's Guide * Detailed system design information including Typical Connection Diagrams, Boot-Procedures, Pin Descriptions, Etc. Also describes use of DSP Condenser tool. * Detailed firmware design information including signal processing flow diagrams and control API information AN288 - CS4953xx/CS4970x4 Firmware User's Manual Includes detailed firmware design information including signal processing flow diagrams and control API information The scope of the CS4970x4 data sheet is primarily to provide hardware specifications of the CS4970x4 family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. The intended audience for the CS4970x4 data sheet is the system PCB designer, MCU programmer, and the quality control engineer. 2 Overview The CS4970x4 DSP Family, combined with Cirrus Logic's comprehensive library of audio processing algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a broad array of digital interface products and audio converters to meet your audio system-level design requirements. Note: The CS4970x4 is available in a 128-pin LQFP package. The audio processing features of the CS4970x4 product family are a superset of audio features available in the CS4953xx product family. Refer to Table 2 on page 5 for the speed and firmware features of the CS4970x4 product family. DS752F1 4 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Table 2. Device and Firmware Selection Guide Device CS497014 300MACS Decode Processor (DSP-A)1 Matrix Processor Module (DSP-A)1 Stereo PCM (4:1/2:1 Down-sampling and Dolby Pro Logic II / IIx / IIz 7.1 1:2/1:4 U-sampling Options)2 SRS Circle Surround II / Circle Surround Auto / Circle Surround Decoder Optimized (Stereo In) Multichannel PCM (4:1/2:1 Down-sampling and 1:2/1:4 Up-sampling Options)2 Dolby Digital MPEG-2 AAC LC 5.1 Dolby Digital Plus Dolby TrueHD3 Cirrus Original Multi-Channel Surround 2 (Effects / Reverb Processor) Virtualizer Processor Module (DSP-B)1 APP (Advanced Postprocessing) Cirrus Virtualizer Technology Dolby Headphone 2 Dolby Virtual Speaker 2 Crossbar (Down-mix / Up-mix) (Simultaneous Process) Post Processor Module (DSP-B)1 SRS CS Headphone -Tone Control -Select 2 -PEQ (up to 11 Bands) -Delay (Speaker to Listening Position Alignment and/or Lip Sync) -7.1 Bass Manager -Audio Manager -4:1/2:1 Down-sampling2 CS497004 300MACS CS497024 300MACS Same as CS497014 + DTS, DTS-ES, DTS96/24 DTS-HD Master Audio3 DTS-HD High Res Audio3 DTS Express 5.1 SRS TruSurround HD/HD4 Same as CS497014 + DTS Neo:6, DTS Neural Surround SRS TruVolume 7.1 Multichannel Dolby Volume Multichannel 1. Additional processing (MPMA, MPMB/VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic FAE for the latest concurrency matrix. 2. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also available as a separate post-processing module that is described in the application note AN288PPI. 3. The indicated HD audio decoder algorithms require external SDRAM. Consult your Cirrus Logic FAE for the recommended SDRAM size for your design. 2.1 Migrating from CS495xx(3) to CS4970x4 CS4970x4 was designed to provide an easy upgrade path from the CS495xx and CS4953x. There are some small differences the hardware designer should be aware of: * The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx. * The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx. * The CS4970x4 adds support for Time-division multiplexing (TDM) mode on both audio input and output ports. * The CS4970x4 does not support external static random access memory (SRAM) operation. * The CS4970x4 external Synchronous dynamic random access memory (SDRAM) bus speed is fixed at 150 MHz vs. the 120 MHz maximum bus speed for the CS495xx. Some firmware modules also support a 75 MHz CS4970x4 SDRAM bus speed. Refer to AN304 for details. * The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI. 2.2 Licensing Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the application notes. Contact your local Cirrus Sales representative for more information. 3 Code Overlays The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of overlays. The overlays have been divided into three main groups: decoders, matrix processors, and postprocessors. All software components are defined in the following list: DS752F1 5 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family * OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc. * Decoders - Any module that initially writes data into the audio I/O buffers, e.g. AC-3TM, DTS, PCM, etc. All the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc. * Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Postprocessors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are Dolby ProLogic IIx and DTS Neo:6. * Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (n2 channels) with the effect of providing "phantom" speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone 2 and Dolby Virtual Speaker 2. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. * Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded -- only the new decoder (the same is true for the other overlays). 4 Hardware Functional Description 4.1 Coyote DSP Core The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP core, leaving more MIPS available for signal processing instructions. CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to the CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio decoder and post-processor modules which are available from Cirrus Logic. The CS4970x4 is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player, and digital broadcast decoder applications. 4.1.1 DSP Memory Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory for any of today's popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES 96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD master audio. The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words. DS752F1 6 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Table 3. CS4970x4 DSP Memory Sizes Memory Type DSP A DSP B X 16K SRAM, 32K ROM 10K SRAM, 8K ROM Y 24K SRAM, 32K ROM 16K SRAM, 16K ROM P 8K SRAM, 32K ROM 8K SRAM, 24K ROM 4.1.2 DMA Controller The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable. 4.2 On-chip DSP Peripherals 4.2.1 Digital Audio Input Port (DAI) The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally, support is provided for audio data input to the DSP via the DAI from an HDMI receiver. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 Digital Audio Output Port (DAO) There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192-kHz SPDIF transmitter (data with embedded clock on a single line). 4.2.3 Serial Control Port 1 & 2 (I2C or SPI) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. 4.2.4 External Memory Interface The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. 4.2.5 General Purpose Input/Output (GPIO) Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high. 4.2.6 Phase-locked Loop (PLL)-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either DS752F1 7 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3 DSP I/O Description 4.3.1 Multiplexed Pins Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4 System Designer's Guide. 4.3.2 Termination Requirements Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4 System Designer's Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4970x4 System Designer's Guide. 4.3.3 Pads The CS4970x4 I/O operates from the 3.3 V supply and is tolerant within 5 V. 4.4 Application Code Security The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. 5 Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 C, CL = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V. 5.1 Absolute Maximum Ratings (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter Symbol Min Max Unit VDD VDDA VDDIO -0.3 -0.3 -0.3 -- 2.0 3.6 3.6 0.3 V V V V Iin -- +/- 10 mA Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V Input voltage on I/O pins Vinio -0.3 5.0 V Storage temperature Tstg -65 150 C DC power supplies: Input pin current, any pin except supplies Core supply PLL supply I/O supply |VDDA - VDDIO| CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. DS752F1 8 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.2 Recommended Operating Conditions (GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Parameter Core supply PLL supply I/O supply |VDDA - VDDIO| DC power supplies: Symbol VDD VDDA VDDIO Min 1.71 3.13 3.13 Typ 1.8 3.3 3.3 0 Max 1.89 3.46 3.46 Unit V V V V 0 +25 + 70 C +125 C TA Ambient operating temperature Commercial Grade (CQZ/CVZ) Commercial 0 Tj Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply. 5.3 Digital DC Characteristics (Measurements performed under static conditions.) High-level input voltage Low-level input voltage, except XTI Low-level input voltage, XTI Input Hysteresis High-level output voltage (IO = -4mA), except XTI, SDRAM Parameter Symbol VIH VIL VILXTI Vhys VOH Min 2.0 -- -- -- VDDIO * 0.9 Typ -- -- -- 0.4 -- Max -- 0.8 0.6 -- -- Unit V V V V V pins Low-level output voltage (IO = 4mA), except XTI, SDRAM VOL -- -- VDDIO * 0.1 V pins SDRAM High-level output voltage (IO = -8mA) SDRAM Low-level output voltage (IO = 8mA) Input leakage current (all digital pins with internal pull-up VOH VOL IIN VDDIO * 0.9 -- -- -- -- -- -- VDDIO * 0.1 5 V V A resistors disabled) Input leakage current (all digital pins with internal pull-up IIN-PU -- -- 70 A resistors enabled, and XTI) 5.4 Power Supply Characteristics (Measurements performed under operating conditions.) Parameter Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO Min Typ Max Unit -- -- -- 350 3.5 120 -- -- -- mA mA mA 1.Dependent on application firmware and DSP clock speed. DS752F1 9 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.5 Thermal Data (128-pin LQFP) Parameter Symbol Min Typ Max -- -- 53 44 -- -- -- -- .45 .39 -- -- ja Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 Thermal Resistance (Junction to Top of Package) C / Watt jt Two-layer Board1 Four-layer Board2 Unit C / Watt Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers. 3. To calculate the die temperature for a given power dissipation 4. To calculate the case temperature for a given power dissipation j = Ambient Temperature + [ (Power Dissipation in Watts) * ja ] c = j - [ (Power Dissipation in Watts) * jt DS752F1 10 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.6 Switching Characteristics--RESET Parameter Symbol Min Max Unit Trstl 1 -- s All bidirectional pins high-Z after RESET low Trst2z -- 100 ns Configuration pins setup before RESET high Trstsu 50 -- ns Configuration pins hold after RESET high Trsthld 20 -- ns Symbol Min Max Unit External Crystal operating frequency1 Fxtal 12.288 24.576 MHz XTI period Tclki 41 81.4 ns XTI high time Tclkih 16.4 -- ns XTI low time Tclkil 16.4 -- ns CL 10 18 pF ESR -- 50 RESET minimum pulse width low RESET# HS[3:0] All Bidirectional Pins Trst2z Trstsu Trsthld Trstl Figure 1. RESET Timing 5.7 Switching Characteristics -- XTI Parameter External Crystal Load Capacitance (parallel resonant)2 External Crystal Equivalent Series Resistance 1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz. 2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer's recommendation for load capacitor selection. XTI t clkih t clkil Tclki Figure 2. XTI Timing DS752F1 11 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.8 Switching Characteristics -- Internal Clock Parameter Internal DCLK frequency1 Symbol Min Max Unit Fdclk -- - MHz Fxtal 131 -- - 7.63 1/Fxtal CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497014-CVZ CS497014-CVZR CS497024-CVZ CS497024-CVZR Internal DCLK period1 DCLKP CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497014-CVZ CS497014-CVZR CS497024-CVZ CS497024-CVZR ns 1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. DS752F1 12 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.9 Switching Characteristics -- Serial Control Port - SPI Slave Mode Parameter Symbol Min Typical Max Units fspisck -- -- 25 MHz tspicss 24 -- -- ns tspickl 20 -- -- ns tspickh 20 -- -- ns Setup time SCP_MOSI input tspidsu 5 -- -- ns Hold time SCP_MOSI input tspidh 5 -- -- ns tspidov -- -- 11 ns tspiirqh -- -- 20 ns tspiirql 0 -- -- ns SCP_CLK low to SCP_CS rising tspicsh 24 -- -- ns SCP_CS rising to SCP_MISO output high-Z tspicsdz -- 20 -- ns tspicbsyl -- 3*DCLKP+20 -- ns SCP_CLK frequency1,2 SCP_CS falling to SCP_CLK rising 2 SCP_CLK low time2 SCP_CLK high time2 SCP_CLK low to SCP_MISO output valid2 SCP_CLK falling to SCP_IRQ rising2 SCP_CS rising to SCP_IRQ falling2 2 SCP_CLK rising to SCP_BSY falling2 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3. 2. When SCP1 is in SPI slave mode, very slow rise and fall times of the SCP_CLK edges may make the edges of the SCP_CLK more susceptible to noise, resulting in non-smooth edges. Any glitch at the threshold levels of the SCP port input signals could result in abnormal operation of the port. In systems that have noise coupling onto SCP_CLK, slow rise and fall times may cause host communication problems. Increasing rise time makes host communication more reliable. t spicss SCP_CS# tspickl 0 1 2 6 7 0 A0 R/W MSB 5 7 6 tspicsh SCP_CLK fspisck SCP_MOSI tspickh A6 A5 LSB tspidsu t spidh SCP_MISO tspidov t spicsdz MSB LSB tspiirqh tspiirql SCP_IRQ# tspibsyl SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing DS752F1 13 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.10 Switching Characteristics -- Serial Control Port - SPI Master Mode Parameter Symbol Min Typical Max Units fspisck -- -- Fxtal/2 MHz tspicss -- 11*DCLKP + (SCP_CLK PERIOD)/2 -- ns SCP_CLK low time tspickl 16.9 -- -- ns SCP_CLK high time tspickh 16.9 -- -- ns Setup time SCP_MISO input tspidsu 11 -- -- ns Hold time SCP_MISO input tspidh 5 -- -- ns SCP_CLK low to SCP_MOSI output valid tspidov -- -- 11 ns SCP_CLK low to SCP_CS falling tspicsl 7 -- -- ns SCP_CLK low to SCP_CS rising tspicsh -- 11*DCLKP + (SCP_CLK PERIOD)/2 -- ns Bus free time between active SCP_CS tspicsx -- 3*DCLKP -- ns SCP_CLK falling to SCP_MOSI output high-Z tspidz -- -- 20 ns SCP_CLK frequency1, 2 SCP_CS falling to SCP_CLK rising 3 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. See Section 5.7. 3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter. . tspicsx tspicss EE_CS# tspickl tspicsl 1 0 2 6 7 0 A0 R/W MSB 5 6 7 tspicsh SCP_CLK fspisck SCP_MISO tspickh A6 A5 LSB tspidsu tspidh SCP_MOSI tspidov tspidz MSB LSB Figure 4. Serial Control Port - SPI Master Mode Timing DS752F1 14 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.11 Switching Characteristics -- Serial Control Port - I2C Slave Mode Parameter Symbol Min Typical Max Units fiicck -- -- 400 kHz SCP_CLK low time tiicckl 1.25 -- -- s SCP_CLK high time tiicckh 1.25 -- -- s tiicckcmd 1.25 -- -- s START condition to SCP_CLK falling tiicstscl 1.25 -- -- s SCP_CLK falling to STOP condition tiicstp 2.5 -- -- s Bus free time between STOP and START conditions tiicbft 3 -- -- s Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 -- -- ns Hold time SCP_SDA input after SCP_CLK falling2 tiich 0 -- -- ns SCP_CLK low to SCP_SDA out valid tiicdov -- -- 18 ns SCP_CLK falling to SCP_IRQ rising tiicirqh -- -- 3*DCLKP + 40 ns NAK condition to SCP_IRQ low tiicirql -- 3*DCLKP + 20 -- ns SCP_CLK rising to SCB_BSY low tiicbsyl -- 3*DCLKP + 20 -- ns SCP_CLK frequency 1 SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. 2. This parameter is measured from the ViL level at the falling edge of the clock. tiicckcmd tiicckl 0 1 tiicr 6 tiicf 7 8 tiicckcmd 0 1 6 7 8 SCP_CLK tiicstscl SCP_SDA tiicckh A6 tiicdov A0 R/W tiicstp fiicck ACK MSB LSB ACK tiicirqh tiicsu tiicbft tiicirql tiich SCP_IRQ# tiiccbsyl SCP_BSY# Figure 5. Serial Control Port - I2C Slave Mode Timing DS752F1 15 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.12 Switching Characteristics -- Serial Control Port - I2C Master Mode Parameter Symbol Min Max Units fiicck -- 400 kHz SCP_CLK low time tiicckl 1.25 -- s SCP_CLK high time tiicckh 1.25 -- s tiicckcmd 1.25 -- s START condition to SCP_CLK falling tiicstscl 1.25 -- s SCP_CLK falling to STOP condition tiicstp 2.5 -- s Bus free time between STOP and START conditions tiicbft 3 -- s Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 -- ns Hold time SCP_SDA input after SCP_CLK falling2 tiich 0 -- ns tiicdov -- 36 ns SCP_CLK frequency 1 SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition SCP_CLK low to SCP_SDA out valid 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. This parameter is measured from the ViL level at the falling edge of the clock. tiicckcmd tiicckl 0 1 tiicr 6 tiicf 7 8 tiicckcmd 0 1 6 7 8 SCP_CLK tiicstscl SCP_SDA tiicckh A6 tiicsu t iicdov A0 R/W tiicstp fiicck ACK MSB LSB tiicb ACK tiich Figure 6. Serial Control Port - I2C Master Mode Timing 5.13 Switching Characteristics -- Parallel Control Port - Intel Slave Mode Parameter Address setup before PCP_CS and PCP_RD low or PCP_CS and Symbol Min Typical Max Unit tias 5 -- -- ns tiah 5 -- -- ns PCP_WR low Address hold time after PCP_CS and PCP_RD low or PCP_CS and PCP_WR high Read DS752F1 16 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Parameter Symbol Min Delay between PCP_RD then PCP_CS low or PCP_CS then Typical Max Unit ticdr 0 -- -- ns Data valid after PCP_CS and PCP_RD low tidd -- -- 18 ns PCP_CS and PCP_RD low for read tirpw 24 -- -- ns Data hold time after PCP_CS or PCP_RD high tidhr 8 -- -- ns Data high-Z after PCP_CS or PCP_RD high tidis -- -- 18 ns PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next tird 30 -- -- ns tirdtw 30 -- -- ns tirdirqhl -- -- 12 ns ticdw 0 -- -- ns Data setup before PCP_CS or PCP_WR high tidsu 8 -- -- ns PCP_CS and PCP_WR low for write tiwpw 24 -- -- ns Data hold after PCP_CS or PCP_WR high tidhw 8 -- -- ns PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next tiwtrd 30 -- -- ns tiwd 30 -- -- ns tiwrbsyl -- 2*DCLKP + 20 -- ns PCP_RD low read 1 PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next write1 PCP_RD rising to PCP_IRQ rising Write Delay between PCP_WR then PCP_CS low or PCP_CS then PCP_WR low read1 PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next write1 PCP_WR rising to PCP_BSY falling 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer. CS4953x4/CS4970x4 System Designer's Guide should be consulted for the firmware speed limitations. PCP_A[3:0] t iah PCP_D[7:0] LSP t ias t idd PCP_CS# t idhr t icdr PCP_WR# MSP t idis t irpw t ird t irdtw PCP_RD# t irdirqh PCP_IRQ# Figure 7. Parallel Control Port - Intel Slave Mode Read Cycle DS752F1 17 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family PCP_A[3:0] t iah PCP_D[7:0] t ias LSP MSP t idhw PCP_CS# t icdw PCP_RD# t idsu t iwpw t iw d t iwtrd PCP_WR# t iwrbsyl PCP_BSY# Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle DS752F1 18 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.14 Switching Characteristics -- Parallel Control Port - Motorola Slave Mode Symbo l Min Typical Max Unit Address setup before PCP_CS and PCP_DS low tmas 5 -- -- ns Address hold time after PCP_CS and PCP_DS low tmah 5 -- -- ns tmcdr 0 -- -- ns Data valid after PCP_CS and PCP_DS low with PCP_R/W high tmdd -- -- 19 ns PCP_CS and PCP_DS low for read tmrpw 24 -- -- ns Data hold time after PCP_CS or PCP_DS high after read tmdhr 8 -- -- ns Data high-Z after PCP_CS or PCP_DS high after read tmdis -- -- 18 ns PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next tmrd 30 -- -- ns tmrdtw 30 -- -- ns tmrwirqh -- -- 12 ns tmcdw 0 -- -- ns Data setup before PCP_CS or PCP_DS high tmdsu 8 -- -- ns PCP_CS and PCP_DS low for write tmwpw 24 -- -- ns PCP_R/W setup before PCP_CS AND PCP_DS low tmrwsu 24 -- -- ns PCP_R/W hold time after PCP_CS or PCP_DS high tmrwhld 8 -- -- ns Data hold after PCP_CS or PCP_DS high tmdhw 8 -- -- ns PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with tmwtrd 30 -- -- ns tmwd 30 -- -- ns tmrwbsyl -- 2*DCLKP + 20 -- ns Parameter Read Delay between PCP_DS then PCP_CS low or PCP_CS then PCP_DS low read1 PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next write1 PCP_RW rising to PCP_IRQ falling Write Delay between PCP_DS then PCP_CS low or PCP_CS then PCP_DS low 1 PCP_R/W high for next read PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next write1 PCP_RW rising to PCP_BSY falling 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer. CS4953x4/CS4970x4 System Designer's Guide should be consulted for the firmware speed limitations. DS752F1 19 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family PCP_A[3:0] t mas t mah LSP PCP_AD[7:0] MSP t mdhr PCP_CS# t mdd t mrwsu t mcdr t mdis t mrwhld PCP_WR# t mrpw t mrdtw t mrd PCP_DS# t mrwirqh PCP_IRQ# Figure 9. Parallel Control Port - Motorola Slave Mode Read Cycle Timing PCP_A[3:0] t mas PCP_AD[7:0] t mah LSP t mdsu MSP t mdhw PCP_CS# t mcdw t mrwhld t mwpw PCP_WR# t mrwsu t mwd t mwtrd PCP_DS# tmrwirql PCP_IRQ# Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing DS752F1 20 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.15 Switching Characteristics -- Digital Audio Slave Input Port Parameter Symbol Min Max Unit Tdaiclkp 40 -- ns -- 45 55 % DAI_LRCLK transition from DAI_SCLK active edge tdaisstlr 10 -- ns DAI_SCLK active edge from DAI_LRCLK transition tdaislrts 10 -- ns Setup time DAI_DATAn tdaidsu 10 -- ns Hold time DAI_DATAn tdaidh 5 -- ns DAI_SCLK period DAI_SCLK duty cycle Note: In these diagrams, falling edge is the inactive edge of DAI_SCLK. DAI_SCLK t daidsu t daidh DAI_DATAn Figure 11. Digital Audio Input (DAI) Port Timing Diagram Tdaiclkp tdaislrts DAI_LRCLK DAI_LRCLK DAI_SCLK Tdaiclkp DAI_SCLK tdaisstlr DAIn_DATAn DAIn_DATAn Figure 12. DAI Slave Timing Diagram DS752F1 21 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.16 Switching Characteristics -- Digital Audio Output Port Parameter Symbol Min Max Unit Tdaomclk 40 -- ns -- 45 55 % Tdaosclk 40 -- ns -- 40 60 % tdaomsck -- 19 ns DAO_SCLK delay from DAO_LRCLK transition3 tdaomlrts -- 8 ns DAO_LRCLK delay from DAO_SCLK transition3 tdaomstlr -- 8 ns DAO1_DATA[3..0], DAO2_DATA[1..0] tdaomdv -- 10 ns DAO_SCLK active edge to DAO_LRCLK transition tdaosstlr 10 -- ns DAO_LRCLK transition to DAO_SCLK active edge tdaoslrts 10 -- ns DAO_Dx delay from DAO_SCLK inactive edge tdaosdv -- 12.5 ns DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode1 DAO_SCLK duty cycle for Master or Slave mode1 Master Mode (Output A1 Mode)1,2 DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input delay from DAO_SCLK transition3 Slave Mode (Output A0 Mode)4 1. Master mode timing specifications are characterized, not production tested. 2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. 3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid. 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. tdaomlclk tdaomlclk DAO_MCLK DAO_MCLK tdaomsck tdaomsck DAO_SCLK DAO_SCLK tdaomdv tdaomdv DAOn_DATAn DAOn_DATAn tdaomlrts tdaomlrts DAO_LRCLK DAO_LRCLK Note: In these diagrams, falling edge is the inactive edge of DAO_SCLK. Figure 13. Digital Audio Port Output Timing Master Mode DS752F1 22 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family tdaosclk DAO_LRCLK DAO_LRCLK tdaoslrts DAO_SCLK DAO_SCLK tdaosclk tdaosstlr DAO_Dx tdaosdv DAO_Dx Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) 5.17 Switching Characteristics -- SDRAM Interface Refer to Figure 15 through Figure 18. (SD_CLKOUT = SD_CLKIN) Parameter Symbol Min Typical Max Unit SD_CLKIN high time tsdclkh 2.3 -- -- ns SD_CLKIN low time tsdclkl 2.3 -- -- ns SD_CLKOUT rise/fall time tsdclkrf -- -- 1 ns SD_CLKOUT Frequency -- -- 150 -- MHz SD_CLKOUT duty cycle -- 45 -- 55 % SD_CLKOUT rising edge to signal valid tsdcmdv -- -- 3.8 ns Signal hold from SD_CLKOUT rising edge tsdcmdh -- 1.1 -- ns SD_CLKOUT rising edge to SD_DQMn valid tsddqv -- 3.8 -- ns SD_DQMn hold from SD_CLKOUT rising edge tsddqh 1.38 -- -- ns SD_DATA valid setup to SD_CLKIN rising edge tsddsu 1.3 -- -- ns SD_DATA valid hold to SD_CLKIN rising edge tsddh 2.1 -- -- ns SD_CLKOUT rising edge to ADDRn valid tsdav -- 3.8 -- ns DS752F1 23 DS752F1 SD_CLKOUT tsdcmdv tsdclkrf tsdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# tsddqh tsddqv SD_DQMn 11 00 SD_An tsdav CAS=2 tsddsu SD_Dn tsddh LSP0 LSP1 MSP0 MSP1 LSP2 MSP2 LSP3 MSP3 SD_CLKIN tsdclkl tsdclkh Figure 15. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT tsdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# LSP0 SD_Dn MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 tsdav SD_An SD_DQMn 00 tsddqv 11 tsddqh Figure 16. External Memory Interface - SDRAM Burst Write Cycle MSP3 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family tsdcmdv 24 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family SD_CLKOUT tsdcmdv tsdcmdv tsdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# SD_DQMn SD_An SD_Dn Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle DS752F1 25 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family SD_CLKOUT tsdcmdv tsdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# SD_DQMn SD_An OPCODE SD_Dn Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle DS752F1 26 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 6 Ordering Information The CS4970x4 family part number is described as follows: CS497NNI-XYZ where NN - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free Table 4. Ordering Information Part No. Status Grade Temp. Range Package CS497014-CVZ Active Commercial 0 to +70 C 128-pin LQFP CS47014-CVZR1 Active Commercial 0 to +70 C CS497024-CVZ Active Commercial 0 to +70 C Active Commercial 0 to +70 C CS497024-CVZR 1 128-pin LQFP 1. R = Tape and reel Note: Please contact the factory for availability of the -D (automotive grade) package. 7 Environmental, Manufacturing, and Handling Information Table 5. Environmental, Manufacturing, & Handling Information Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS497014-CVZ 260 C 3 7 Days CS47014-CVZR 260 C 3 7 Days CS497024-CVZ 260 C 3 7 Days CS497024-CVZR 260 C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS752F1 27 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 8 Device Pin-Out Diagram GPIO38, PCP_WR# / DS#, SCP2_CLK SD_A10, EXT_A10 SD_BA0, EXT_A13 SD_BA1, EXT_A14 105 GNDIO5 SD_WE# SD_CAS# SD_RAS# EXT_A15 110 SD_CS# VDD5 EXT_A16 EXT_A17 EXT_A18 115 GND5 EXT_A19 EXT_OE# EXT_CS1# RESET# 120 VDDIO6 GNDIO6 GPIO33, SCP1_MOSI GPIO34, SCP1__MISO / SDA GPIO35, SCP1_CLK 125 VDD6 GND6 GPIO37, SCP1_BSY#, PCP_BSY# 8.1 128-Pin LQFP Pin-Out Diagram SD_A0, EXT_A0 1 GPIO11, PCP_A3, AS#, SCP2_MISO / SDA SD_A1, EXT_A1 100 VDDIO5 GPIO10, PCP_A2 / A10, SCP2_MOSI SD_A2, EXT_A2 GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GND4 5 SD_A3, EXT_A3 GPIO7, SCP1_CS#, IOWAIT SD_A4, EXT_A4 GPIO6, PCP_CS#, SCP2_CS# 95 VDD4 VDDIO7 EXT_CS2# GNDIO7 SD_A5, EXT_A5 GPIO3, DDAC 10 GNDIO4 GPIO2 VDD7 SD_A6, EXT_A6 GPIO1 90 SD_A7, EXT_A7 VDDIO4 GPIO0, EE_CS# SD_A8, EXT_A8 GND7 15 SD_A9, EXT_A9 XTAL_OUT GND3 XTI 85 SD_A11, EXT_A11 XTO GNDA SD_A12, EXT_A12 CS497xx4 PLL_REF_RES 20 VDD3 SD_CLKEN 128-Pin LQFP VDDA (3.3V) SD_CLKIN VDD8 80 SD_CLKOUT GPIO14, DAI1_DATA3, TM3, DSD3 SD_DQM1 GPIO13, DAI1_DATA2, TM2, DSD2 SD_D8, EXT_D8 GND8 25 SD_D9, EXT_D9 GPIO12, DAI1_DATA1, TM1, DSD1 GNDIO3 DAI1_DATA0, TM0, DSD0 75 SD_D10, EXT_D10 VDDIO8 SD_D11, EXT_D11 DAI1_SCLK, DSD_CLK VDDIO3 DAI1_LRCLK, DSD4 30 SD_D12, EXT_D12 GNDIO8 SD_D13, EXT_D13 GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY# 70 SD_D14, EXT_D14 GPIO43, BDI_CLK, DAI2_SCLK SD_D15, EXT_D15 BDI_DATA, DAI2_DATA, DSD5 SD_D0, EXT_D0 GPIO26, DAO2_DATA3 / XMTB 35 GNDIO2 DBDA EXT_WE# DBCK 65 SD_D1, EXT_D1 SD_D2, EXT_D2 SD_D3, EXT_D3 VDDIO2 SD_D4, EXT_D4 SD_D5, EXT_D5 60 SD_D6, EXT_D6 SD_D7, EXT_D7 SD_DQM0 GND2 VDD2 55 GNDIO1 DAO1_LRCLK DAO1_SCLK DAO1_DATA0, HS0 VDDIO1 50 GPIO15, DAO1_DATA1, HS1 GPIO16, DAO1_DATA2, HS2 GND1 45 GPIO23, DAO2_LRCLK GPIO17, DAO1_DATA3 / XMTA GPIO22, DAO2_SCLK GPIO18, DAO2_DATA0, HS3 VDD1 TEST DAO_MCLK 40 GPIO19, DAO2_DATA1, HS4 GPIO20, DAO2_DATA2 Figure 19. 128-Pin LQFP Pin-Out Diagram DS752F1 28 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 9 Package Mechanical Drawings 9.1 128-Pin LQFP Package Drawing D D1 E E1 1 e b A A1 L Figure 20. 128-Pin LQFP Package Drawing Table 6. 128-Pin LQFP Package Characteristics MILLIMETERS INCHES DIM MIN A A1 b D D1 E E1 e q L L1 -- 0.05 0.17 0 0.45 NOM -- -- 0.22 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 3.5 0.60 1.00 REF MAX MIN NOM MAX 1.60 0.15 0.27 -- .002" .007" .063" .006" .011" 7 0.75 0 .018" -- -- .009" .866" .787" .630" .551" .020" 3.5 .024" .039" REF 7 .030" TOLERANCES OF FORM AND POSITION ddd DS752F1 0.08 .003" 29 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 10 Revision History Revision Date PP9 November, 2010 Changes Added "Status" column and footnote 1 to Table 4. Added Tj conditions to Section 5.2. Changed 500 ma to 350 ma in Section 5.4. PP10 March, 2011 Updated Section 5.15 "Switching Characteristics -- Digital Audio Slave Input Port" on page 21. Updated Section 5.16 "Switching Characteristics -- Digital Audio Output Port" on page 22. PP11 February, 2012 Added max internal DCLK frequency and min internal DCLK period to Section 5.8. Added notes to Section 5.9. Updated tspickl and tspickh values in Section 5.10. Updated tdaosdv max value in Section 5.16. PP12 October, 2013 Updated note in Section 2 overview. Minor change to Section 2.1 title. F1 February, 2014 Updated note in Section 2 overview regarding CS4970x4. Changed status of CS497024-CVZ and CS497024-CVZR to "Active" in Table 4. DS752F1 30 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. 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Cirrus Logic, Cirrus, Cirrus Logic logo designs, Cirrus Framework, and DSP Condenser are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. THX is a registered trademark of THX, Ltd. THX Select 2 and THX Ultra 2 are trademarks of THX, Ltd. Dolby, Dolby Digital, Dolby Headphone, Virtual Speaker, Pro Logic, Audistry, and Dolby Volume are registered trademarks of Dolby Laboratories, Inc. AAC, AC-3, Dolby TrueHD, and Dolby Volume 258 are trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or readyto-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. DTS and DTS Neo:6 are registered trademarks of the Digital Theater Systems, Inc. DTS-ES 96/24, DTS-ES, DTS 6.1, DTS 96/24, DTS Neural Surround, and DTS Express are trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD are either trademarks or registered trademarks of SRS Labs, Inc. SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are incorporated under license from SRS Labs, Inc. SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies incorporated in the Cirrus Logic CS4953xx products are owned by SRS Labs, a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of Cirrus Logic CS4953xx products must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS4953xx products must be sent to SRS Labs for review. SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone 360, SRS HPF, SRS Studio-Sound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are protected under US and foreign patents issued and/or pending. Neither the purchase of the Cirrus Logic CS4953xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual. Motorola is a registered trademark of Motorola, Inc. SPI is a trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Semiconductor. DS752F1 31 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic: CS497024-DVZ CS497024-DVZR