April 2004
Copyright © Alliance Semiconductor. All rights reserved.
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 1 of 9
3.3V 32K X 8 CMOS SRAM (Common I/O)
®
Features
• Pin compatible with AS7C3256
• Industrial and commercial temperature options
• Organization: 32,768 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Very low power consumption: ACTIVE
- 180mW max @ 10 ns
• Very low power consumption: STANDBY
- 7.2 mW max CMOS I/O
• Easy memory expansion with
CE
and
OE
inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
-8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
A
9
A
8
256 X 128 X 8
Array
(262,144)
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A
10
A
11
A
12
A
13
A
14
I/O0
I/O7
VCC
GND
OE
CE
WE
Column decoder
Row decoder
Control
circuit
Sense amp
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3 A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C3256A
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C3256A
16
15
28-pin TSOP 1 (8×13.4 mm) 28-pin SOJ (300 mil)
Selection guide
-10 -12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 50 45 40 35 mA
Maximum CMOS standby current 2 2 2 2 mA
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C3256A is a 3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device
organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage,
including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques
permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when
CE
is high. CMOS standby mode consumes 7.2 mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns
are ideal for high-performance applications. The chip enable (
CE
) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (
CE
) and write enable (
WE
) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting chip enable (
CE
) and output enable (
OE
) LOW, with write enable (
WE
) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 3.3 ±0.3V supply. The AS7C3256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.5 +5.0 V
Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 oC
Ambient temperature with VCC applied Tbias –55 +125 oC
DC current into outputs (low) IOUT –20mA
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHLD
OUT Read (ICC)
LLXD
IN Write (ICC)
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 3 of 9
®
Recommended operating conditions
* VIL min = –1.0V for pulse width less than 5ns.
** VIH max = VCC + 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
Parameter Symbol Min Typical Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH** 2.0 – VCC+0.5 V
VIL*-0.5 – 0.8 V
Ambient operating temperature commercial TA0–70
oC
industrial TA–40 – 85 oC
Parameter Sym Test conditions
-10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max
Input leakage
current |ILI|VCC = Max,
Vin = GND to VCC
–1–1–1–1µA
Output leakage
current |ILO|VCC = Max,
VOUT = GND to VCC
–1–1–1–1µA
Operating
power supply
current
ICC
VCC = Max, CE ≤ VIL
f = fMax, IOUT = 0mA –50–45–40–35mA
Standby power
supply current
ISB
VCC = Max, CE > VIH
f = fMax
–20–20–20–20mA
ISB1
VCC = Max, CE > VCC–0.2V
VIN < 0.2V or
VIN > VCC–0.2V, f = 0
–2.0–2.0–2.0–2.0mA
Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
Vin = 0V 5 pF
I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 4 of 9
Read cycle (over the operating range)3,9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE controlled)3,6,8,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10–12–15–20–ns
Address access time tAA – 10 – 12 – 15 – 20 ns 3
Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3
Output enable (OE) access time tOE –5–6–7–8ns
Output hold from address change tOH 3–3–3–3–ns5
CE LOW to output in low Z tCLZ 3–3–3–3–ns4, 5
CE HIGH to output in high Z tCHZ –3–3–4–5ns4, 5
OE LOW to output in low Z tOLZ 0–0–0–0–ns4, 5
OE HIGH to output in high Z tOHZ –3–3–4–5ns4, 5
Power up time tPU 0–0–0–0–ns4, 5
Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5
Undefined output/don’t careFalling inputRising input
Address
D
out
Data valid
t
OH
tAA
t
RC
Supply
current
CE
OE
D
out
t
RC1
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 5 of 9
®
Write cycle (over the operating range)11
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10–12–15–20–ns
Chip enable to write end tCW 8 – 8 –10–12–ns
Address setup to write end tAW 8 – 8 –10–12–ns
Address setup time tAS 0–0–0–0–ns
Write pulse width tWP 7–8–9–12–ns
Write recovery time tWR 0–0–0–0–ns
Address hold from end of write tAH 0–0–0–0–ns
Data valid to write end tDW 5–6–8–10–ns
Data hold time tDH 0–0–0–0–ns4, 5
Write enable to output in high Z tWZ –5–6–7–8ns4, 5
Output active from write end tOW 3–3–3–3–ns4, 5
t
AW
t
AH
t
WC
Address
WE
D
in
D
out
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
t
WR
t
AW
Address
CE
WE
D
in
D
out
Data valid
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
t
WR
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 6 of 9
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B.
4 These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6
WE
is High for read cycle.
7
CE
and
OE
are Low for read cycle.
8 Address valid prior to or coincident with
CE
transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
350
Ω
C
13
320
Ω
D
out
GND
+3.3V
168
Ω
D
out
+1.72V
Figure B: Output load
Thevenin equivalent
- Output
l
oa
d
: see F
i
gure B
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 7 of 9
®
Package diagrams
28-pin SOJ
Min Max
in inches
A0.128 0.148
A1 0.026 -
A2 0.095 0.105
B0.026 0.032
b0.016 0.020
c0.007 0.010
D0.720 0.730
E0.255 0.275
E1 0.295 0.305
E2 0.330 0.340
e0.050 BSC
28-pin TSOP1
8×13.4 mm
Min Max
A1.00 1.20
A1 0.05 0.15
A2 0.91 1.05
b0.17 0.27
c0.10 0.20
D11.70 11.90
e0.55 nominal
E7.90 8.10
Hd 13.20 13.60
L0.50 0.70
α0° 5°
eD
E1
Pin 1
b
B
A1
A2
c
E
Seating
Plane
E2
A
e
b
E
Hd
D
c
LA1AA2
α
28-pin SOJ
28-pin TSOP1
®
AS7C3256A
4/23/04; v.2.0 Alliance Semiconductor P. 8 of 9
Ordering information
Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C3256A-10JIN)
Part numbering system
Package / Access time Temperature 10 ns 12 ns 15 ns 20 ns
Plastic SOJ, 300 mil Commercial AS7C3256A-10JC AS7C3256A-12JC AS7C3256A-15JC AS7C3256A-20JC
Industrial AS7C3256A-10JI AS7C3256A-12JI AS7C3256A-15JI AS7C3256A-20JI
TSOP 8x13.4mm Commercial AS7C3256A-10TC AS7C3256A-12TC AS7C3256A-15TC AS7C3256A-20TC
Industrial AS7C3256A-10TI AS7C3256A-12TI AS7C3256A-15TI AS7C3256A-20TI
AS7C 3 256A –XX XC or I X
SRAM prefix
Voltage:
3 = 3.3V supply Device number Access time
Packages:
J = SOJ 300 mil
T = TSOP 8x13.4mm
Temperature range:
C = 0 oC to 70 0C
I = -40C to 85C
N= Lead Free Part
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C3256A
Document Version: v.2.0
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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AS7C3256A
®
®