ABCU-57xxxxZ Family
10/100/1000BASE-T 1.25 GBd Small Form Pluggable
Low Voltage (3.3 V) Electrical Transceiver over Category 5 Cable
Data Sheet
Description
The ABCU-57xxxxZ family of electrical transceivers from
Avago Technologies oer full-duplex throughput of 1000
Mbps by transporting data over shielded and unshielded
twisted pair category 5 cable with 5-level PAM (Pulse
Amplitude Modulation) signals.
The Avago Technologies 1000BASE-T module takes sig-
nals from both the twisted pair category 5 cable and the
SerDes interface. Pin count overhead between the MAC
and the PHY is minimized, and Gigabit Ethernet opera-
tion is achieved with maximum space savings.
Product Ordering Information
ABCU-5730RZ -5~70 RX_LOS enabled
ABCU-5740RZ -5~70 RX_LOS disabled
ABCU-5730GZ -5~70 RX_LOS enabled & Isolated
ground
ABCU-5730ARZ -40~85 RX_LOS enabled
ABCU-5740ARZ -40~85 RX_LOS disabled
ABCU- 5740AGZ -40~85 RX_LOS disabled
& Isolated ground
ABCU-5731ARZ -40~85 SGMII RX_LOS enabled
ABCU-5741ARZ -40~85 SGMII RX_LOS disabled
ABCU-5741AGZ -40~85 SGMII RX_LOS disabled &
Isolated ground
ABCU-5731RZ -5~70 SGMII RX_LOS enabled
ABCU-5741RZ -5~70 SGMII RX_LOS disabled
Related Products
AFBR-5710Z Family of 850nm +3.3V SFP optical
transceivers for Gigabit Ethernet
AFCT-5710Z Family of 1310nm +3.3V SFP optical
transceivers for Gigabit Ethernet
Features
• RoHS-6 Compliant (see Table 1)
• Designed for Industry-Standard, Small Form Factor
Pluggable (SFP) Ports
• Compliance with IEEE 802.3:2005
• Custom RJ-45 connector with integrated magnetics
• Link lengths at 1.25 Gbd: up to 100 m per IEEE802.3
• Low power, high performance 1.25 Gbd SerDes inte-
grated in module
• Single +3.3 V power supply operation
• Auto-negotiation per IEEE 802.3:2005 Clause 28
(Twisted Pair) and Clause 37 (1000BASE-X)
• Compatible to both shielded and unshielded twisted
pair category 5 cable
• Available in Commercial Temperature (-5~70 °C) and
Industrial Temperature (-40~85 °C)
• 10/100/1000BASE-T operation available with SGMII
host systems.
Applications
• Switch to switch interface
• Switched backplane applications
• File server interface
Module Diagrams
Figure 1 illustrates the major functional components
of the ABCU-57xxxxZ family of transceivers. The 20-pin
connection diagram of module printed circuit board of
the module is shown in Figure 2. Figure 3 depicts the pin
assignment of the MDI (RJ45 jack).
Figure 6 depicts the external conguration and dimen-
sions of the module.
2
Figure 3. MDI ( RJ 45 Jack) Pin Assignment
Magnetics RJ45
Adapter
EEPROM
SerDes/
DSP
TX_DATA
RX_DATA
TX_DISABLE
RX_LOS
MOD_DEF2
MOD_DEF1
MOD_DEF0
100
100
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
V
EE
T
TD-
TD+
V
EE
T
V
CC
T
V
CC
R
V
EE
R
RD+
RD-
V
EE
R
V
EE
T
TX_FAULT
TX_DISABLE
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
Rate Select
LOS
V
EE
R
V
EE
R
Top of Board Bottom of Board
(as viewed thru top of board)
PIN 1 PIN 8
Note: LOS is only applicable for ABCU-573xxxZ models
Figure 2. 20-pin Connection Diagram of Module Printed Circuit Board
Serial Identication (EEPROM)
The ABCU-57xxxxZ family complies with an industry stan-
dard MultiSource Agreement that denes the serial identi-
cation protocol. This protocol uses the 2-wire serial CMOS
EEPROM protocol of the ATMEL AT24C01A or equivalent.
The contents of the ABCU-57xxxxZ family serial ID memory
are dened in Table 10 as specied in the SFP MSA.
Controller and Data I/O
Data I/Os are designed to accept industry standard dif-
ferential signals. In order to reduce the number of passive
components required on the customer’s board, Avago
Technologies has included the functionality of the trans-
mitter bias resistors and coupling capacitors within the
module. The transceiver is compatible with an “ac-coupled”
conguration and is internally terminated. Figure 1 depicts
the functional diagram of the ABCU-57xxxxZ family of
transceivers. 100-ohm resistor shown at RX_LOS in Figure
1 refers to ABCU-573xxxZ conguration.
Caution should be taken into account for the proper inter-
connection between the supporting Physical Layer integrat-
ed circuits and the ABCU-57xxxxZ family of transceivers.
Figure 4 illustrates the recommended interface circuit.
Several control data signals and timing diagrams are imple-
mented in the module and are depicted in Figure 6.
Installation
The ABCU-57xxxxZ family can be installed in or removed
from any MultiSource Agreement (MSA) compliant Small
Form Pluggable port whether the host equipment is
operating or not. The module is simply inserted, small
end rst, under nger-pressure. Controlled hot-plugging
is ensured by design and by 3-stage pin sequencing at
the electrical interface to the host board. The module
housing makes initial contact with the host board EMI
shield, mitigating potential damage due to ElectroStatic
Discharge (ESD). The module pins sequentially contact
the (1) Ground, (2) Power, and (3) Signal pins of the host
board surface mount connector. This printed circuit board
card-edge connector is depicted in Figure 2.
Figure 1. Transceiver Functional Diagram
3
PROTOCOL IC
SerDes
V_SUPPLY
TX[0:9]
RX[0:9]
10 uF 0.1 uF
1 uH
1 uH
0.1 uF
10 uF 0.1 uF
VCC_T
VCC_R
4.7 K
TX_DISABLE
TX_FAULT
TD+
TD-
RD+
RD-
100
RX_LOS
REF CLK
V_SUPPLY
MOD_DEF 1
MOD_DEF 2
MOD_DEF 0
4.7 K 4.7 K 4.7 K 4.7 K
0.01 uF
ABCU-57xxxxZ
EEPROM
RJ45 JACK &
MAGNETICS
CAT5
CABLE
0.01 uF
0.01 uF
0.01 uF
PHY
IC
100
100
*100
100
100
Figure 4. Typical Application Conguration for ABCU-57xxxxZ
VCC T
0.1 µF
0.1 µF 10 µF
1 µH
1 µH
0.1 µF 10 µF
3.3 V
SFP MODULE
VCC R
HOST BOARD
Note: Inductors must have less than 1ohm series resistance per MSA
Figure 5. MSA Recommended Power Supply Filter
* All models that have LOS disabled, will ground
the LOS pin through a 100 ohm internal resistor.
4
Table 1. Regulatory Compliance
Feature Test Method Performance
Electrostatic Discharge
(ESD) to the Electrical
Pins
MIL-STD-883C Method 3015.4
JEDEC/EIA JES022-A114-A
Class 2 (2000 Volts)
Electrostatic Discharge
(ESD) to the RJ 45
Connector Receptacle
Variation of IEC 61000-4-2 Typically withstand 15 KV ( Air Discharge), 8 KV
(Contact) without damage when the RJ 45 connector
receptacle is contacted by a Human Body Model probe.
Electromagnetic
Interference (EMI)
FCC Part 15 Class B
CENELEC EN55022 Class B
(CISPR 22A)VCCI Class 1
System margins are dependent on customer board and
chassis design.
Radiated Immunity Variation of IEC 61000-4-3 Typically shows a negligible eect from a 10 V/m eld
swept from 80 to 1000 MHz applied to the transceiver
without a chassis enclosure.
Component
Recognition
Underwriters Laboratories and Canadian
Standards Association Joint Component
Recognition for Information Technology
Equipment Including Electrical Business
Equipment
UL File # E173874
Grounding
Conguration
DC short between signal and chassis
grounds
- Meets all regulatory requirements as listed above.
- Compliant with system boards using multi-point
grounding scheme
ROHS Compliance Chemical composition analysis Less than 0.1% lead, mercury, hexavalent chromium,
polybrominated biphenyls, and polybrominated
biphenyl ethers by weight of homogeneous material.
Exemption for lead in high melting temperature solder
applied to module connector. Less than 0.01% cadmium
by weight of homogeneous material.
Application Support
Evaluation Kit
To help you in your preliminary transceiver evaluation,
Avago Technologies oers a 1.25 GBd Gigabit Ethernet
evaluation board. This board will allow testing of the
electrical parameters of transceiver. Please contact your
local Field Sales representative for availability and order-
ing details.
Regulatory Compliance
See Table 1 for transceiver Regulatory Compliance perfor-
mance. The overall equipment design will determine the
certication level. The transceiver performance is oered
as a gure of merit to assist the designer.
Immunity
Equipment hosting the ABCU-57xxxxZ modules will be
subjected to radio-frequency electromagnetic elds in
some environments. The transceivers have excellent im-
munity to such elds due to their shielded design.
Electrostatic Discharge (ESD)
There are two conditions in which immunity to ESD dam-
age is important. Table 1 documents our immunity to
both of these conditions. The rst condition is during han-
dling of the transceiver prior to insertion into the trans-
ceiver port. To protect the transceiver, it is important to
use normal ESD handling precautions. These precautions
include using grounded wrist straps, work benches, and
oor mats in ESD controlled areas. The ESD sensitivity of
the ABCU-57xxxxZ is compatible with typical industry
production environments.
The second condition is static discharges to the exterior
of the host equipment chassis after installation. To the
extent that the RJ45 connector interface is exposed to the
outside of the host equipment chassis, it may be subject
to system-level ESD requirements. The ESD performance
of the ABCU-57xxxxZ exceeds typical industry standards.
5
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high-speed trans-
ceivers from Avago Technologies will be required to meet
the requirements of FCC in the United States, CENELEC
EN55022 (CISPR 22A) in Europe and VCCI in Japan.
The metal housing and shielded design minimize the
EMI challenge facing the host equipment designer. These
transceivers provide superior EMI performance. This
greatly assists the designer in the management of the
overall system EMI performance.
Flammability
The ABCU-57xxxxZ electrical transceiver housing is
made of metal and high strength, heat resistant, chemi-
cally resistant, and UL 94V-0 ame retardant plastic.
Caution
There are no user serviceable parts nor any maintenance
required for the ABCU-57xxxxZ. Tampering with or
modifying the performance will result in voided product
warranty. It may also result in improper operation of the
ABCU-57xxxxZ circuitry, and possible overstress of the
RJ 45 connector. Device degradation or product failure
may result. Connecting the module to a non-approved
1000BaseT module, operating above the recommended
absolute maximum conditions or operating the ABCU-
57xxxxZ in a manner inconsistent with its design and
function may result in hazardous radiation exposure and
may be considered an act of modifying or manufacturing
an electrical module product.
Ordering Information
Please contact your local eld sales engineer or one of
Avago Technologies franchised distributors for ordering
information. For technical information, please visit Avago
Technologies web page at www.avagotech.com or con-
tact Avago Technologies Customer Response Center. For
information related to the MSA visit www.schelto.com/
SFP/index.html
Customer Manufacturing Processes
This module is pluggable and is not designed for aqueous
wash, IR reow or wave soldering processes.
6
Table 2. 20-pin Connection Diagram Description
Pin Name Function/Description MSA Notes
1 VEET Transmitter Ground
2 TX Fault Transmitter Fault Indication - High Indicates a Fault Note 1
3 TX Disable Transmitter Disable - Module disables on high or open Note 2
4 MOD-DEF2 Module Denition 2 - Two wire serial ID interface Note 3
5 MOD-DEF1 Module Denition 1 - Two wire serial ID interface Note 3
6 MOD-DEF0 Module Denition 0 - Grounded in module Note 3
7 Rate Select Not Connected
8LOS Loss of Signal - High Indicates Loss of Signal Note 4
9 VEER Receiver Ground
10 VEER Receiver Ground
11 VEER Receiver Ground
12 RD- Inverse Received Data Out Note 5
13 RD+ Received Data Out Note 5
14 VEER Receiver Ground
15 VCCR Receiver Power - 3.3 V +/- 5% Note 6
16 VCCT Transmitter Power - 3.3 V +/- 5% Note 6
17 VEET Transmitter Ground
18 TD+ Transmitter Data In Note 7
19 TD- Inverse Transmitter Data In Note 7
20 VEET Transmitter Ground
Notes:
1. TX Fault is not used and is always tied to ground through a 100 ohm resistor.
2. TX Disable as described in the MSA is not applicable to the 1000BASE-T module, but is used for convenience as an input to reset the internal
ASIC. This pin is pulled up within the module with a 4.7 KW resistor.
Low (0 – 0.8 V): Transceiver on
Between (0.8 V and 2.0 V): Undened
High (2.0 – 3.465 V): Transceiver in reset state
Open: Transceiver in reset state
3. Mod-Def 0,1,2. These are the module denition pins. They should be pulled up with a 4.7-10 KW resistor on the host board to a supply less than
VCCT + 0.3 V or VCCR + 0.3 V.
Mod Def 0 is tied to ground through a 100 ohm resistor to indicate that the module is present.
Mod-Def 1 is clock line of two wire serial interface for optional serial ID
Mod-Def 2 is data line of two wire serial interface for optional serial ID
4. LOS (Loss of Signal) operation on the 1000BaseT SFP is dierent than for optical SFP applications. For models with RX_LOS enabled, RX_LOS
signal is a 1000BASE-T linkup/link-down indicator and not a peak (AC) or voltage (DC) detector. For models where RX_LOS is disabled, RX_LOS
is not used and is always tied to ground via 100-ohm resistor.
5. RD-/+: These are the dierential receiver outputs. They are ac coupled 100 W dierential lines which should be terminated with 100 W dierential
at the user SerDes. The ac coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines
will be between 370 and 2000 mV dierential (185 – 1000 mV single ended) when properly terminated. These levels are compatible with CML
and LVPECL voltage swings.
6. VCCR and VCCT are the receiver and transmitter power supplies. They are dened as 3.3 V ± 5% at the SFP connector pin. The maximum supply
current is 317 mA and the associated in-rush current will typically be no more than 30 mA above steady state after 500 nanoseconds.
7. TD-/+: These are the dierential transmitter inputs. They are ac coupled dierential lines with 100 W dierential termination inside the module.
The ac coupling is done inside the module and is thus not required on the host board. The inputs will accept dierential swings of 500 – 2400
mV (250 – 1200 mV single ended), though it is recommended that values between 500 and 1200 mV dierential (250 – 600 mV single ended)
be used for best EMI performance. These levels are compatible with CML and LVPECL voltage swings.
7
Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Unit Notes
Storage Temperature TS-40 +85 °C Note 1
Case Temperature TC-40 +85 °C Note 1 ,2
Relative Humidity RH 5 95 % Note 1
Module Supply Voltage VCCT,R -0.5 3.6 V Note 1, 2
Data/Control Input Voltage VI-0.5 VCC V Note 1
Sense Output Current - MOD-DEF2 5.0 mA
Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Unit Notes
Case Temperature TC-5
-40
70
85
°C
°C
Note 3
Module Supply Voltage VCCT,R 3.135 3.3 3.465 V Note 3
Data Rate 1.25 Gb/s Note 3
Transceiver Electrical Characteristics
(TC = -5 °C to +70 °C, VCCT,R = 3.3 V ± 5%) (Tc = -40 °C to +85°C, VccT,R = 3.3 V +/- 5%)
Parameter Symbol Minimum Typical Maximum Unit Notes
AC Electrical Characteristics
Power Supply Noise Rejection
(peak-peak)
PSNR 100 mV Note 4
DC Electrical Characteristics
Module supply current
(TC = -5 °C to +70 °C, VCCT,R = 3.3 V ± 5%)
(Tc = -40 °C to +85°C, VccT,R = 3.3 V +/- 5%)
ICC 350
370
mA
Power Dissipation
(TC = -5 °C to +70 °C, VCCT,R = 3.3 V ± 5%)
(Tc = -40 °C to +85°C, VccT,R = 3.3 V +/- 5%)
PDISS 1100
1150
mW
Sense Outputs:
MOD-DEF2
RX_LOS
VOH 2.0 VCCT, R+ 0.3 V Note 5
VOL 0 0.4
Control Inputs:
Transmitter Disable(TX_DISABLE),
MOD-DEF1, 2
VIH 2.0 VCC V Note 5
VIL 0 0.8 V
Notes:
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short
period of time. See Reliability Data Sheet for specic reliability performance.
2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability
is not implied, and damage to the device may occur over an extended period of time.
3. Operating conditions will vary, depending on model. Recommended Operating Conditions are those values outside of which functional perfor-
mance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time. See Reliability
Data Sheet for specic reliability performance later when it is ready.
4. MSA-specied lter is required on the host board to achieve PSNR performance over the frequency range 10 Hz to 2 MHz.
5. LVTTL, external 4.7-10 KW pull-Up resistor required for MOD-DEF 1 and MOD-DEF 2.
8
Transmitter and Receiver Electrical Characteristics
(TC = -5 °C to +70 °C, VCCT,R = 3.3 V ± 5%) (Tc = -40 °C to +85°C, VccT,R = 3.3 V +/- 5%)
Parameter Symbol Minimum Typical Maximum Unit Notes
Data Input:
Transmitter Dierential
Input Voltage (TD +/-)
VI500
2400 mV Note 1
Data Output:
Receiver Dierential
Output Voltage (RD +/-)
VO370 735 2000 mV Note 2
Receive Data Rise & Fall Times
(Receiver)
Trf 100 250 ps Note 3
Transceiver Timing Characteristics
(TC = -5 °C to +70 °C, VCCT,R = 3.3 V ± 5%) (Tc = -40 °C to +85°C, VccT,R = 3.3 V +/- 5%)
Parameter Symbol Minimum Typical Maximum Unit Notes
Tx Disable Assert Time t_o NA Note 4
Tx Disable Negate Time t_on NA Note 4
Module Reset Assert Time t_o_rst 10 msNote 5
Module Reset Negate Time t_on_rst 300 ms Note 6
Time to initialize t_init 300 ms
Tx Fault Assert Time t_fault NA Note 7
Tx Disable to Reset t_reset NA Note 7
LOS Assert Time t_loss_on NA Note 7
LOS De-assert Time t_loss_o NA Note 7
Rate Select Change Time t_ratesel NA Note 7
Serial ID Clock Rate F_serial_clock 100 kHz
Notes:
1. Internally ac coupled and terminated (100 Ohm dierential). These levels are compatible with CML and LVPECL voltage swings.
2. Internally ac coupled with an external 100 ohm dierential load termination.
3. 20%-80% rise and fall times measured with a 500 MHz signal utilizing a 1010 pattern.
4. Tx Disable function as described in the SFP MSA is not used in the 1000BASE-T module.
5. Time from rising edge of Tx Disable until link comes down.
6. Time from falling edge of Tx Disable until auto-negotiation starts.
7. Not used in the 1000BASE-T module
9
Figure 6. Transceiver Timing Diagrams (Module Installed Except Where Noted)
VCC > 3.15 V
t_init
POWER SAVING
(TX_DISABLE)
TRANSMITTED SIGNAL
(AUTO-NEGOTIATION
BEGINS)
t-init: MODULE HOT-PLUGGED OR VOLTAGE APPLIED AFTER INSERTION, WHEN TX_DISABLE IS NEGATED
VCC > 3.15 V
t_init
TX_DISABLE
TRANSMITTED SIGNAL
(AUTO-NEGOTIATION
BEGINS)
t-init: VOLTAGE APPLIED WHEN TX_DISABLE IS ASSERTED
t_on_rst
t_o_rst
Tx_DISABLE
TRANSMITTED SIGNAL
(AUTO-NEGOTIATION
BEGINS ON RISING EDGE)
t_o_rst & t_on_rst: TX_DISABLE (RESET) ASSERTED THEN DE-ASSERTED
t_on_rst
10
Table 3. EEPROM Serial ID Memory Contents at address A0
Addr Hex ASCII Addr Hex ASCII Addr Hex ASCII Addr Hex ASCII
0 03 40 41 A 68 Note 3 96 Note 5
1 04 41 42 B 69 Note 3 97 Note 5
2 00 42 43 C 70 Note 3 98 Note 5
3 00 43 55 U 71 Note 3 99 Note 5
4 00 44 2D - 72 Note 3 100 Note 5
5 00 45 35 5 73 Note 3 101 Note 5
6 08 46 37 7 74 Note 3 102 Note 5
7 00 47 Note 1 75 Note 3 103 Note 5
8 00 48 Note 1 76 Note 3 104 Note 5
9 00 49 Note 1 77 Note 3 105 Note 5
10 00 50 Note 1 78 Note 3 106 Note 5
11 01 51 Note 1 79 Note 3 107 Note 5
12 0D 52 20 80 Note 3 108 Note 5
13 00 53 20 81 Note 3 109 Note 5
14 00 54 20 82 Note 3 110 Note 5
15 00 55 20 83 Note 3 111 Note 5
16 00 56 20 84 Note 4 112 Note 5
17 00 57 20 85 Note 4 113 Note 5
18 64 58 20 86 Note 4 114 Note 5
19 00 59 20 87 Note 4 115 Note 5
20 41 A 60 00 88 Note 4 116 Note 5
21 56 V 61 00 89 Note 4 117 Note 5
22 41 A 62 00 90 Note 4 118 Note 5
23 47 G 63 Note 2 91 Note 4 119 Note 5
24 4F O 64 00 92 00 120 Note 5
25 20 65 Note 1 93 00 121 Note 5
26 20 66 00 94 00 122 Note 5
27 20 67 00 95 Note 2 123 Note 5
28 20 124 Note 5
29 20 125 Note 5
30 20 126 Note 5
31 20 127 Note 5
32 20
33 20
34 20
35 20
36 01
37 00
38 17
39 6A
Notes:
1. The contents of these registers will change dependent on model number.
2. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64-94.
3. Address 68-83 specify a unique identier.
4. Address 84-91 specify the date code.
5. These elds are reserved for optional use by Avago Technologies.
11
Table 4. Summary of Internal IC Registers
Register Description
0 Control
1 Status
2-3 N/A for SFP Module
4 Auto-Negotiation Advertisement
5 Auto-Negotiation Link Partner Ability
6 Auto-Negotiation Expansion
7 Auto-Negotiation Next Page Transmit
8 Auto-Negotiation Link Partner Received Next Page
9 MASTER-SLAVE Control Register
10 MASTER-SLAVE Status Register
11-15 N/A for SFP Module
16 Extended Control 1
17 Extended Status 1
18-19 N/A for SFP Module
20 Extended Control 2
21 Receive Error Counter
22 Cable Diagnostic 1
23-25 N/A for SFP Module
26 Extended Control 3
27 Extended Status 2
28 Cable Diagnostic 2
29-31 N/A for SFP Module
Internal ASIC Registers
The ASIC (or “PHY”, for Physical Layer IC) in the trans-
ceiver module contains 32 registers. Each register
contains 16 bits. The registers are summarized in
table 11 and detailed in table 12 through 28. Each bit
is either Read Only (RO) or Read/Write (R/W). Some
bits are also described as Latch High (LH) or Latch
Low (LL) and/or Self Clearing (SC).
The registers are accessible through the 2-wire se-
rial CMOS EEPROM protocol of the ATMEL AT24C01A
or equivalent. The address of the PHY is 1010110x,
where x is the R/W bit. Each register’s address is
000yyyyy, where yyyyy is the binary equivalent of the
register number. Write and read operations must send
or receive 16 bits of data, so the “multi-page” access
protocol must be used.
12
Table 5. Register 0 (Control)
Bit Name Description
Hardware
Reset
Software
Reset Details
0.15R/W Reset 1 = PHY reset
0 = Normal Operation
0 self-clearing Performs software reset
0.14R/W Loopback 1 = Enable
0 = Disable
0 0 Serial data in on RD+/- is deserial-
ized, then reserialized and sent
out on TD+/-
0.13R/W Speed Selection
(LSB)
0 = 1000 Mb/s 0 Update Paired with bit 0.6. Module may
function at speeds other than
1000 MB/s depending on model
This bit is only meaningful if bit
0.12 is 0.
0.12R/W Auto-Negotiation
Enable
1 = Enable
0 = Disable
1 Update Changes to this bit take eect
after software reset.
0.11R/W Power Down 1 = Power Down
0 = Normal Operation
0 0
0.10R/W Isolate 1 = Isolate
0 = Normal Operation
0 0
0.9R/W/SC Restart Auto-
Negotiation
1 = Restart Auto-Nego-
tiation Process
0 = normal operation
0 Self-clearing
0.8R/W Duplex Mode 1 = Full Duplex
0 = Half Duplex
1 Update This bit is only meaningful if 0.12
is 0.
0.7R/W Collision Test 1 = enable COL signal
test
0 = disable COL signal
test
0 0
0.6R/W Speed Selection
(MSB)
1 = 1000 Mb/s 1 Update Paired with bit 0.13. Module may
function at speeds other than
1000 MB/s depending on model
This bit is only meaningful if bit
0.12 is 0.
0.5:0R/W N/A to SFP Module 000000 000000
13
Table 6. Register 1 (Status)
Bit Name Description
Hardware
Reset
Software
Reset Details
1.15:9
RO
N/A to SFP Module 0000000 0000000
1.8
RO
Extended Status 1 = Extended status information in register
15
1 1 Always 1
1.7
RO
N/A to SFP Module 0 0
1.6
RO
MF Preamble
Suppression
1 = PHY will accept management frames
with preamble suppressed.
1 1 Always 1
1.5
RO
Auto-Negotiation
Complete
1 = Auto-Negotiation Process Completed
0 = Auto-Negotiation Process Not Com-
pleted
0 0
1.4
RO/LH
Remote Fault 1 = remote fault condition detected
0 - no remote fault condition detected
0 0
1.3
RO
Auto-Negotiation
Ability
1 = module is able to perform Auto-Nego-
tiation
0 = module is unable to perform Auto-
Negotiation
1 1
1.2
RO/LL
Link Status 1 = link is up
0 = link is down
0 0
1.1
RO/LH
Jabber Detect 1 = jabber condition detected
0 = no jabber condition detected
0 0
1.0
RO
Extended Capability 1 = extended register capabilities 1 1 Always 1
14
Table 7. Register 4 (Auto-Negotiation Advertisement)
Bit Name Description
Hardware
Reset
Software
Reset Details
4.15:14
R/W
N/A to SFP Module 10 10 When writing to register 4, be
sure to preserve the values of
these bits. Changes to these
values can interrupt the normal
operation of the SFP module.
4.13
R/W
Remote Fault 1 = Remote fault bit is set
0 = No remote fault
0 Retain This bit takes eect after auto-
negotiation is restarted, either
via bit 0.9 or because the link
goes down.
4.12
R/W
N/A to SFP Module 0 Retain
4.11:10
R/W
PAUSE Encoding 11 = Both Asymmetric
PAUSE and Symmetric
PAUSE toward local device
10 = Asymmetric PAUSE
toward link partner
01 = Symmetric PAUSE
00 = No PAUSE
00 Retain This bit takes eect after auto-
negotiation is restarted, either
via bit 0.9 or because the link
goes down.
4.9
R/W
N/A to SFP Module 0 0
4.8
R/W
100BASE-TX Full
Duplex
1 = Advertise PHY is
100BASE-TX full duplex
capable
0 = Advertise PHY is not
100BASE-TX full duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)
Retain This bit takes eect auto-negoti-
ation is restarted via bit 0.9
4.7
R/W
100BASE-TX Half
Duplex
1 = Advertise PHY is
100BASE-TX half duplex
capable
0 = Advertise PHY is not
100BASE-TX half duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)
Retain This bit takes eect auto-negoti-
ation is restarted via bit 0.9
4.6
R/W
10BASE-T Full-
Duplex
1 = Advertise PHY is
10BASE-T full duplex
capable
0 = Advertise PHY is not
10BASE-T full duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)
Retain This bit takes eect auto-negoti-
ation is restarted via bit 0.9
4.5
R/W
10BASE-T Half-
Duplex
1 = Advertise PHY is
10BASE-T half duplex
capable
0 = Advertise PHY is not
10BASE-T half duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)
Retain This bit takes eect auto-negoti-
ation is restarted via bit 0.9
4.4:0
RO
IEEE 802.3 Selector
Field
00001 00001 Set per IEEE standard.
15
Table 8. Register 5 (Auto-Negotiation Link Partner Ability)
Bit Name Description
Hardware
Reset
Software
Reset Details
5.15
RO
Next Page 1 = Link partner advertises next page
ability
0 = Link partner does not advertise next
page ability
0 0
5.14
RO
Acknowledge 1 = Link partner acknowledges receiv-
ing link code word from module
0 = Link partner does not acknowledge
receiving link code word from module
0 0
5.13
RO
Remote Fault 1 = Link partner has a remote fault
0 = Link partner does not have a
remote fault
0 0
5.12
RO
N/A to SFP Module 0 0
5.11:10
RO
PAUSE Encoding 11 = Asymmetric PAUSE and Symmetric
PAUSE toward local device
10 = Asymmetric PAUSE toward link
partner
01 = Symmetric PAUSE
00 = No PAUSE
00 00
5.9:5
RO
N/A to SFP Module 00000 00000
5.4:0
RO
IEEE 802.3 Selector Field 00000 00000 Set per
IEEE standard.
Table 9. Register 6 (Auto-Negotiation Expansion)
Bit Name Description
Hardware
Reset
Software
Reset Details
6.15:5
RO
N/A to SFP Module 00000000000 00000000000
6.4
RO
Parallel Detection
Fault
1 = A fault has been detected via
the Parallel Detection function
0 = A fault has not been detected
via the Parallel Detection function
0 0 This register is not
valid until auto-
negotiation is com-
plete, as indicated
by bit 1.5.
6.3
RO
Link Partner Next
Page Able
1 = Link partner is next page able
0 = Link partner is not next page
able
0 0 See note in bit 6.4.
6.2
RO
Next Page Able 1 = Local device is next page able
0 = Local device is not next page
able
1 1 See note in bit 6.4.
6.1
RO/LH
Page Received 1 = A new page has been received
0 = A new page has not been
received
0 0 See note in bit 6.4.
6.0
RO
Link Partner Auto-
Negotiation Able
1 = Link partner is auto-negotia-
tion able
0 = Link partner is not auto-nego-
tiation able
0 0 See note in bit 6.4.
16
Table 10. Register 7 (Auto-Negotiation Next Page Transmit Register)
Bit Name Description
Hardware
Reset
Software
Reset Details
7.15
R/W
Next Page 1 = Additional next pages
to follow
0 = Last page
0 0
7.14
RO
N/A to SFP Module 0 0
7.13
R/W
Message Page 1 = Message page
0 = Unformatted page
1 1
7.12
R/W
Acknowledge 2 1 = Will comply with
message
0 = Will not comply with
message
0 0
7.11
RO
Toggle 1 = previous value of the
toggle bit was0
0 = previous value of the
toggle bit was 1
0 0
7.10:0
R/W
Message/Unformatted
Code Field
00000000001 00000000001
Table 11. Register 8 (Auto-Negotiation Link Partner Received Next Page)
Bit Name Description
Hardware
Reset
Software
Reset Details
8.15
RO
Next Page 1 = Additional next pages
to follow
0 = Last page
0 0
8.14
RO
Acknowledge 0 0
8.13
RO
Message Page 1 = Message page
0 = Unformatted page
0 0
8.12
RO
Acknowledge 2 1 = Will comply with mes-
sage
0 = Will not comply with
message
0 0
8.11
RO
Toggle 1 = previous value of the
toggle bit was 0
0 = previous value of the
toggle bit was 1
0 0
8.10:0
RO
Message/Unformatted
Code Field
00000000000 00000000000
17
Table 12. Register 9 (MASTER-SLAVE Control)
Bit Name Description Hardware Reset
Software
Reset Details
9.15:13
R/W
Transmitter Test
Mode
000 = Normal Operation
001 = Transmit Waveform Test
010 = Transmit Jitter Test in
MASTER Mode
011 = Transmit Jitter Test in
SLAVE Mode
000 000 The module enters test modes
when MDI crossover is rst
disabled via bits 16.6:5.
9.12
R/W
MASTER-SLAVE
Manual Cong
Enable
1 = Enable MASTER-SLAVE
Manual conguration value in
register 9.11
0 = Disable MASTER-SLAVE
Manual conguration value in
register 9.11
0 Retain This bit takes eect after auto-
negotiation is restarted via
bit 0.9.
9.11
R/W
MASTER-SLAVE
Cong Value
1 = Congure PHY as MAS-
TER during MASTER-SLAVE
negotiation
0 = Congure PHY as SLAVE
during MASTER-SLAVE nego-
tiation
1 Retain This bit takes eect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless
bit 9.12 is 1.
9.10
R/W
Port Type 1 = Prefer PHY as MASTER
(multiport)
0 = Prefer PHY as SLAVE (single
port)
1 Retain This bit takes eect after auto-
negotiation is restarted via bit
0.9. This bit is ignored unless
bit 9.12 is 0.
9.9
R/W
1000BASE-T Full
Duplex
1 = Advertise PHY is 1000BA-
SET-T full duplex capable
0 = Advertise PHY is not
1000BASE-T full duplex
capable
1 Retain This bit takes eect after auto-
negotiation is restarted via
bit 0.9.
9.8
R/W
1000BASE-T Half
Duplex
1 = Advertise PHY is 100BASE-
TX full duplex capable
0 = Advertise PHY is not
100BASE-TX full duplex
capable
1 (for ABCU-
57x1-XXX)
0 (for ABCU-
57x0-XXX)0
Retain This bit takes eect auto-
negotiation is restarted via
bit 0.9
9.7:0RO N/A to SFP
Module
00000000 00000000
18
Table 13. Register 10 (MASTER-SLAVE Status)
Bit Name Description
Hardware
Reset
Software
Reset Details
10.15
RO/LH/SC
MASTER-SLAVE
Conguration Fault
1 = MASTER-SLAVE con-
guration fault detected
0 = No MASTER-SLAVE
conguration fault de-
tected
0 0 This bit is cleared each time that
this register is read. This bit clears
on Auto-Negotiation enable
or Auto-Negotiation complete.
This bit is set if the number of
failed MASTER-SLAVE resolutions
reaches 7. This bit is set if both
PHYs are forced to MASTER or
SLAVE at the same time using
bits 9.12 and 9.11.
10.14
RO
MASTER-SLAVE
Conguration
Resolution
1 = Local PHY
conguration
resolved to MASTER
0 = Local PHY
conguration
resolved to SLAVE
0 0
10.13
RO
Local Receiver
Status
1 = Local Receiver OK
0 = Local Receiver not OK
0 0
10.12
RO
Remote Receiver
Status
1 = Remote Receiver OK
0 = Remote Receiver not
OK
0 0
10.11
RO
Link Partner Full
Duplex
1 = Link Partner is capable
of 1000BASE-T full duplex
0 = Link Parnter is not
capable of 1000BASE-T full
duplex
0 0 This bit is valid only when the
Page Received bit (6.1) is set to 1.
10.10
RO
Link Partner Half
Duplex
1 = Link Partner is capable
of 1000BASE-T half duplex
0 = Link Parnter is not
capable of 1000BASE-T
half duplex
0 0 This bit is valid only when the
Page Received bit (6.1) is set to 1.
10.9:8 N/A to SFP Module 00 00
10.7:0
RO/SC
Idle Error Count Counts errors when
receiving idle patterns.
00000000 00000000 These bits do not roll over
when they are all ones.
19
Table 14. Register 16 (Extended Control 1)
Bit Name Description
Hardware
Reset
Software
Reset Details
16.15:7
R/W
N/A to SFP Module 000000000 Retain (15:10, 7)
or Update (9:8)
When writing to register 16,
be sure to preserve the values
of these bits. Changes to
these values can interrupt the
normal operation of the SFP
module.
16.6:5
R/W
MDI Crossover Mode 00 = Manual MDI
conguration
01 = Manual MDIX
conguration
10 = N/A to SFP
module
11 = Enable
automatic crossover
11 Update Changes to this bit take eect
after software reset.
16.4:0
R/W
N/A to SFP Module 11000 Retain (2:0) or
Update (4:3)
When writing to register 16,
be sure to preserve the values
of these bits. Changes to
these values can interrupt the
normal operation of the SFP
module.
20
Table 15. Register 17 (Extended Status 1)
Bit Name Description
Hardware
Reset
Software
Reset Details
17.15:14
RO
Speed 10 = 1000 Mbps
01 = 100 Mbps
00 = 10 Mbps
0 Retain This bit is only valid after bit 17.11
is set.
17.13
RO
Duplex 1 = Full duplex
0 = Half duplex
0 Retain This bit is only valid after bit 17.11
is set.
17.12
RO/LH
Page Received 1 = Page received
0 = Page not received
0 0
17.11
RO
Speed and
Duplex Resolved
1 = Resolved
0 = Speed not resolved
0 0 This bit is set when auto-nego-
tiation is either completed or
disabled.
17.10
RO
Link 1 = Link up
0 = Link down
0 0
17.9:7
RO
Cable Length 000 = < 50 m
001 = 50 - 80 m
010 = 80 - 110 m
011 = 110 - 140 m
100 = > 140 m
000 000
17.6
RO
MDI Crossover
Status
1 = Crossover
0 = No crossover
0 0 Crossover means that pairs A+/-
(pins 1 & 2 on the RJ45 jack) and
B+/- (pins 3 & 6) are interchanged
and C+/- (pins 4 &5) and D+/- (pins
7 & 8) are interchanged. This bit is
only valid after bit 17.11 is set.
17.5:4
RO
N/A to SFP Module 00 00
17.3
RO
MAC Transmit
Pause Enabled
1 = Transmit pause
enabled
0 = Transmit pause
disabled
0 0 This bit reects the capability of the
MAC to which the module is con-
nected on the serial side. This bit is
only valid after bit 17.11 is set.
17.2
RO
MAC Receive
Pause Enabled
1 = Receive pause
enabled
0 = Receive pause
disabled
0 0 This bit reects the capability of the
MAC to which the module is con-
nected on the serial side. This bit is
only valid after bit 17.11 is set.
17.1
RO
Polarity 1 = Polarity reversed
0 = Polarity not reversed
0 0 This bit is set if any of the four
twisted pairs have the + and - wires
reversed.
17.0
RO
Jabber 1 = Jabber detected
0 = No jabber detected
0
21
Table 16. Register 20 (Extended Control 2)
Bit Name Description
Hardware
Reset
Software
Reset Details
20.15
RO
Link down on no idles 1 = Link lock lost
0 = Link lock intact
0 0 If idle patterns are not seen
within 1 ms, link lock is lost and
link is brought down.
20.14:4
R/W
N/A to SFP Module 00011000110 0001100110 When writing to register 20, be
sure to preserve the values of
these bits. Changes to these
values can interrupt the normal
operation of the SFP module.
20.3 Reserved N/A to SFP
module
This bit must be read and left
R/W unchanged when per-
forming a write.
20.2:0R/W N/A to SFP Module 000 000 When writing to register 20, be
sure to preserve the values of
these bits. Changes to these
values can interrupt the normal
operation of the SFP module.
Table 17. Register 21 (Receive Error Counter)
Bit Name Description
Hardware
Reset
Software
Reset Details
21.15:0
RO/SC
Receive errors Counts errors received
on the 1000BASE-T side
0 0 These bits do not
roll over when they are all
ones.
Table 18. Register 22 (Cable Diagnostic 1)
Bit Name Description
Hardware
Reset
Software
Reset Details
22.15:2
RO
N/A to SFP Module
22.1:0
R/W
MDI Pair Select 00 = Pins 1 & 2 (Channel A)
01 = Pins 3 & 6 (Channel B)
10 = Pins 4 & 5 (Channel C)
11 = Pins 7 & 8 (Channel D)
For VCT results, choose the
twisted pair on which regis-
ter 28 will dsiplay.
22
Table 19. Register 26 (Extended Control 3)
Bit Name Description
Hardware
Reset
Software
Reset Details
26.15:8
RO
N/A to SFP
Module
00000000 Retain
26.7:3
R/W
N/A to SFP
Module
00001 Update When writing to register 26, be
sure to preserve the values of
these bits. Changes to these
values can interrupt the normal
operation of the SFP module.
26.2:0
R/W
RD+/- Output
Amplitude
000=0.50V
001=0.60V
010=0.70V
011=0.80V
100=0.90V
101=1.00V
110=1.10V
111=1.20V
010 Retain All voltages measured peak-to-
peak into a 100-ohm load.
Table 20. Register 27 (Extended Status 2)
Bit Name Description Hardware Reset
Software
Reset Details
27.15:13
RO/SC
N/A to SFP
Module
100 Update
(27.15),
Retain
(27.14:13)
When writing to register
27, be sure to preserve the
values of these bits. Changes
to these values can interrupt
the normal operation of the
SFP module.
27.12
R/W
1000BASE-X
Auto-negotiation
Bypass Enable
1 = Enabled
0 = Disabled
1 Update If enabled, BASE-X link will
come up after 200 ms even
if BASE-X auto-negotiation
fails. When writing to register
27, be sure to preserve the
values of this bit. Changes to
this value can interrupt the
normal operation of the SFP
module.
27.11
RO
1000BASE-X
Auto-negotiation
Bypass Status
1 = BASE-X auto-negotia-
tion failed and BASE-X link
came up becase bypass
mode timer expired
0 = BASE-X link came up
because regular BASE-X
auto-negotiation was
completed
0 Retain See bit 27.12.
27.10:0
R/W
N/A to SFP
Module
0000001000
(ABCU-57x0xxZ)
0000000100
(ABCU-57x1xxZ)
Update When writing to register
27, be sure to preserve the
values of these bits. Changes
to these values can interrupt
the normal operation of the
SFP module.
23
Table 21. Register 28 (Cable Diagnostic 2)
Bit Name Description
Hardware
Reset
Software
Reset Details
28.15
R/W
Enable Cable
Diagnostic Test
1 = Enable test
0 = disable test
0 0 The test can only be performed when the
link is down. If the link partner is trying
to auto-negotiate or if the link partner is
sending out idle link pulses, the test will
proceed.
28.14:13
RO
Status 11 = Test fail
10 = Open detected
in twisted pair
01 = Short detected
in twisted pair
00 = No short or
open detected in
twisted pair
00 00 The twisted pair under test is specied in
register 22.
28.12:8
RO
Reected
Magnitude
11111 = 1 V
10000 = 0 V
00000= -1 V
00000 00000 The twisted pair under test is specied in
register 22.
28.7:0
RO
Distance Distance to the
short or open
00000000 00000000 The distance is given in meters by 13/16
* (decimal equivalent of 28.7:0) + 32 .The
twisted pair under test is specied in
register 22. If no short or open is detected,
these bits are 0s.
24
Figure 7. Module Drawing
Figure 8. Temperature Measurement Point
NOTES:
1. IT IS ACCEPTABLE TO MEASURE THE TEMPERATURE OF THE HOUSING THROUGH THE LABEL.
THE LABEL IS THIN AND MAKES LITTLE DIFFERENCE TO THE TEMPERATURE MEASURED.
67.9 ±0.2
13.6 ±0.1 13.4 ±0.1
47.50 ±0.15
8.5 ±0.1
1 ±0.10
2.25 ±0.10
13.95 MAX.
9.2 ±0.1
34.6 ±0.2
41.8 ±0.15
22.3 ±0.5
41.5 ±0.5
25.2 ±0.5
CL
TEMPERATURE MEASUREMENT POINT
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. Obsoletes AV01-0165EN
AV02-3410EN - March 6, 2014
Figure 9. SFP Host Board Mechanical Layout