DG408LE, DG409LE
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17 , +12 V / ± 5 V / +5 V / +3 V,
8-Ch / Dual 4-Ch High Performance Analog Multiplexers
DESCRIPTION
The DG408LE, DG409LE are monolithic analog
multiplexers / demultiplexers designed to operate on
single and dual supplies. Single supply voltage ranges from
3 V to 16 V while dual supply operation is recommended
with ± 3 V to ± 8 V.
The DG408LE is an 8 channel single-ended analog
multiplexer designed to connect one of eight inputs to
a common output as determined by a 3 bit binary address
(A0, A1, A2). The DG409LE is a dual 4 channel differential
analog multiplexer designed to connect one of four
differential inputs to a common dual output as determined
by its 2 bit binary address (A0, A1). Break-before-make
switching action to protect against momentary crosstalk
between adjacent channels.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer / demultiplexer to all switches
off for stacking several devices. All control inputs, address
(Ax) and enable (EN) are TTL compatible over the full
specified operating temperature range.
The DG408LE, DG409LE feature low on-resistance, fast
switching time, and low leakage. They are ideal for data
acquisition, control and automation, test instrument, and
healthcare products. The DG408LE, DG409LE has an
internal regulator powers the logic circuit. Such design
reduces device power consumption and makes them ideal
for battery operated applications.
The DG408LE, DG409LE are available in TSSOP16,
SOIC16, and QFN16 packages.
FEATURES
• Pin-for-pin compatibility with DG408, DG409,
and DG508, DG509
• 3 V to 16 V single supply or ± 3 V to ± 8 V dual
supply operation
• Low power consumption: 6 μA/max., EN = Vx = 5 V
• Lower on-resistance: RDS(on) - 17 typ.
• Fast switching: tON - 55 ns, tOFF - 36 ns
• Break-before-make guaranteed
• Low leakage: IS(OFF) - 1 nA max.
• TTL, CMOS, LV logic (3 V) compatible
• -99 dB off-isolation and -98 dB crosstalk at 100 kHz
• Low parasitic capacitances: CS(OFF) = 5.5 pF,
CD(ON) = 35 pF (DG408LE)
• ESD Protection:
± 2.5 kV human body model
± 100 V machine model
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
*
This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
BENEFITS
• High accuracy
• Single and dual power rail capacity
• Wide operating voltage range
• Simple logic interface
APPLICATIONS
• Automatic test equipment
• Data acquisition systems
• Meters and instruments
• Medical and healthcare systems
• Communication systems
• Audio and video signal routing
• Relay replacement
• Battery powered systems
• Computer peripherals
• Audio and video signal routing
FUNCTIONAL BLOCK DIAGRAMS AND PIN CONFIGURATIONS
Available
Available
Available
A
0
D
a
A
1
D
b
EN GND
V- V+
S
1a
S
1b
S
2a
S
2b
S
3a
S
3b
S
4a
S
4b
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
89
DG409LE Dual-In- Line, SOIC and TSSOP
S3
A0
S6
D
S4
A1
S8
S7
EN A2
V- GND
S1V+
S2S5
Decoders/Drivers
1
2
3
4
5
6
7
16
15
14
13
12
11
10
Top View
89
DG408LE Dual-In- Line, SOIC and TSSOP
DG408LE, DG409LE
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QFN OUTLINE
Note
• For low and high voltage levels for VAX and VEN consult “Digital Control” parameters for specific V+ operation.
Note
• -T1 indicates tape and reel, -GE3 indicates lead (Pb)-free and RoHS-compliant, NO -GE3 indicates standard tin/lead finish.
• Exposed pad of QFN package can be connected to GND, V-, or left floating.
EN A0A1A2
S4DS
8S7
V-
S1
S2
S3
GND
V+
S5
S6
Decoder/Driver
1
2
3
4
5678
12
11
10
9
16 15 14 13
Decoder/Driver
V-
S1a
S2a
S3a
1
2
3
4
S4a DaDbS4b
5678
V+
S1b
S2b
S3b
12
11
10
9
EN A0A1GND
16 15 14 13
DG408LE QFN16
(3 mm x 3 mm)
DG409LE QFN16
(3 mm x 3 mm)
TRUTH TABLE (DG408LE)
A2A1A0EN ON SWITCH
XXX0 None
0001 1
0011 2
0101 3
0111 4
1001 5
1011 6
1101 7
1111 8
TRUTH TABLE (DG409LE)
A1A0EN ON SWITCH
XX0 None
001 1
011 2
101 3
111 4
ORDERING INFORMATION
TEMP. RANGE CONFIGURATION PACKAGE PART NUMBER MIN. ORDER / PACK. QUANTITY
-40 °C to +85 °C
Lead-free
8 Channel
Single Ended
DG408LE
16-pin TSSOP DG408LEDQ-GE3 Tube 360 units
DG408LEDQ-T1-GE3 Tape and reel, 3000 units
16-pin SOIC DG408LEDY-GE3 Tube 500 units
DG408LEDY-T1-GE3 Tape and reel, 2500 units
16-pin QFN
(3 mm x 3 mm)
Variation 2
DG408LEDN-T1-GE4 Tape and reel, 2500 units
Dual 4 Channel
Differential
DG409LE
16-pin TSSOP DG409LEDQ-GE3 Tube 360 units
DG409LEDQ-T1-GE3 Tape and reel, 3000 units
16-pin SOIC DG409LEDY-GE3 Tube 500 units
DG409LEDY-T1-GE3 Tape and reel, 2500 units
16-pin QFN
(3 mm x 3 mm)
Variation 2
DG409LEDN-T1-GE4 Tape and reel, 2500 units
DG408LE, DG409LE
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Notes
a. Signals on SX, DX, AX, or EN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 8 mW/°C above 75 °C.
d. Derate 17.3 mW/°C above 70 °C
e. Also applies when V- = GND
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
PARAMETER LIMIT UNIT
V+ to V- e 18
VGND to V- -18
Digital Inputs a, VS, VD(V-) - 0.3 to (V) + 0.3
Current (any terminal) 30 mA
Peak Current, S or D (pulsed at 1 ms, 10 % duty cycle max.) 100
Storage Temperature (D suffix) -65 to +125 °C
Power Dissipation (package) b
16-pin plastic TSSOP c 600
mW16-pin narrow SOIC c 600
16-pin miniQFN d1385
ESD Human Body Model (HBM); per ANSI / ESDA / JEDEC® JS-001 2500 V
Latch Up Current, per JESD78D 300 mA
DG408LE, DG409LE
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Notes
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin.
SPECIFICATIONS (Single Supply 12 V)
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 12 V, ± 10 %, V- = 0 V
VEN = 0.8 V or 2.4 V f
TEMP. b TYP.
d
D SUFFIX
-40 °C to +85 °C UNIT
MIN. c MAX. c
Analog Switch
Analog Signal Range e VANALOG Full - 0 12 V
Drain-Source
On-Resistance RDS(on) VD = 10.8 V, VD = 2 V or 9 V, IS = 10 mA
sequence each switch on
Room 17 - 23
Full - - 27
RDS(on) Matching
Between Channels g RDS VD = 10.8 V, VD = 2 V or 9 V
IS = 10 mA
Room 1 - 3
On-Resistance Flatness RFLAT(on) Room 3 6.5
Switch Off Leakage
Current a
IS(off) VEN = 0 V, VD = 11 V or 1 V
VS = 1 V or 11 V
Room - -1 1
nA
Full - -5 5
ID(on)
Room - -1 1
Full - -5 5
Channel On Leakage
Current aID(on) VS = VD = 1 V or 11 V Room - -1 1
Full - -5 5
Digital Control
Logic High Input Voltage VINH Full - 2.4 - V
Logic Low Input Voltage VINL Full - - 0.8
Input Current aIIN VAX = VEN = 2.4 V or 0.8 V Full - -1 1 μA
Dynamic Characteristics
Transition Time tTRANS
VS1 = 8 V, VS8 = 0 V, (DG408LE)
VS1b = 8 V, VS4b = 0 V, (DG409LE)
see figure 2
Room 85 - 100
ns
Full - - 110
Break-Before-Make Time tOPEN VS(all) = VDA = 5 V
see figure 4
Room 34 1 -
Full - - -
Enable Turn-On Time tON(EN) VAX = 0 V, VS1 = 5 V (DG408LE)
VAX = 0 V, VS1b = 5 V (DG409LE)
see figure 3
Room 55 - 72
Full - - 82
Enable Turn-Off Time tOFF(EN)
Room 36 - 47
Full - - 50
Charge Injection
e
(DG408LE)
QC
L = 1 nF, VGEN = 6 V, RGEN = 0 Room -11 - - pC
Charge Injection
e
(DG409LE)
Room -10 - -
Off Isolation e, h (DG408LE) OIRR
f = 100 kHz, RL = 50
Room -99 - -
dB
Off Isolation e, h (DG409LE) Room -87 - -
Crosstalk e (DG408LE) XTALK
Room -98 - -
Crosstalk e (DG409LE) Room -109 - -
Source Off Capacitance e
(DG408LE) CS(off) f = 1 MHz, VS = 0 V, VEN = 0 V
Room 5.5 - -
pF
Source Off Capacitance e
(DG409LE) Room 5.5 - -
Drain Off Capacitance e
(DG408LE) CD(off) f = 1 MHz, VD = 2.4 V, VEN = 0 V
Room 25 - -
Drain Off Capacitance e
(DG409LE) Room 13.5 - -
Drain On Capacitance
(DG408LE) CD(on) f = 1 MHz, VD = 0 V, VEN = 2.4 V
(DG409LE only)
Room 35 - -
Drain On Capacitance e
(DG409LE) Room 23.5 - -
Power Supplies
Power Supply Range V+ - 3 12 V
Power Supply Current I+ VEN = VA = 0 V or 5 V Room 3.5 6 μA
DG408LE, DG409LE
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Notes
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on channel 4 do to proximity to the drain pin.
SPECIFICATIONS (Dual Supply V+ = 5 V, V - = -5 V)
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 5 V, ± 10 %, V- = -5 V
VEN = 0.6 V or 2.4 V f
TEMP. b TYP. d
D SUFFIX
-40 °C to +85 °C UNIT
MIN. cMAX. c
Analog Switch
Analog Signal Range e VANALOG Full - -5 5 V
Drain-Source
On-Resistance RDS(on) VD = ± 3.5 V, IS = 10 mA
sequence each switch on
Room 15 - 25
Full - - 30
Switch Off Leakage
Current a
IS(off) V+ = 5.5, V- = 5.5 V
VEN = 0 V, VD = ± 4.5 V, VS = ± 4.5 V
Room - -1 1
nA
Full - -5 5
ID(off)
Room - -1 1
Full - -5 5
Channel On Leakage
Current a ID(on) V+ = 5.5 V, V- = -5.5 V
VEN = 2.4 V, VD = ± 4.5 V, VS = ± 4.5 V
Room - -1 1
Full - -5 5
Digital Control
Logic High Input Voltage VINH Full - 2.4 - V
Logic Low Input Voltage VINL Full - - 0.6
Input Current a IIN VAX = VEN = 2.4 V or 0.6 V Full - -1 1 μA
Dynamic Characteristics
Transition Time tTRANS
VS1 = 3.5 V, VS8 = -3.5 V, (DG408LE)
VS1b = 3.5 V, VS4b = -3.5 V, (DG409LE)
see figure 2
Room 87 - 100
ns
Full - - 120
Break-Before-Make Time
tOPEN VS(all) = VDA = 3.5 V
see figure 4
Room 84 1 -
Full - - -
Enable Turn-On Time tON(EN) VAX = 0 V, VS1 = 3.5 V (DG408LE)
VAX = 0 V, VS1b = 3.5 V (DG409LE)
see figure 3
Room 58 - 73
Full - - 80
Enable Turn-Off Time tOFF(EN)
Room 31 - 46
Full - - 51
Source Off Capacitance e
(DG408LE) CS(off) f = 1 MHz, VS = 0 V, VEN = 0 V
Room 6 - -
pF
Source Off Capacitance e
(DG409LE) Room 5.5 - -
Drain Off Capacitance e
(DG408LE) CD(off) f = 1 MHz, VD = 0 V, VEN = 0 V
Room 26 - -
Drain Off Capacitance e
(DG409LE) Room 14 - -
Drain On Capacitance e
(DG408LE) CD(on) f = 1 MHz, VD = 0 V, VEN = 2.4 V
Room 36 - -
Drain On Capacitance e
(DG409LE) Room 24 - -
DG408LE, DG409LE
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Notes
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on channel 4 do to proximity to the drain pin.
SPECIFICATIONS (Single Supply 5 V)
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 5 V, ± 10 %, V- = 0 V
VEN = 0.6 V or 2.4 V f
TEMP. b TYP. d
D SUFFIX
-40 °C to +85 °C UNIT
MIN. cMAX. c
Analog Switch
Analog Signal Range e VANALOG Full - 0 5 V
Drain-Source
On-Resistance RDS(on) V+ = 4.5 V, VD or VS = 1 V or 3.5 V,
IS = 5 mA
Room 28 - 36
Full - - 41
RDS(on) Matching Between
Channels g RDS V+ = 4.5 V, VD = 1 V or 3.5 V,
IS = 5 mA
Room 1 - 3
On-Resistance Flatness RFLAT(on) Room - - 4
Switch Off Leakage
Current a
IS(off) V+ = 5.5 V, VS = 1 V or 4 V
VD = 4 V or 1 V
Room - -1 1
nA
Full - -5 5
ID(off)
Room - -1 1
Full - -5 5
Channel On Leakage
Current a ID(on) V+ = 5.5 V, VD = VS = 1 V or 4 V
sequence each switch on
Room - -1 1
Full - -5 5
Digital Control
Logic High Input Voltage VINH V+ = 5 V Full - 2.4 - V
Logic Low Input Voltage VINL Full - - 0.6
Input Current a IIN VAX = VEN = 2.4 V or 0.6 V Full - -1 1 μA
Dynamic Characteristics
Transition Time tTRANS
VS1 = 3.5 V, VS8 = 0 V, (DG408LE)
VS1b = 3.5 V, VS4b = 0 V, (DG409LE)
see figure 2
Room 113 - 135
ns
Full - - 165
Break-Before-Make Time tOPEN VS(all) = VDA = 3.5 V,
see figure 4
Room 75 1 -
Full - - -
Enable Turn-On Time tON(EN) VAX = 0 V, VS1 = 3.5 V (DG408LE)
VAX = 0 V, VS1b = 3.5 V (DG409LE)
see figure 3
Room 77 - 89
Full - - 110
Enable Turn-Off Time tOFF(EN)
Room 43 - 50
Full - - 53
Charge Injection
e
(DG408LE)
QC
L = 1 nF, RGEN = 0 , VGEN = 2.5 V Room -2 - - pC
Charge Injection
e
(DG409LE)
Room -2 - -
Off Isolation e, h (DG408LE) OIRR
f = 100 kHz, RL = 50
Room -100 - -
dB
Off Isolation e, h (DG409LE) Room -83 - -
Crosstalk e (DG408LE) XTALK
Room -101 - -
Crosstalk e (DG409LE) Room -108 - -
Source Off Capacitance e
(DG408LE) CS(off) f = 1 MHz, VS = 0 V, VEN = 0 V
Room 6.5 - -
pF
Source Off Capacitance e
(DG409LE) Room 6.5 - -
Drain Off Capacitance e
(DG408LE) CD(off) f = 1 MHz, VD = 0 V, VEN = 0 V
Room 30 - -
Drain Off Capacitance e
(DG409LE) Room 16 - -
Drain On Capacitance e
(DG408LE) CD(on) f = 1 MHz, VD = 0 V, VEN = 2.4 V
Room 40 - -
Drain On Capacitance e
(DG409LE) Room 26.5 - -
DG408LE, DG409LE
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Notes
a. Leakage parameters are guaranteed by worst case test condition and not subject to production test.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on channel 4 do to proximity to the drain pin.
SPECIFICATIONS (Single Supply 3 V)
PARAMETER SYMBOL
TEST CONDITIONS
UNLESS OTHERWISE SPECIFIED
V+ = 3 V, ± 10 %, V- = 0 V
VEN = 0.4 V or 2 V f
TEMP. b TYP. d
D SUFFIX
-40 °C to +85 °C UNIT
MIN. cMAX. c
Analog Switch
Analog Signal Range e VANALOG Full - 0 3 V
Drain-Source
On-Resistance RDS(on) V+ = 2.7 V, VD = 0.5 or 2.2 V,
IS = 5 mA
Room 63 - 80
Full - - 92
Switch Off Leakage
Current a
IS(off)
V+ = 3.3 V, VS = 2 or 1 V, VD = 1 or 2 V
Room - -1 1
nA
Full - -5 5
ID(off)
Room - -1 1
Full - -5 5
Channel On Leakage
Current a ID(on) V+ = 3.3 V, VD = VS = 1 V or 2 V
sequence each switch on
Room - -1 1
Full - -5 5
Digital Control
Logic High Input Voltage VINH Full - 2 - V
Logic Low Input Voltage VINL Full - - 0.4
Input Current a IIN VAX = VEN = 2.4 V or 0.4 V Full - -1 1 μA
Dynamic Characteristics
Transition Time tTRANS
VS1 = 1.5 V, VS8 = 0 V, (DG408LE)
VS1b = 1.5 V, VS4b = 0 V, (DG409LE)
see figure 2
Room 211 - 275
ns
Full - - 300
Break-Before-Make Time tOPEN VS(all) = VDA = 1.5 V,
see figure 4
Room 209 1 -
Full - - -
Enable Turn-On Time tON(EN) VAX = 0 V, VS1 = 1.5 V (DG408LE)
VAX = 0 V, VS1b = 1.5 V (DG409LE)
see figure 3
Room 125 - 150
Full - - 180
Enable Turn-Off Time tOFF(EN)
Room 45 - 75
Full - - 95
Charge Injection
e
(DG408LE)
QC
L = 1 nF, RGEN = 0 , VGEN = 1.5 V Room 0 - - pC
Charge Injection
e
(DG409LE)
Room -0.4 - -
Off Isolation e, h (DG408LE) OIRR
f = 100 kHz, RL = 50
Room -90 - -
dB
Off Isolation e, h (DG409LE) Room -95 - -
Crosstalk e (DG408LE) XTALK
Room -95 - -
Crosstalk e (DG409LE) Room -93 - -
Source Off Capacitance e
(DG408LE) CS(off) f = 1 MHz, VS = 0 V, VEN = 0 V
Room 7 - -
pF
Source Off Capacitance e
(DG409LE) Room 7 - -
Drain Off Capacitance e
(DG408LE) CD(off) f = 1 MHz, VD = 0 V, VEN = 0 V
Room 33 - -
Drain Off Capacitance e
(DG409LE) Room 18 - -
Drain On Capacitance e
(DG408LE) CD(on) f = 1 MHz, VD = 0 V, VEN = 2 V
Room 43 - -
Drain On Capacitance e
(DG409LE) Room 28 - -
DG408LE, DG409LE
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
RDS(on) vs. VD and Power Supply
RDS(on) vs. VD and Temperature (Dual Supply)
Input Threshold vs. V+ Supply Voltage
RDS(on) vs. VD and Power Supply
RDS(on) vs. VD and Temperature
Switching Time vs. Supply Voltage
10
15
20
25
30
35
40
45
50
55
60
65
70
0123456789101112
RDS(on) - Drain-Source On-Resistance ()
VD- Drain Voltage (V)
V+ = 3.3 V
V+ = 12 V
V+ = 5 V
5
10
15
20
25
30
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
RDS(on) - Drain-Source On-Resistance ()
VD - Drain Voltage (V)
25 °C
-40 °C
V+ = 5 V, V- = - 5 V
85 °C
1.2
1.3
1.4
1.5
1.6
1.7
1.8
34567891011121314
VT (V)
V+ - Positive Supply Voltage (V)
Upper Threshold Limit
Lower Threshold Limit
10
15
20
25
-5 -4 -3 -2 -1 0 1 2 3 4 5
RDS(on) - Drain-Source On-Resistance ()
VD- Drain Voltage (V)
V+ = +5 V
V- = -5 V
15
20
25
30
35
40
45
50
0123456
RDS - On-Resistance ()
VD- Drain Voltage (V)
V+ = 5 V, V- = 0 V
25 C
85 C
-40 C
20
40
60
80
100
120
140
160
180
3456789101112
Switching Speed (ns)
V+ - Positive Supply Voltage(V)
tOFF
tTRANS tON
DG408LE, DG409LE
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S16-0389-Rev.A, 07-Mar-16 9Document Number: 78084
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Leakage Current vs. Analog Voltage
Charge Injection vs. Analog Voltage (DG409LE)
Drain/Source Capacitance vs. Analog Voltage (DG408LE)
Charge Injection vs. Analog Voltage (DG408LE)
Insertion Loss, Off Isolation, and Crosstalk vs. Frequency
-150
-100
-50
0
50
100
-5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
Leakage Current (pA)
VD, VS– Analog Voltage (V)
Id(on)
Is(off)
Id(off)
-15
-10
-5
0
5
10
-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12
Q - Charge Injection (pC)
Vs- Source Voltage (V)
V+ = +/- 5 V
V+ = 12 V
V+ = 5 V
0
5
10
15
20
25
30
35
40
45
50
0123456789101112
CD, CS– Drain/SourceCapacitance (pF)
Drain/Source Capacitance vs. Analog Voltage (DG408L)
Id(on)
Is(off)
Id(off)
V+ = 12 V, V- = 0 V
-20
-15
-10
-5
0
5
-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12
Q - Charge Injection (pC)
Vs- Source Voltage (V)
V+ = +/- 5 V
V+ = 12 V
V+ = 5 V
-110
-90
-70
-50
-30
-10
10
0 1 10 100 1000
Loss (dB)
Frequency (MHz)
Insertion Loss (-3 dB = 39 MHz)
Off Isolation
Crosstalk
V+ = 5 V, V- = 0
DG408LE, DG409LE
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S16-0389-Rev.A, 07-Mar-16 10 Document Number: 78084
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SCHEMATIC DIAGRAM (Typical Channel)
Fig. 1
TEST CIRCUITS
Fig. 2 - Transition Time
EN
A0
S1
D
V+
Sn
V-
Decode/
Drive
Level
Shift
V-
V+
AX
GND
Voltage Regulator
Body
Snatcher
V-
V-
V-
A1
A0
A2
A1
A0
V+
V-
EN
V+
V-GND
D
35 pF
VO
S1
S2 - S
7
S8
50
300
VS8
VS1
V+
V-
EN
V+
V-GND
35 pF
VO
S1b
S1a - S
4a, Da
S4b
300
Db
Logic
Input
Switch
Output
VS1
VO
tTRANS
tr < 20 ns
tf < 20 ns
S8 ON (DG408LE)
or
S4 ON (DG409LE)
S1 ON
tTRANS
50 %
VS8
50 %
90 %
3 V
0 V
DG408LE
DG409LE VSB4
VS1
3 V
3 V
VAX
50
90 %
DG408LE, DG409LE
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S16-0389-Rev.A, 07-Mar-16 11 Document Number: 78084
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Fig. 3 - Enable Switching Time
Fig. 4 - Break-Before-Make Interval
50 %
80 %
Logic
Input
Switch
Output
VO
VS
tOPEN
tr < 20 ns
tf < 20 ns
0 V
3 V
0 V
EN V+
GND V-
35 pF
V-
3 V
A2Db, D
All S and Da
300
VO
50
bbm.5
4/9
A1
A0DG408LE
DG409LE
VS1
DG408LE, DG409LE
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S16-0389-Rev.A, 07-Mar-16 12 Document Number: 78084
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Fig. 5 - Charge Injection
Fig. 6 - Off Isolation Fig. 7 - Crosstalk
Fig. 8 - Insertion Loss Fig. 9 - Source Drain Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?78084.
A0
EN
A1
A2
VO
V+
GND V-
D
Vg
Rg
SX
CL
1 nF
Channel
Select
3 V
0 V
ON
Logic
Input
Switch
Output
VO
VO is the measured voltage due to charge transfer
error Q, when the channel turns off.
Q = CL x VO
OFF
V+
V-
VO
RL
50
VO
V+
GND V-
A2
D
A1
A0
S8
SX
VS
EN
Rg = 50
Off Isolation = 20 log
VOUT
VIN
VIN
V+
V-
RL
50
VO
V+
GND V-
A2
D
A1
A0
S8
SX
VS
EN
Rg = 50
Crosstalk = 20 log
VOUT
VIN
VIN S1
V+
V-
RL
50
A2
VO
D
Rg = 50
Insertion Loss = 20 log
VOUT
A1
VIN
A0
VSS1
V+
GND V-EN
V-
V+
f = 1 MHz
S1
D
EN
GND
V+
V-
Meter
HP4192A
Impedance
Analyzer
or Equivalent
S
8
A
1
A
2
A
0
Channel
Select
V-
V+
All Leads
0.101 mm
0.004 IN
E
HC
D
e B A1 LĬ
4312 8756
131416 15 91012 11
Package Information
Vishay Siliconix
Document Number: 71194
02-Jul-01 www.vishay.com
1
SOIC (NARROW): 16ĆLEAD
JEDEC Part Number: MS-012
MILLIMETERS INCHES
Dim Min Max Min Max
A1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B0.38 0.51 0.015 0.020
C0.18 0.23 0.007 0.009
D9.80 10.00 0.385 0.393
E3.80 4.00 0.149 0.157
e1.27 BS C 0.050 BSC
H5.80 6.20 0.228 0.244
L0.50 0.93 0.020 0.037
Ĭ0_8_0_8_
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5300
Package Information
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Revision: 09-May-16 1Document Number: 72208
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
QFN-16 Lead (3 x 3)
Notes
(1) All dimensions are in millimeters.
(2) N is the total number of terminals.
(3) Dimension b applies to metallized terminal and is measured between 0.25 and 0.30 mm from terminal tip.
(4) Coplanarity applies to the exposed heat sink slug as well as the terminal.
(5) The pin #1 identifier may be either a mold or marked feature, it must be located within the zone indicated.
DIM.
VARIATION 1 VARIATION 2
MILLIMETERS INCHES MILLIMETERS INCHES
MIN. NOM MAX. MIN. NOM MAX. MIN. NOM MAX. MIN. NOM MAX.
A 0.80 0.90 1.00 0.031 0.035 0.039 0.80 0.90 1.00 0.031 0.035 0.039
b 0.18 0.23 0.30 0.007 0.009 0.012 0.18 0.25 0.30 0.007 0.010 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122
D2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071
E 2.90 3.00 3.10 0.114 0.118 0.122 2.90 3.00 3.10 0.114 0.118 0.122
E2 1.00 1.15 1.25 0.039 0.045 0.049 1.50 1.70 1.80 0.059 0.067 0.071
e 0.50 BSC 0.020 BSC 0.50 BSC 0.020 BSC
L 0.30 0.40 0.50 0.012 0.016 0.020 0.30 0.40 0.50 0.012 0.016 0.020
ECN: T16-0233-Rev. D, 09-May-16
DWG: 5899
-C-
C0.08
C0.10//
-A-
-B-
E
SEATING
PLANE
A3
A1
A
NX
SIDE VIEW
(3)
Terminal Tip
Exposed Pad
D
D/2
E/2
BOTTOM VIEW
TOP VIEW
C0.25
C0.25
E2/2
E2
D2
D2/2
L
e
3 x e
3 x e
C0.10 MA B
4xb
(3)
(4)
(4)
Vishay Siliconix
Package Information
Document Number: 74417
23-Oct-06
www.vishay.com
1
Symbols
DIMENSIONS IN MILLIMETERS
Min Nom Max
A - 1.10 1.20
A1 0.05 0.10 0.15
A2 - 1.00 1.05
B 0.22 0.28 0.38
C - 0.127 -
D 4.90 5.00 5.10
E 6.10 6.40 6.70
E1 4.30 4.40 4.50
e-0.65-
L 0.50 0.60 0.70
L1 0.90 1.00 1.10
y--0.10
θ10°3°6°
ECN: S-61920-Rev. D, 23-Oct-06
DWG: 5624
TSSOP: 16-LEAD
PAD Pattern
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Revision: 02-Sep-11 1Document Number: 63550
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
RECOMMENDED MINIMUM PAD FOR TSSOP-16
0.281
(7.15)
Recommended Minimum Pads
Dimensions in inches (mm)
0.171
(4.35)
0.055
(1.40)
0.012
(0.30)
0.026
(0.65)
0.014
(0.35)
0.193
(4.90)
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72608
24 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-16
RECOMMENDED MINIMUM PADS FOR SO-16
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
0.372
(9.449)
Return to Index
Return to Index
Legal Disclaimer Notice
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Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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