ispLSI ® 5384VE
In-System Programmable
3.3V SuperWIDE™ High Density PLD
15384ve_05
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
•Second Generation SuperWIDE HIGH DENSITY
IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
—3.3V Power Supply
—User Selectable 3.3V/2.5V I/O
—18000 PLD Gates / 384 Macrocells
—Up to 192 I/O Pins
—384 Registers
—High-Speed Global Interconnect
—SuperWIDE Generic Logic Block (32 Macrocells) for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
—PCB Efficient Ball Grid Array (BGA) Package Options
—Interfaces with Standard 5V TTL Devices
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 165 MHz Maximum Operating Frequency
—tpd = 6.0 ns Propagation Delay
—TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
—Electrically Erasable and Reprogrammable
— Non-Volatile
—Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
•100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
•ARCHITECTURE FEATURES
—Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
—Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
—Macrocells Support Concurrent Combinatorial and
Registered Functions
—Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
—Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
—Programmable I/O Supports Programmable Bus
Hold, Pull-up, Open Drain and Slew Rate Options
—Four Global Product Term Output Enables, Two
Global OE Pins and One Product Term OE per
Macrocell
Global Routing Pool
(GRP)
Boundary
Scan
Interface
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and three extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
three extra product terms are used for shared controls:
reset, clock, clock enable and output enable.
Functional Block Diagram
Specifications ispLSI 5384VE
2
Functional Block Diagram
Figure 1. ispLSI 5384VE Functional Block Diagram (192-I/O Option)
Package Type Multplexed Signals
256 fpBGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE
272 BGA I/O 119 / CLK2 I/O 131 / CLK3 I/O 0 / TOE
Global Routing Pool
(GRP)
Boundary
Scan
Interface
GOE0
GOE1
TDI
TCK
TMS
TDO
CLK 1
CLK 0
1CLK 3
1CLK 2
VCCIO
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Input Bus
Input Bus Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block Generic
Logic Block
I/O 111
I/O 110
I/O 109
I/O 108
I/O 99
I/O 98
I/O 97
I/O 96
I/O 127
I/O 126
I/O 125
I/O 124
I/O 115
I/O 114
I/O 113
I/O 112
I/O 143
I/O 142
I/O 141
I/O 140
I/O 131
I/O 130
I/O 129
I/O 128
I/O 48
I/O 49
I/O 50
I/O 51
I/O 60
I/O 61
I/O 62
I/O 63
I/O 64
I/O 65
I/O 66
I/O 67
I/O 76
I/O 77
I/O 78
I/O 79
I/O 80
I/O 81
I/O 82
I/O 83
I/O 92
I/O 93
I/O 94
I/O 95
I/O 159
I/O 158
I/O 157
I/O 156
I/O 147
I/O 146
I/O 145
I/O 144
I/O 175
I/O 174
I/O 173
I/O 172
I/O 163
I/O 162
I/O 161
I/O 160
I/O 191
I/O 190
I/O 189
I/O 188
I/O 179
I/O 178
I/O 177
I/O 176
1
TOE
I/O 1
I/O 2
I/O 3
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 44
I/O 45
I/O 46
I/O 47
1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Use the table below
to determine which I/O is shared by package type.
RESET
Specifications ispLSI 5384VE
3
ispLSI 5000VE Description (Continued)
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch and the necessary clocks and
control logic to allow combinatorial or registered opera-
tion. The macrocells each have two outputs, combinatorial
and registered. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facili-
tates efficient use of this feature to construct high-speed
input registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also available to
each register, eliminating the need to gate the clock to the
macrocell registers. Reset for the macrocell register is
provided from the global signal, its polarity is user-
selectable. The macrocell register can be programmed to
operate as a D-type register or a D-type latch.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global Routing
Pool contains one input from each macrocell output and
one input from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA in 3.3V mode. The output drivers
have a separate VCCIO reference input which is inde-
pendent of the main VCC supply for the device. This
feature allows individual output drivers to drive either
3.3V (from the device VCC) or 2.5V (from the VCCIO pin)
output levels while the device logic and the output current
drive are powered from device supply (VCC). The output
drivers also provide individually programmable edge
rates and open drain capability. A programmable pullup
resistor is provided to tie off unused inputs. Additionally,
a programmable bus-hold latch is available to hold tristate
outputs in their last valid state until the bus is driven again
by some device.
The ispLSI 5000VE Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000VE Family Members
The ispLSI 5000VE Family ranges from 128 macrocells
to 512 macrocells and operates from a 3.3V power
supply. All family members will be available with multiple
package options. The ispLSI 5000VE Family device
matrix showing the various bondout options is shown in
the table below.
The interconnect structure (GRP) is very similar to Lattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
The ispLSI 5000VE encompasses the innovative fea-
tures of the ispLSI 5000VA family with several
enhancements. The macrocell is optimized and the T-
type flip flop option is removed. To improve the efficiency
of design fits, the Product Term Reset Logic is simplified
and the polarity option as well as the Global Preset
function are removed. The programmable output-delay
feature (skew option) is also removed. As a result, the
ispLSI 5000VE is not JEDEC compatible with the ispLSI
5000VA. ispLSI 5000VA and 5000VE pinouts may differ
in the same package, however all programming and
power/ground pins are located in the same locations.
Table 1. ispLSI 5000VE Family
Package Type
ispLSI 5128VE
Device GLBs Macrocells 128 TQFP 256 fpBGA 272 BGA 388 fpBGA 388 BGA
4 128 96 I/O — — — —
8256 96 I/O 144 I/O 144 I/O — —
12 384 — 192 I/O 192 I/O — —
16 512 —
100 TQFP
—
72 I/O
—
—192 I/O 192 I/O 256 I/O 256 I/O
ispLSI 5256VE
ispLSI 5384VE
ispLSI 5512VE
Specifications ispLSI 5384VE
4
Figure 2. ispLSI 5384VE Block Diagram (192 I/O Version)
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
16
16
16
16
16
16
16
16
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
16 16
32
16
I/O
160
160
PT
160
32
D
Q
32
16
I/O
68
DQ
160
160
68
160
PT
32
32 32
16 16
576
16 16
32 32
16 16
32 32
16 16
32 32
16 16
32 32
16 16
32 32
16 16
3
3
PT 3
PT
3
3
3
PT 3
PT
3
3
3
PT 3
PT
3
3
3
PT 3
PT
3
3
3
PT 3
PT
3
3
3
PT 3
PT
3
RESET
GOE1
GOE0
CLK1
CLK0
IO0/TOE
CLK3
CLK2
GLB0
GLB1
GLB2
GLB3
GLB4
GLB5
GLB11
GLB10
GLB9
GLB8
GLB7
GLB6
Specifications ispLSI 5384VE
5
Figure 3. ispLSI 5000VE Generic Logic Block (GLB)
012 6667
Macrocell 0
PT 160
Macrocell 1
Macrocell 15
Macrocell 31
PT 9
PT 8
PT 7
PT 6
PT 5
PT 0
PT 1
PT 2
PT 3
PT 4
PT 79
PT 78
PT 77
PT 76
PT 75
PT 159
PT 158
PT 157
PT 156
PT 155
Shared PT Clock
Global PTOE 0 ... 3
4
Shared PT Clock
Global PTOE 0 ... 3
4
Shared PT Clock
Global PTOE 0 ... 3
4
To I/O Pad
Shared PT Clock
Global PTOE 0 ... 3
4
From GRP
PTSA
Global PTOE Bus
From PTSA
From PTSA
From PTSA
From PTSA
PT 161
PT 162
Shared PT Reset
Shared PT Reset
Shared PT Reset
Shared PT Reset
PTSA bypass
PT Clock
PT Preset
PT Reset
PTOE
PTSA bypass
PT Clock
PT Preset
PT Reset
PTOE
PTSA bypass
PT Clock
PT Preset
PT Reset
PTOE
PTSA bypass
PT Clock
PT Preset
PT Reset
PTOE
To GRP
To I/O Pad
To GRP
To I/O Pad
To GRP
To I/O Pad
To GRP
Specifications ispLSI 5384VE
6
Figure 4. ispLSI 5000VE Macrocell
PTSA
DQ
RP
PTSA bypass
PT Clock
PT Reset
Clk En
R/L
PTOE
Shared PT Clock
GOE0
GOE1
PT Preset
speed/
power
TOE
CLK0
CLK1 Clk
CLK2
CLK3
Global Reset
Shared PT Reset
Global PTOE 2
Global PTOE 3
Global PTOE 0
Global PTOE 1
VCCIOVCCIO VCC
Slew
rate Open
drain
2.5V/3.3V
Output
I/O Pad
To GRP
To GRP
Input threshold
2.5V/3.3V
Note: Not all macrocells have I/O pads.
Specifications ispLSI 5384VE
7
Global Clock Distribution
The ispLSI 5000VE Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but are
also available for logic implementation through GRP
signal routing. Figure 5 shows these different clock
distribution options.
Figure 5. ispLSI 5000VE Global Clock Structure
CLK0
CLK1
CLK 0
(dedicated pin)
CLK 1
(dedicated pin)
IO/CLK 2
(shared pin)
IO/CLK 3
(shared pin)
CLK2
CLK3
to/from GRP
Global Reset
RESET
(dedicated pin)
to/from GRP
IO0/TOE
(shared pin) TOE
to/from GRP
Specifications ispLSI 5384VE
8
Figure 6. Boundary Scan Register Circuit for I/O Pins
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Normal
Function
OE
EXTEST
Update DR
SCANOUT
(to next cell)
Clock DR
SCANIN
(from previous
cell)
Shift DR
Normal
Function
TOE
DQ
DQ
DQ
D
1
0
1
0
1
0
QDQ
I/O Pin
Reset
BSCAN
Registers BSCAN
Latches
HIGHZ
0
PROG_MODE
EXTEST
1
0
1
SCANOUT
(to next cell)
Clock DR
SCANIN
(from previous
cell)
Shift DR
DQ
Input Pin 0
1
Specifications ispLSI 5384VE
9
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
TDO
Data to be
captured
Data to be
driven out
Valid Data Valid Data
Valid Data Valid Data
Data Captured
btsu
T
bth
T
btcl
T
btch
T
btcp
T
btvo
T
btco
T
btoz
T
btcpsu
T
btcph
T
btuov
T
btuco
T
btuoz
T
SYMBOL PARAMETER MIN MAX UNITS
tbtcp TCK [BSCAN test] clock pulse width 125 – ns
tbtch TCK [BSCAN test] pulse width high 62.5 – ns
tbtcl TCK [BSCAN test] pulse width low 62.5 – ns
tbtsu TCK [BSCAN test] setup time 25 – ns
tbth TCK [BSCAN test] hold time 25 – ns
trf TCK [BSCAN test] rise and fall time 50 – mV/ns
tbtco TAP controller falling edge of clock to valid output –25ns
tbtoz TAP controller falling edge of clock to data output disable –25ns
tbtvo TAP controller falling edge of clock to data output enable –25ns
tbtcpsu BSCAN test Capture register setup time 25 – ns
tbtcph BSCAN test Capture register hold time 25 – ns
tbtuco BSCAN test Update reg, falling edge of clock to valid output –50ns
tbtuoz BSCAN test Update reg, falling edge of clock to output disable –50ns
tbtuov BSCAN test Update reg, falling edge of clock to output enable –50ns
Specifications ispLSI 5384VE
10
Absolute Maximum Ratings 1, 2
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Tri-Stated Output Voltage Applied........... -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
Table 2-0005/5KVE
V
CC
V
CCIO
PARAMETER
Supply Voltage
I/O Reference Voltage
Commercial T
A
= 0°C to +70°CMIN. MAX. UNITS
3.00
2.3
3.60
3.60
V
Industrial T
A
= -40°C to +85°C3.00 3.60 V
V
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL
Table 2-0006/5KVE
C
PARAMETER
Clock Capacitance 10
UNITSTYPICAL TEST CONDITIONS
2
pf V = 3.3V, V = 0.0V
CC CK
C
I/O Capacitance 10
1
pf V = 3.3V, V = 0.0V
CC I/O
C
Global Input Capacitance 10
3
pf V = 3.3V, V = 0.0V
CC G
Erase Reprogram Specification
Table 2-0008/5KVE
PARAMETER MINIMUM MAXIMUM UNITS
ispLSI Erase/Reprogram Cycles 10000 – Cycles
Specifications ispLSI 5384VE
11
Switching Test Conditions
Input Pulse Levels
Table 2-0003/5KVE
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
GND to VCCIOmin
≤ 1.5ns 10% to 90%
1.5V
1.5V
See Figure 9
3-state levels are measured 0.5V from
steady-state active level.
Output Load Conditions (See Figure 9)
TEST CONDITION R1
3.3V 2.5V
R2 CL
A 35pF
D35pF
B35pF
35pF
Active High
Slow Slew
Active Low
C5pF
5pF
511Ω
∞
∞
511Ω
511Ω
∞
475Ω
∞
475Ω
∞
∞
475Ω
R1 R2
316Ω
∞
∞
316Ω
316Ω
∞
348Ω
∞
348Ω
∞
∞
348Ω
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004A/5KVE
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
Figure 9. Test Load
V
CCIO
R1
R2CL
*
Device
Output Test
Point
*
CL includes Test Fixture and Probe Capacitance.
0213D
VOL
SYMBOL
1. I/O voltage configuration must be set to VCC. Table 2-0007/5KVE
VOH
VIH
VIL
PARAMETER
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
VCCIO = min, IOL = 8 mA
VCCIO = min, IOH = -4 mA
CONDITION MIN. TYP. MAX. UNITS
–
2.4
2.0
-0.3
–
–
–
–
0.4
–
5.25
0.8
V
V
VCCIO I/O Reference Voltage 3.0 – 3.6 V
V
V
Specifications ispLSI 5384VE
12
DC Electrical Characteristics
Over Recommended Operating Conditions
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
VIH
SYMBOL
2.5V/5KVE
VOH
PARAMETER
Input High Voltage
Output High Voltage V
CCIO=min
, I
OH
= -2mA
V
CCIO=min
, I
OL
= 2mA
CONDITION MIN. TYP. MAX. UNITS
1.7
1.8
–
–
5.25
–
V
VCCIO
VIL
I/O Reference Voltage
Input Low Voltage 2.3
-0.3 –
–2.7
0.7 V
V
V
V
CCIO=min
, I
OH
= -100µA2.1 – – V
––0.6V
V
CCIO=min
, I
OL
= 100µA––0.2V
VOL Output Low Voltage
1. I/O voltage configuration must be set to VCCIO.
SYMBOL
1. Pullup is capable of pulling to a minimum voltage of V
OH
under no-load conditions. DC Char_5KVE
IPU
IBHL
PARAMETER
IBHH
IBHLO
1I/O Active Pullup Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
IIH
IIL Input or I/O High Leakage Current
Input or I/O Low Leakage Current 0V ≤ V ≤ V (Max.)
IN IL
CONDITION MIN. TYP. MAX. UNITS
–
–
–
–
40
-40
–
–
–
–
–
–
–
–
-10
10
-200
50
–
–
550
µA
µA
µA
µA
µA
µA
IBHLH
IBHT
Bus Hold High Overdrive Current
Bus Hold Trip Points –
VIL
–
–-550
VIH
µA
V
IVCCIO Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax)– – 30 mA
µA
(VCCIO-0.2)V ≤ VIN ≤ VCCIO
VCCIO ≤ VIN ≤ 5.25V
0V ≤ VIN ≤ VIL
0V ≤ VIN ≤ VCCIO
0V ≤ VIN ≤ VCCIO
VIN = VIL(max)
VIN = VIH(min)
Specifications ispLSI 5384VE
13
External Switching Characteristics
Over Recommended Operating Conditions
.MARAP TSET
3
.DNOC
NOITPIRCSED
5,4
561-521- STINU
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t
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6
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t
2dp
6
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f
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1
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f
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f
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2
002—761— zHM
t
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t
1oc
6
AyaleDtuptuOotkcolC.geRBLG—0.3—5.4sn
t
1h —ssapybTP5,kcolCretfaemiTdloH.geRBLG0.0—0.0— sn
t
2us —kcolCerofebemiTputeS.geRBLG5.5—0.7— sn
t
2h —kcolCretfaemiTdloH.geRBLG0.0—0.0— sn
t
3us —htaP.geRtupnI,kcolCerofebemiTputeS.geRBLG0.3—5.3— sn
t
3h —htaP.geRtupnI,kcolCretfaemiTdloH.geRBLG5.0—5.0— sn
t
1r AyaleDtuptuOotniPteseR.txE—0.8— 0.01sn
t
1wr
7
—noitaruDesluPteseR.txE 0.4—0.5— sn
t
sid/netp
6
C/BelbasiD/elbanEtuptuOmreTtcudorPlacoL—0.7—5.8sn
t
sid/netpg
6
C/BelbasiD/elbanEtuptuOmreTtcudorPlabolG—0.21—0.41sn
t
sid/neg
6
C/BelbasiD/elbanEtuptuOottupnIEOlabolG—5.4—5.5sn
t
sid/net
6
C/BelbasiD/elbanEtuptuOottupnIEOtseT—5.8— 5.01sn
t
hw —hgiH,noitaruDesluPkcolC.cnyS.txE 5.2—0.3— sn
t
lw —woL,noitaruDesluPkcolC.cnyS.txE 5.2—0.3— sn
.kcabdeefPRGgnisuretnuoctib-61dradnatS.1
vgnimiTspe.1ev4835
.
2
.
0
.%05nahtrehtofoelcycytudkcolcarofwollaotsisihT.)lwt+hwt(/1nahtsselebyam)elggoT(xamf.2 .noitcessnoitidnoCtseTgnihctiwSecnerefeR.3 -hgihdna,0KLC,BLG1fodaolPRGa,tuonafASTPesactsrowhtiwnekaterasrebmungnimitlla,esiwrehtodetonsselnU.4 .yarraDNAdeeps .revirdtuptuoevitcalamrongnisuderusaemsretemarapgnimiT.5 sioiccVnehwderrucnisiyaledsn5.0lanoitiddanA.ecnereferegatlovO/IsaccVhtiwderusaemerasretemarapyaledehT.6 .ecnereferegatlovO/Isadesu .roivahebtuptuonwonknuesuacyammuminimnahtsselshtdiwesluP.7
Specifications ispLSI 5384VE
14
External Switching Characteristics
Over Recommended Operating Conditions
.MARAP TSET
3
.DNOC
NOITPIRCSED
5,4
001-08- STINU
.NIM.XAM.NIM.XAM
t
1dp
6
AssapyBTP5,yaleD.porPataD—0.01—0.21sn
t
2dp
6
AyaleDnoitagaporPataD—0.21—0.51sn
f
xam AkcabdeeFlanretnIhtiwycneuqerFkcolC
1
001—08— zHM
f
).txE(xam —)1oct+2ust(/1,kcabdeeF.txEhtiw.qerFkcolC76—65— zHM
f
).goT(xam —elggoTxaM,ycneuqerFkcolC
2
521—001— zHM
t
1us —ssapybTP5,klCerofebemiTputeS.geRBLG0.7—0.8— sn
t
1oc
6
AyaleDtuptuOotkcolC.geRBLG—0.6—0.7sn
t
1h —ssapybTP5,kcolCretfaemiTdloH.geRBLG0.0—0.0— sn
t
2us —kcolCerofebemiTputeS.geRBLG0.9— 0.11—sn
t
2h —kcolCretfaemiTdloH.geRBLG0.0—0.0— sn
t
3us —htaP.geRtupnI,kcolCerofebemiTputeS.geRBLG5.4—5.5— sn
t
3h —htaP.geRtupnI,kcolCretfaemiTdloH.geRBLG0.1—0.1— sn
t
1r AyaleDtuptuOotniPteseR.txE—5.11—0.31sn
t
1wr
7
—noitaruDesluPteseR.txE 5.6—0.8— sn
t
sid/netp
6
C/BelbasiD/elbanEtuptuOmreTtcudorPlacoL—0.01—0.21sn
t
sid/netpg
6
C/BelbasiD/elbanEtuptuOmreTtcudorPlabolG—5.51—0.71sn
t
sid/neg
6
C/BelbasiD/elbanEtuptuOottupnIEOlabolG—5.7—0.9sn
t
sid/net
6
C/BelbasiD/elbanEtuptuOottupnIEOtseT—5.11—5.21sn
t
hw —hgiH,noitaruDesluPkcolC.cnyS.txE 0.4—0.5— sn
t
lw —woL,noitaruDesluPkcolC.cnyS.txE 0.4—0.5— sn
.kcabdeefPRGgnisuretnuoctib-61dradnatS.1
0.2.vgnimiTspe.2ev4835
.%05nahtrehtofoelcycytudkcolcarofwollaotsisihT.)lwt+hwt(/1nahtsselebyam)elggoT(xamf.2 .noitcessnoitidnoCtseTgnihctiwSecnerefeR.3 -hgihdna,0KLC,BLG1fodaolPRGa,tuonafASTPesactsrowhtiwnekaterasrebmungnimitlla,esiwrehtodetonsselnU.4 .yarraDNAdeeps .revirdtuptuoevitcalamrongnisuderusaemsretemarapgnimiT.5 sioiccVnehwderrucnisiyaledsn5.0lanoitiddanA.ecnereferegatlovO/IsaccVhtiwderusaemerasretemarapyaledehT.6 .ecnereferO/Isadesu .roivahebtuptuonwonknuesuacyammuminimnahtsselshtdiwesluP.7
Specifications ispLSI 5384VE
15
Internal Timing Parameters
Over Recommended Operating Conditions
In/Out Delays
tin Input Buffer Delay – 0.6 – 1.3 – 2.3 – 2.3 ns
tgclk_in Global Clock Buffer Input Delay (clk0) – 0.7 – 1.3 – 1.8 – 1.8 ns
trst Global Reset Pin Delay – 4.9 – 6.6 – 7.1 – 7.1 ns
tgoe Global OE Pin Delay – 3.2 – 3.9 – 5.9 – 7.4 ns
tbuf Output Buffer Delay – 1.9 – 2.2 – 2.7 – 3.7 ns
ten Output Enable Delay – 1.3 – 1.6 – 1.6 – 1.6 ns
tdis Output Disable Delay – 1.3 – 1.6 – 1.6 – 1.6 ns
Routing/GLB Delays
troute GRP and Logic Delay – 3.2 – 3.6 – 4.0 – 4.5 ns
tpdb 5-pt Bypass Propagation Delay – 0.3 – 0.4 – 1.0 – 1.5 ns
tpdi Combinatorial Propagation Delay – 0.0 – 0.0 – 0.0 – 0.0 ns
tptsa Product Term Sharing Array – 1.8 – 2.4 – 3.0 – 4.5 ns
tfbk Internal Feedback Delay – 0.0 – 0.0 – 0.0 – 0.5 ns
tinreg Input Buffer to Macrocell Register Delay – 2.5 – 2.5 – 2.5 – 3.5 ns
Register/Latch Delays
tsRegister Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns
ts_pt Register Setup Time (Product Term Clock) 0.6 – 1.0 – 1.5 – 1.5 – ns
thRegister Hold Time 2.9 – 3.0 – 4.0 – 5.0 – ns
tcoi Register Clock to GLB Output Delay – 0.4 – 1.0 – 1.5 – 1.5 ns
tsl Latch Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns
thl Latch Hold Time 2.9 – 3.0 – 4.0 – 5.0 – ns
tgoi Latch Gate to GLB Output Delay – 0.4 – 1.0 – 1.5 – 1.5 ns
tpdli GLB Latch propagation Delay – 1.0 – 1.5 – 2.0 – 2.5 ns
tces Clock Enable Setup Time 4.1 – 4.3 – 5.3 – 6.3 – ns
tceh Clock Enable Hold Time 0.9 – 1.7 – 2.7 – 3.7 – ns
tsri Asynchronous Set/Reset to GLB Output Delay – 1.2 – 1.2 – 1.7 – 2.2 ns
tsrr Asynchronous Set/Reset Recovery Time 0.8 – 1.2 – 1.2 – 2.2 – ns
Control Delays
tptclk Macrocell PT Clock Delay – 0.4 – 0.4 – 0.5 – 0.5 ns
tbclk Block PT Clock Delay – 1.4 – 1.9 – 2.5 – 2.5 ns
tptsr Macrocell PT Set/Reset Delay – 2.1 – 3.7 – 4.8 – 4.8 ns
tbsr Block PT Set/Reset Delay – 3.1 – 5.7 – 6.8 – 6.8 ns
tptoe Macrocell PT OE Delay – 1.9 – 2.0 – 2.1 – 3.6 ns
tgptoe Global PT OE Delay – 6.9 – 7.5 – 7.6 – 8.6 ns
-165 -125 -100 -80
MIN MAX MIN MAX MIN MAX MIN MAX UNITPARAMETER DESCRIPTION
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet
for further details. Timing v 2.0
Specifications ispLSI 5384VE
16
ispLSI 5384VE Timing Parameters (continued)
Timing Table/5384VE
Timing v.2.0
Tioi Input Adders
Routing Adders
Tioo Output Adders1
Tbla Additional Block Loading Adders
UNITS
ADDER
-100 -80
BASE PARAMETER
ADDER TYPE
clk1
clk3
1.7 ns
clk2 1.7 ns
ns
1 0.1 ns
2 0.2 ns
3 0.3 ns
tgclk_in
tgclk_in
tgclk_in
troute
troute
troute
1.7
1.7 1.71.7
0.1
0.2
0.3
-125-165
1.7
1.7
0.1
0.2
0.3
1.4
tlp 1.5 ns
troute 1.51.51.0
1.4 1.71.4
0.1
0.1
0.2
4 0.4 ns
troute 0.40.40.3
5 0.5 ns
troute 0.50.50.4
6 0.6 ns
troute 0.60.60.4
7 0.7 ns
troute 0.70.70.5
8 0.8 ns
troute 0.80.80.6
9 0.9 ns
troute 0.90.90.6
10 1.0 ns
troute 1.01.00.7
11 1.1 ns
troute 1.11.1
0.8
1Timing for open drain configurations is the same as non-open drain configurations.
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
Slow Slew I/O
LVCMOS25_out 0.5 ns
ns
tbuf, ten, tdis
tbuf, ten 4.04.0
0.50.5
4.04.0
0.5
LVCMOS33_out 0.0 ns
tbuf, ten, tdis 0.00.00.0
LVTTL_out 0.0 ns
tbuf, ten, tdis 0.00.00.0
Specifications ispLSI 5384VE
17
ispLSI 5384VE Timing Model
tBLA
tLP
tIOI
tBSR
tPTSR
tGPTOE
tPTOE
tPDi
tGOE
tRST
tIN
tINREG
tROUTE
tPDb
tFBK
tBUF
tIOO
tEN
tDIS
tPTSA
tPTCLK
tBCLK
tGCLK_IN
IN
Q
OE
From Feedback
In/Out
Delays
In/Out
Delays
Routing/
GLB Delays
Register/
Latch Delays
Control
Delays
Feedbac
k
OUTDATA
MC Reg
CE
S/R
CLK
RST
Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array
and VCC I/O option).
5000VE Timing Model
Specifications ispLSI 5384VE
18
Power Consumption
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will reduce the power dissipation for these
product terms. Figure 10 shows the relationship between
power and operating frequency.
Power consumption in the ispLSI 5384VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of five product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of five. The fast “high-speed”
260
0255075100 125 150 175 200
f
max (MHz)
I
CC (mA)
Notes: Configuration of 24 16-bit Counters
Typical Current at 3.3V, 25° C
ispLSI 5384VE
High Speed Mode
ispLSI 5384VE
Low Power Mode
0127/5384VE
ICC can be estimated for the ispLSI 5384VE using the following equation:
High Speed Mode: ICC = 22 + (# of PTs * 0.314) + (# of nets * Fmax * 0.00317)
Low Power Mode: ICC = 22 + (# of PTs * 0.271) + (# of nets * Fmax * 0.00317)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Fmax = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
340
420
460
380
300
220
Figure 10. Typical Device Power Consumption vs fmax
Specifications ispLSI 5384VE
19
TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
TDI Input - This pin is the JTAG Test Data In pin used to load data.
TDO Output - This pin is the JTAG Test Data Out pin used to shift data out.
TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon
customer's design. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1 Input - These two pins are the Global Output Enable input pins.
RESET Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active
high or low input) for this pin is selectable.
I/O Input/Output – These are the general purpose I/O used by the logic array.
GND Ground
NC1No connect.
VCC Vcc
CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
CLK2 / I/O, Input/Output - These pins share functionality. They can be used as dedicated clock inputs for
CLK3 / I/O all registers, as well as I/O pins.
VCCIO Input - This pin is used for optional 2.5V outputs. Every I/O can independently select either 3.3V
or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches
only draw current from this supply.
Signal Descriptions
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Specifications ispLSI 5384VE
20
Signal Configuration
ispLSI 5384VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CLK0
VCC
VCC
VCCVCC
VCC
VCC
TMS
TCKTDIVCCVCCVCC
VCCGND
VCC GNDGND
GND
GND
GNDGNDVCCVCC
GOE0GOE1
VCCVCC GNDGNDGNDGND
GND
GNDGNDGND VCCVCC
VCCVCC GNDGNDGND
VCCIO RESET
VCCTDO VCC GNDGNDGND
VCC
VCC
GND
GND
GNDGNDGNDGND
GND
GND
NC1
NC1
CLK1
I/O
165
I/O
168
I/O
172
I/O
175
I/O
177
I/O
179
I/O
187
I/O
188
I/O 0/
TOE
I/O
2
I/O
5
I/O
9
I/O
14
I/O
16
I/O
21
I/O
28
I/O
30
I/O
32
I/O
33
I/O
37
I/O
38
I/O
44
I/O
45
I/O
49
I/O
50
I/O
52
I/O
53
I/O
54
I/O
60
I/O
61
I/O
17
I/O
18
I/O
24
I/O
25
I/O
29
I/O
34
I/O
40
I/O
46
I/O
48
I/O
58
I/O
64
I/O
67
I/O
62
I/O
69
I/O
72
I/O
13
I/O
20
I/O
22
I/O
26
I/O
36
I/O
42
I/O
41
I/O
56
I/O
57
I/O
66
I/O
65
I/O
70
I/O
73
I/O
12
I/O
11
I/O
76
I/O
74
I/O
78
I/O
6
I/O
8
I/O
77 I/O
71 I/O
63 I/O
55 I/O
47 I/O
43 I/O
35 I/O
27 I/O
19
I/O
80
I/O
81
I/O
1
I/O
4
I/O
82 I/O
75 I/O
68 I/O
59 I/O
51 I/O
39 I/O
31 I/O
23 I/O
15
I/O
84
I/O
85
I/O
86 I/O
83 I/O
79 I/O
10 I/O
7
I/O
88
I/O
89
I/O
190
I/O
191
I/O
90
I/O
92 I/O
91 I/O
87 I/O
189 I/O
3
I/O
93
I/O
183
I/O
184
I/O
94 I/O
95 I/O
99 I/O
182 I/O
186
I/O
180
I/O
185
I/O
98 I/O
103 I/O
107 I/O
170 I/O
178
I/O
96
I/O
97
I/O
102
I/O
100 I/O
176
I/O
181
I/O
171
I/O
173
I/O
101 I/O
112 I/O
122 I/O
127 I/O
134 I/O
142 I/O
150 I/O
158 I/O
166
I/O
110 I/O
118 I/O
130 I/O
137 I/O
146 I/O
154 I/O
162 I/O
174
I/O
104
I/O
167
I/O
169
I/O
111
I/O
109
I/O
105
I/O
161
I/O
160
I/O
159
I/O
155
I/O
148
I/O
143
I/O
141
I/O
138
I/O
135
I/O
128
I/O
123
I/O
120
I/O
114
I/O
106
I/O
164
I/O
163
I/O
157
I/O
156
I/O
149
I/O
144
I/O
136
I/O
132
I/O
129
I/O
124
I/O
117
I/O
115
I/O
108
I/O
153
I/O
152
I/O
151
I/O
147
I/O
145
I/O
140
I/O
139
I/O
133
I/O
126
I/O
125
I/O
121
I/O
116
I/O
113 A
B
AI/O 131/
CLK3
I/O 119/
CLK2
B
C C
D D
E E
FF
G G
H H
J J
K K
L L
M M
NN
P P
RR
T T
16 15 14 13 12 11 10
1. NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
9 8 7 6 5 4 3 2 1
ispLSI 5384VE
Bottom View
Specifications ispLSI 5384VE
21
Signal Configuration
ispLSI 5384VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size)
20 19 18 17 16 15 14 13 12 11 10 987654321
AA
B B
C C
D
GNDNC
1
NC
1
NC
1
NC
1
I/O
170
NC
1
NC
1
NC
1
NC
1
I/O
18
NC
1
NC
1
NC
1
NC
1
NC
1
NC
1
NC
1
GNDGNDGNDGND VCCVCCVCC
GOE1
GOE0
NC
1
NC
1
NC
1
NC
1
NC
1
VCCVCC
NC
1
NC
1
NC
1
GND
GND
GNDGND
GND
GNDGNDGND CLK1 VCC
VCC
VCC
TMSTCK
TDI
VCC
VCCVCC
CLK0 NC
1
NC
1
NC
1
NC
1
NC
1
NC
1
GNDTDO
VCCIO RESET
GND GND GND
GND GND GND GND
GNDVCC GND GND GND
GND GND GND GND
D
EE
FispLSI 5384VE F
G
Bottom View
G
HH
JJ
KK
L L
M M
N N
P P
RR
TT
U U
VV
W W
YY
20 19 18 17 16 15 14 13 12 11 10 987654321
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
I/O
164 I/O
165
I/O
169
I/O
166
I/O
162
I/O
134
I/O
130
I/O
127
I/O
172
I/O
176
I/O
179
I/O
178
I/O
174
I/O
190
I/O
191
I/O
90
I/O
89
I/O
91
I/O
187 I/O
189
I/O
188
I/O
94 I/O
95
I/O
93
I/O
92
I/O
185 I/O
186
I/O
184
I/O
183
I/O
96
I/O
181 I/O
182
I/O
180
I/O
98 I/O
99
I/O
97
I/O
177
I/O
106
I/O
101 I/O
103
I/O
100
I/O
175
I/O
173
I/O
171
I/O
168
I/O
104 I/O
107
I/O
102
I/O
108 I/O
110 I/O
112
I/O
105
I/O
167
I/O
155
I/O
145
I/O
133
I/O
124
I/O
118
I/O
113
I/O
109 I/O
161
I/O
156
I/O
152
I/O
148
I/O
144
I/O
138
I/O
123
I/O
120
I/O
117
I/O
111
I/O
163
I/O
159
I/O
157
I/O
153
I/O
150
I/O
147
I/O
143
I/O
137 I/O
141
I/O
135
I/O
128
I/O
125
I/O
121
I/O
116
I/O
160
I/O
158
I/O
154
I/O
146
I/O
142 I/O
151
I/O
149
I/O
140
I/O
139
I/O
136
I/O
132
I/O
129
I/O
126
I/O
122
I/O
115
I/O
114
I/O 119/
CLK2
I/O 131/
CLK3
I/O 0/
TOE
I/O
1
I/O
2
I/O
6
I/O
7I/O
8
I/O
10 I/O
11
I/O
16
I/O
22
I/O
26 I/O
23
I/O
30
I/O
33
I/O
36
I/O
40
I/O
44 I/O
43
I/O
49
I/O
52
I/O
54
I/O
57
I/O
61
I/O
67 I/O
63
I/O
25 I/O
19
I/O
29
I/O
32
I/O
41 I/O
39 I/O
35
I/O
45
I/O
46
I/O
50
I/O
53
I/O
56
I/O
60
I/O
66
I/O
17
I/O
20
I/O
24
I/O
34 I/O
31 I/O
27 I/O
15
I/O
38
I/O
42
I/O
62 I/O
59 I/O
55 I/O
51 I/O
47
I/O
65
I/O
69 I/O
68
I/O
72
I/O
13
I/O
14
I/O
21
I/O
37
I/O
48
I/O
58
I/O
70 I/O
71
I/O
73 I/O
64 I/O
28
I/O
74
I/O
75
I/O
76
I/O
78
I/O
79
I/O
9
I/O
12
I/O
77
I/O
80
I/O
81
I/O
4I/O
3
I/O
5
I/O
82
I/O
84 I/O
83
I/O
85
I/O
86
I/O
88 I/O
87
Specifications ispLSI 5384VE
22
Part Number Description
Ordering Information
Device Number
Grade
Blank = Commercial
I = Industrial
ispLSI 5384VE XXX X XXXX
Speed
165 = 165 MHz fmax
125 = 125 MHz fmax
100 = 100 MHz fmax
80 = 80 MHz fmax Power
L = Low
Package
F256 = 256-Ball fpBGA
(Thermally Enhanced)
B272 = 272-Ball BGA
(Thermally Enhanced)
–
Device Family
X
0212/5384ve
Table 2-0041A/5384VE
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
165 6.0 256-Ball fpBGAispLSI 5384VE-165LF256
165 6.0 272-Ball BGAispLSI 5384VE-165LB272
125 7.5 256-Ball fpBGAispLSI 5384VE-125LF256
125 7.5 272-Ball BGAispLSI 5384VE-125LB272
100 10 256-Ball fpBGAispLSI 5384VE-100LF256
100 10 272-Ball BGA
ispLSI 5384VE-100LB272
COMMERCIAL
Table 2-0041B/5384VE
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
125 7.5 256-Ball fpBGAispLSI 5384VE-125LF256I
125 7.5 272-Ball BGAispLSI 5384VE-125LB272I
100 10 256-Ball fpBGAispLSI 5384VE-100LF256I
100 10 272-Ball BGAispLSI 5384VE-100LB272I
80 12 256-Ball fpBGAispLSI 5384VE-80LF256I
80 12 272-Ball BGA
ispLSI 5384VE-80LB272I
INDUSTRIAL
The ispLSI 5384VE is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster
(i.e. ispLSI 5384VE-165LF256) than the Industrial speed grade (i.e. ispLSI 5384VE-125LF256I).
