6.5 GHz, Ultrahigh Dynamic Range,
Differential Amplifier
Data Sheet
ADL5569
Rev. C Document Feedback
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Technical Support www.analog.com
FEATURES
−3 dB bandwidth: 6.5 GHz typical
Preset 20 dB voltage gain, can be reduced by adding
external resistors
Differential or single-ended input to differential output
Internally dc-coupled inputs and outputs
Low noise input stage: 9.3 dB noise figure at 2 GHz
Low distortion at 5 V supply and 2 V p-p output with 100 Ω load
500 MHz: −78 dBc (HD2), −71 dBc (HD3), −80 dBc (IMD3)
2 GHz: −64 dBc (HD2), −52 dBc (HD3), −65 dBc (IMD3)
Input voltage noise (NSD, RTI): 1.0 nV/√Hz at 100 MHz
Single-supply operation: ac-coupled applications
Dual-supply operation: dc-coupled applications
Slew rate: 24 V/ns at 2 V p-p output
DC power consumption: 86 mA per amplifier at 5 V
APPLICATIONS
Differential ADC drivers for GSPS ADCs
High speed data acquisition
Single-ended to differential conversion
DAC buffering
DC coupling and level shifting
RF/IF gain blocks
Balun alternative from dc to 4 GHz
SAW filter interfacing
FUNCTIONAL BLOCK DIAGRAM
50Ω
R
G
500Ω
R
F
50Ω
R
G
500Ω
R
F
GM B
50Ω
R
G
500Ω
R
F
VIN
VIP
VON
VOP
VIN2
NOTES
1. R
G
IS THE SERIES RESISTANCE O F T HE AMPLIFIER,
AND R
F
IS THE FEE DBACK RE S ISTANCE
OF THEAMPLIFIER.
VIP2
VON2
VOP2
PDB VCOM VCC
GND GND
PDB2 VCOM2 VCC2
1
2
311
GM B
50Ω
R
G
500Ω
R
F
4
5
13
12
10
9
678
16 15 14
ADL5569
15671-001
Figure 1.
GENERAL DESCRIPTION
The ADL5569 is a high performance, dual, differential amplifier
with 20 dB of voltage gain, optimized for applications spanning
from dc to 6.5 GHz. The amplifier is available in a dual format,
and it offers a low referred to input (RTI) noise spectral density
(NSD) of 1.0 nV/√Hz (at 100 MHz) and excellent distortion
performance over a wide frequency range, making it an ideal
driver for high speed 12-bit to 16-bit analog-to-digital converters
(ADCs). The ADL5569 is ideally suited for use in high perfor-
mance zero intermediate frequency (IF) and complex IF receiver
designs. In addition, this device has excellent low distortion for
single-ended input driver applications.
Using two external series resistors for each amplifier expands
the gain flexibility of the amplifier and allows any gain selection
from 6 dB to 20 dB for a differential input. For a single-ended
input, the gain can be adjusted from 6 dB to 17 dB with the
addition of some external resistors. This device maintains low
distortion through its output common-mode range of 2.0 V to
3.0 V, providing a flexible capability for driving ADCs with
ac levels up to 2 V p-p.
Operating from a single 5 V supply, the quiescent current of the
ADL5569 is typically 86 mA per amplifier. When disabled, the
amplifiers consume only 8 mA per amplifier.
The device is optimized for wideband, low distortion, and low
noise operation, giving it unprecedented second harmonic
distortion (HD2) and third harmonic distortion (HD3) from
dc to 4 GHz. These attributes, together with its adjustable gain
capability, make this device the amplifier of choice for driving a
wide variety of ADCs, mixers, pin diode attenuators, surface
acoustic wave (SAW) filters, and a multitude of discrete radio
frequency (RF) devices.
Fabricated on an Analog Devices, Inc., high speed silicon germa-
nium (SiGe) process, the ADL5569 is supplied in a compact
2.5 mm × 3 mm, 16-lead LFCSP package and operates over the
−40°C to +85°C temperature range.
ADL5569 Data Sheet
Rev. C | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 15
Basic Connections ...................................................................... 15
Input and Output Interfacing ................................................... 16
Gain Adjustment and Interfacing ............................................ 17
Effect of Load Capacitance ....................................................... 18
GSPS ADC Interfacing .............................................................. 18
Soldering Information and Recommended Land Pattern .... 20
Evaluation Board ........................................................................ 20
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
11/2018—Rev. B to Rev. C
Changes to GSPS ADC Interfacing Section ................................ 18
Updated Outline Dimensions ....................................................... 23
8/2018—Rev. A to Rev. B
Changes to Gain Adjustment and Interfacing Section .............. 17
7/2018—Rev. 0 to Rev. A
Changes to Figure 4 and Figure 7 ................................................... 8
Changes to Figure 10, Figure 11, Figure 12, and Figure 13 ......... 9
Changes to Figure 19 and Figure 20 Captions ............................ 10
Changes to Figure 23 and Figure 24 ............................................. 11
5/2018—Revision 0: Initial Versi on
Data Sheet ADL5569
Rev. C | Page 3 of 23
SPECIFICATIONS
Supply voltage (VS) = 5 V, maximum gain, output common-mode voltage (VCOM) = VS/2, source impedance (RS) = 100 Ω differential, load
impedance (RL) = 100 Ω differential, output voltage (VOUT) = 2 V p-p composite, frequency = 500 MHz, TA = 25°C, parameters specified for
differential input and differential output, and signal spacing = 2 MHz for two tone measurements, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth1 VOUT ≤ 0.5 V p-p 6.5 GHz
Bandwidth, 1.0 dB Flatness VOUT ≤ 1.0 V p-p 4.8 GHz
Voltage Gain (AV)
Differential Input RL = open 20 dB
R
L
= 100 Ω differential
6
dB
Single-Ended Input RL = 100 Ω differential 6 17 dB
Gain Accuracy ±0.15 dB
Gain Supply Sensitivity VS ± 5% 8.6 mdB/V
Gain Temperature Sensitivity TA = −40°C to +85°C 4 mdB/°C
Slew Rate Rising, VOUT = 2 V p-p step 24 V/ns
Falling, VOUT = 2 V p-p step 24 V/ns
Settling Time 2 V step to 1% 500 ps
Overdrive Recovery Time Differential input voltage step from 2 V to
0 V for VOUT ≤ ±20 mV
6 ns
Reverse Isolation (SDD12) PDB and PDB2 are high −34 dB
When Amplifier Disabled
PDB and PDB2 are low
dB
INPUT AND OUTPUT CHARACTERISTICS
Input Common-Mode Range 1.3 3.5 V
Input Resistance
Differential 100 Ω
Single-Ended 91.7 Ω
Common-Mode Rejection Ratio (CMRR) 47 dB
Output Common-Mode Range VCOM and VCOM2 2.0 3.0 V
VCOM and VCOM2 Input Impedance 2.5 kΩ
Output, Common Mode Referenced to VCOM (VS/2)
Offset −30 ±10 +30 mV
Drift TA = −40°C to +85°C 0.15 mV/°C
Output, Differential Offset
Voltage −10 ±1.5 +10 mV
Drift
T
A
= −40°C to +85°C
µV/°C
Output Resistance (Differential) 14.0 Ω
Maximum Output Voltage Swing 1 dB compression point 6.5 V p-p
POWER INTERFACE
Supply Voltage 4.75 5 5.25 V
Digital Input Voltage PDB, PDB2
Logic High (VIH) 2.1 3.45 V
Logic Low (VIL) 0 1.0 V
PDB Input Current PDB = 3 V −7 µA
PDB = 0 V −70 µA
Supply Current (ISUPPLY) Each amplifier
Quiescent, Each Amplifier PDB is high 86 mA
Disabled (Powered Down), Each Amplifier PDB is low 8 mA
ADL5569 Data Sheet
Rev. C | Page 4 of 23
Parameter Test Conditions/Comments Min Typ Max Unit
NOISE/HARMONIC PERFORMANCE
100 MHz
Second Harmonic Distortion (HD2) −89 dBc
Third Harmonic Distortion (HD3) −83 dBc
Output Third-Order Intercept (OIP3)
dBm
Third-Order Intermodulation Distortion (IMD3) −82 dBc
Output Second-Order Intercept (OIP2) 74 dBm
Second-Order Intermodulation Distortion (IMD2) −73 dBc
Output 1 dB Compression Point (OP1dB) 17.4 dBm
Noise Figure2 5.4 dB
Noise Spectral Density (NSD), RTI2 1.0 nV/√Hz
500 MHz
HD2 −78 dBc
HD3 −71 dBc
OIP3 41 dBm
IMD3 −80 dBc
OIP2 74 dBm
IMD2 −73 dBc
OP1dB 17.2 dBm
NF2 6.3 dB
NSD, RTI2 1.2 nV/√Hz
1000 MHz
HD2 −65 dBc
HD3 −58 dBc
OIP3 39 dBm
IMD3 −76 dBc
OIP2 71 dBm
IMD2 −70 dBc
OP1dB 17.7 dBm
NF2 7.0 dB
NSD, RTI2 1.3 nV/√Hz
2000 MHz
HD2
dBc
HD3 −52 dBc
OIP3 34 dBm
IMD3 −65 dBc
OIP2 63 dBm
IMD2 −62 dBc
OP1dB 17.4 dBm
NF2 9.3 dB
NSD, RTI2 1.8 nV/√Hz
3000 MHz
HD2 −62 dBc
HD3 −46 dBc
OIP3 30 dBm
IMD3 −58 dBc
OIP2 57 dBm
IMD2 −56 dBc
OP1dB 16.2 dBm
NF
2
dB
NSD, RTI2 2.2 nV/√Hz
Data Sheet ADL5569
Rev. C | Page 5 of 23
Parameter Test Conditions/Comments Min Typ Max Unit
4000 MHz
HD2 −58 dBc
HD3 −48 dBc
OIP3 25 dBm
IMD3
dBc
OIP2 59 dBm
IMD2 −58 dBc
OP1dB 14.3 dBm
NF2 12.1 dB
NSD, RTI2 2.5 nV/√Hz
1 S parameters are taken with the device under test (DUT) itself. The printed circuit board (PCB) is not used in the measurement.
2 NSD RTI is calculated from the noise figure, as follows:
NSD (RTI) = ½ ×
IN
NF
RkT ×−× 1)104
/10
(
where:
k is Boltzmann's constant, which equals 1.381 × 10−23J/K.
T is the standard absolute temperature for evaluating noise figure, which equals 290 K.
RIN is the differential input impedance of each amplifier, which equals 100 Ω.
ADL5569 Data Sheet
Rev. C | Page 6 of 23
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Output Voltage Swing × Bandwidth Product 5 V-GHz
Supply Voltage (V
S
) at VCC and VCC2
5.25 V
V I P, VIP2, VIN, and VIN2 VS + 0.5 V
PDB, PDB2 3.6 V
Maximum Output Current, IOUT (VIP, VIP2,
VIN, and VIN2 Pins)
±30 mA
Internal Power Dissipation 1 W
Maximum Junction Temperature
125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC
is the junction to case thermal resistance.
Table 3. Thermal Resistance
Package Type θJA1 θJC2 Unit
CP-16-44 90.5 20.9 °C/W
1 Measured on an Analog Devices evaluation board.
2 Based on simulation with JEDEC standard JESD51.
ESD CAUTION
Data Sheet ADL5569
Rev. C | Page 7 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15671-002
1
3
4
9
2
6
14
VIN
VIP
GND
VIP2
5
VIN2
VCC
15
VCOM
16
PDB
VON2
10 VOP2
11 GND
12 VOP
13 VON
PDB2
7
VCOM2
8
VCC2
ADL5569
TOP VIEW
(No t t o Scale)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS INTERNAL L Y
CONNECTED TO GND AND MUS T BE S OL DE RE D TO
A LOW IMPE DANCE GRO UND P LANE.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN Negative Side of Balanced Differential Inputs for Amplifier 1. This pin is biased to the VCC voltage (VVCC)/2, and is
typically ac-coupled.
2 VIP Positive Side of Balanced Differential Inputs for Amplifier 1. This pin is biased to VVCC/2, and is typically ac-coupled.
3, 11 GND Ground. Ground reference for the entire chip. These pins must be soldered to a low impedance ground plane.
4 VIP2 Positive Side of Balanced Differential Inputs for Amplifier 2. This pin is biased to the VCC2 voltage (VVCC2)/2 and is
typically ac-coupled.
5 VIN2 Negative Side of Balanced Differential Inputs for Amplifier 2. This pin is biased to VVCC2/2 and is typically ac-coupled.
6 PDB2 Power-Down Control (Active Low) for Amplifier 2. This pin is internally pulled up to approximately 2.8 V. A logic
high on this pin (2.1 V < PDB2 voltage (VPDB2) < 3.3 V) enables the device.
7 VCOM2 Common-Mode Voltage Input for Amplifier 2. A voltage applied to this pin sets the common-mode voltage of the
inputs and outputs of the amplifier. If left open, the VCOM2 voltage (VVCOM2) = VCC2/2. Decouple this pin to ground
with a 0.1 µF capacitor.
8 VCC2 Positive Supply for Amplifier 2.
9 VON2 Negative Side of Balanced Differential Outputs for Amplifier 2. This pin is biased to VVCOM2 and is typically ac-coupled.
10 VOP2 Positive Side of Balanced Differential Outputs for Amplifier 2. This pin is biased to VVCOM2 and is typically ac-coupled.
12 VOP Positive Side of Balanced Differential Outputs for Amplifier 1. This pin is biased to VVCOM and is typically ac-coupled.
13
VON
Negative Side of Balanced Differential Outputs for Amplifier 1. This pin is biased to V
VCOM
and is typically ac-coupled.
14 VCC Positive Supply for the Amplifier 1.
15 VCOM Common-Mode Voltage Input for Amplifier 1. A voltage applied to this pin sets the common-mode voltage of the
inputs and outputs of the amplifier. If left open, VVCOM = VVCC/2. Decouple this pin to ground with a 0.1 µF capacitor.
16 PDB Power-Down Control (Active Low) for Amplifier 1. This pin is internally pulled up to approximately 2.8 V. A logic
high on this pin (2.1 V < PDB voltage (VPDB) < 3.3 V) enables the device.
EPAD Exposed Pad. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane.
ADL5569 Data Sheet
Rev. C | Page 8 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, maximum gain, VCOM = VS/2, RS = 100 Ω differential, RL = 100 Ω differential, VOUT = 2 V p-p, frequency = 500 MHz, TA = 25°C,
parameters specified for differential input and differential output, and signal spacing = 2 MHz for two-tone measurements, unless
otherwise noted.
10M 100M 1G 10G
FRE Q UE NCY ( Hz )
21
20
19
18
17
16
15
14
13
12
11
GAI N (dB)
15671-003
Figure 3. Gain vs. Frequency (S Parameters Taken with DUT, PCB Not Used in
Measurement)
10M 10G
FRE Q UE NCY ( Hz )
20
18
16
14
12
10
8
6
4
2
0
GAI N (d B)
100M 1G
15671-004
–40°C
+25°C
+80°C
GAI N = 19dB
GAI N = 14dB
GAI N = 10dB
GAI N = 6dB
Figure 4. Gain vs. Frequency over Temperature
10M 100M 1G 10G
FRE Q UE NCY ( Hz )
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.25
–0.20
GAI N MIS M ATCH
CHANNEL A TO CHANNE L B (dB)
15671-005
Figure 5. Gain Mismatch (Channel A to Channel B) vs. Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
10M 100M 1G 6G
PHASE MISMATCH
CHANNEL A TO CHANNE L B (Degrees)
FREQUENCY ( Hz )
15671-006
Figure 6. Phase Mismatch (Channel A to Channel B) vs. Frequency
15671-007
6
8
10
12
14
16
18
20
01000 2000 3000 4000 5000 6000
FREQUENCY (MHz)
OUTPUT P 1dB (dBm)
–40°C
+25°C
+85°C
Figure 7. Output P1dB vs. Frequency over Temperature
16
0
4
2
6
10
14
8
12
0 6
NOISE FIGURE (dB)
FRE Q UE NCY ( GHz)
1 2 3 4 5
15671-008
Figure 8. Noise Figure vs. Frequency
Data Sheet ADL5569
Rev. C | Page 9 of 23
3.5
3.0
2.5
0
NOISE SPECRAL DENSITY, REFERRED
TO INPUT (nV/√Hz)
0.5
1.0
1.5
2.0
15671-009
0 6
FRE Q UE NCY ( GHz)
12345
Figure 9. Noise Spectral Density, Referred to Input vs. Frequency
60
–100
IM D3 AND OIP 3 ( dBc/ dBm)
–80
–60
–40
–20
0
20
40
OIP3
IMD3
15671-010
0 6
FRE Q UE NCY ( GHz)
12345
Figure 10. Third-Order Intermodulation Distortion (IMD3) and Output
Third-Order Intercept (OIP3) vs. Frequency
15671-211
50
0
OI P 3 ( dBm)
10
5
15
20
25
30
35
40
45
0 6
FREQUENCY ( GHz)
12345
+85°C
+25°C
–40°C
Figure 11. OIP3 vs. Frequency over Temperature
0
–90 0 6
IM D3 ( dBc)
FRE Q UE NCY ( GHz)
–80
–70
–60
–50
–40
–30
–20
–10
12345
+85°C
+25°C
–40°C
15671-012
Figure 12. IMD3 vs. Frequency over Temperature
–120
–100
–80
–60
–40
–20
0
0123456
IM D3 ( dBc)
FREQUENCY (GHz)
R
L
= 200Ω, 0.5V p -p
R
L
= 200Ω, 1V p-p
R
L
= 100Ω, 0.5V p -p
R
L
= 100Ω, 1V p-p
15671-213
Figure 13. IMD3 vs. Frequency over RLOAD for POUT per Tone
100
–100
–80
–60
–40
–20
0
20
40
60
80
IM D2 AND OIP 2 ( dBc/ dBm)
15671-014
0 6
FRE Q UE NCY ( GHz)
12345
OIP2
IMD2
Figure 14. Second-Order Intermodulation Distortion (IMD2) and Output
Second-Order Intercept (OIP2) vs. Frequency
ADL5569 Data Sheet
Rev. C | Page 10 of 23
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
HD2 (d Bc)
15671-015
0 6
FREQUENCY ( GHz)
12345
Figure 15. Second Harmonic Distortion (HD2) vs. Frequency
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
HD3 (d Bc)
15671-016
0 6
FREQUENCY ( GHz)
12345
Figure 16. Third Harmonic Distortion (HD3) vs. Frequency
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
HD2 (d Bc)
15671-017
0 6
FRE Q UE NCY ( GHz)
1 2 3 4 5
–40°C
+25°C
+85°C
Figure 17. HD2 vs. Frequency over Temperature
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
HD3 (d Bc)
15671-018
0 6
FRE Q UE NCY ( GHz)
12345
–40°C
+25°C
+85°C
Figure 18. HD3 vs. Frequency over Temperature
–110
–100
–90
–80
–70
–60
–50
–40
012345
HD2 (d Bc)
FREQUENCY (GHz)
HD2 AT 2V p-p
HD2 AT 1.5V p-p
HD2 AT 1V p-p
15671-219
Figure 19. HD2 vs. Frequency for Various Output Voltages Swings
–110
–100
–90
–80
–70
–60
–50
–40
012345
HD3 (d Bc)
FREQUENCY (GHz)
HD3 AT 2V p-p
HD3 AT 1.5V p-p
HD3 AT 1V p-p
15671-220
Figure 20. HD3 vs. Frequency for Various Voltages Swings
Data Sheet ADL5569
Rev. C | Page 11 of 23
–10
–100
–90
–80
–70
–60
–50
–40
–30
–20
HD2 AND HD3 (d Bc)
15671-021
2.0 3.0
VCOM (V)
2.2 2.4 2.6 2.8
225MHz
3000MHz
5900MHz
HD3
HD2
Figure 21. HD2 and HD3 vs. Output Common-Mode Voltage (VCOM)
0
–10
–90
–80
–70
–60
–50
–40
–30
–20
IM D3 ( dBc)
15671-022
2.0 3.0
VCOM (V)
2.2 2.4 2.6 2.8
1GHz
3GHz
6GHz
Figure 22. IMD3 vs. VCOM
0
–10
–90
–80
–70
–60
–50
–40
–30
–20
IM D3 ( dBc)
15671-023
0 6
FRE Q UE NCY ( GHz)
1 2 3 4 5
1V p-p PER TONE
0.5V p-p PER TONE
1.5V p-p PER TONE
Figure 23. IMD3 vs. Frequency at Various POUT per Tones
FREQUENCY (GHz)
–100
–80
–60
–40
–20
0
0123
4
HD2 AND HD3 (d Bc)
HD3
HD2 5.25V
5V
4.75V
15671-224
Figure 24. HD2 and HD3 vs. Frequency for Various Supplies
C4 500mV/di v
M1 250mV 4.0ns 50Ω B
W
8.0G A C4 840mV
M1
4
T
15671-025
Figure 25. Disable Time Response
–30
–40
–50
–60
–70
–80
–90 05.0
HD2 (d Bc)
FREQUENCY ( GHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
15671-026
Figure 26. HD2 vs. Frequency for a Single-Ended Input Circuit
ADL5569 Data Sheet
Rev. C | Page 12 of 23
–30
–40
–50
–60
–70
–80
–90 05.0
HD3 (d Bc)
FRE Q UE NCY ( GHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
15671-027
Figure 27. HD3 vs. Frequency for a Single-Ended Input Circuit
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0123456
IM D3 AND OIP 3 (dBc/dBm)
FRE Q UE NCY ( GHz)
IMD3
OIP3
15671-028
Figure 28. IMD3 and OIP3 vs. Frequency for a Single-Ended Input Circuit
C4 500mV/DIV
M1 250mV 4. 0ns 50Ω
BW
8.0G A C4 840mV
M1
4
T
15671-029
Figure 29. Enable Time Response
M1 600mV 4. 0ns A C1 –44.0mV
M1
T
15671-030
Figure 30. Large Signal Pulse Response, Output Voltage (VOUT) = 4 V p-p
FREQUENCY (Hz)
10M 100M 1G 6G
0
10
20
30
40
50
60
70
CMRR (dB)
15671-231
Figure 31. Common-Mode Rejection Ratio (CMRR) vs. Frequency
1000
006.0
GRO UP DE LAY ( ps)
FRE Q UE NCY ( GHz)
100
200
300
400
500
600
700
800
900
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
500MHz, 439p s
1.0G Hz , 442p s
1.5G Hz , 448p s
3.0G Hz , 456p s
15671-032
Figure 32. Group Delay vs. Frequency
Data Sheet ADL5569
Rev. C | Page 13 of 23
–24
–36 100M10M 1G 10G
REVERSE ISOLATION (d B)
FRE Q UE NCY ( Hz )
–34
–32
–30
–28
–26
15671-033
Figure 33. Reverse Isolation (SDD12) vs. Frequency
15671-034
00
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
8GHz
4GHz
3GHz
2GHz
10MHz
Figure 34. Differential Input Reflection Coefficient (SDD11)
TEMPERATURE (°C)
–40 –20 020 40 808560
170
171
172
173
174
175
176
177
178
179
180
SUPPLY CURRENT (mA)
15671-235
Figure 35. Supply Current vs. Temperature
0
–20
–40
–60
CHANNEL TO CHANNEL ISOLATION (dB)
–80
–100
–120
10M 100M
FREQUENCY (Hz)
1G 10G
CHANNEL A TO CHANNEL B
CHANNEL B TO CHANNEL A
15671-036
Figure 36. Channel to Channel Isolation vs. Frequency
15671-035
00
5.0
–5.0
2.0
1.0
–1.0
–2.0
0.5
–0.5
0.2
–0.2
8GHz
4GHz
3GHz
1GHz
500MHz
2GHz
10MHz
Figure 37. Differential Output Reflection Coefficient (SDD22)
ADL5569 Data Sheet
Rev. C | Page 14 of 23
THEORY OF OPERATION
The ADL5569 is a high gain, fully differential, dual amplifier
and ADC driver that operates on a single power supply
voltage (VS) of 5 V. Internal resistors preset the gain to 20 dB,
and external resistors can be added to reduce this gain. The
−3 dB bandwidth is 6.5 GHz, and the device has a differential
input impedance of 100 Ω. The ADL5569 has a differential
output impedance of 14 Ω and an operating output common-
mode voltage range of 2.0 V to 3.0 V with a 5 V supply.
The ADL5569 is composed of a pair of fully differential amplifiers
with on-chip feedback and feedforward resistors. The gain is
fixed at 20 dB but can be reduced by adding two resistors in
series with the two inputs. The amplifier provides a high differ-
ential, open-loop gain and has an output common-mode circuit
that enables the user to change the output common-mode voltage
by applying a voltage to the VCOM or VCOM2 pin.
Each amplifier provides superior low distortion for frequencies
near dc to beyond 2000 MHz, with low noise and low power
consumption. This amplifier achieves an IMD3 of −82 dBc at
100 MHz, and −80 dBc IMD3 at 500 MHz for 2 V p-p operation.
In addition, the ADL5569 can deliver 5 V p-p operation under
heavy loads. The internal gain is set at 20 dB, and the device has
a noise figure of 9.3 dB at 2 GHz. When comparing noise figure
and distortion performance, this amplifier delivers the best in
category spurious-free dynamic range (SFDR).
The ADL5569 features flexible input and output coupling.
The device can be ac-coupled or dc-coupled. For dc coupling,
the output common-mode voltage can be adjusted (using the
VCOM and VCOM2 pins) from 2.5 V to 0.5 V for VS at 3.3 V
and ground at −2.0 V.
The distortion performance as a function of output common-
mode voltage is shown in Figure 21. Note that the VCOM and
VCOM2 pins set the common-mode voltage at the outputs of
the amplifier, the VOP, VOP2, VON, and VON2 pins, when
configured for ac-coupled applications.
For ac-coupled applications with series capacitors at the inputs,
as shown in Figure 38, the input common-mode level is set to
the same as the voltage at VCOM or VCOM2.
Due to the wide input common-mode voltage range, this device
can easily be dc-coupled to many types of mixers, demodulators,
and amplifiers. If the outputs are ac-coupled, no external VCOM
or VCOM2 voltage adjustment is required because the amplifier
output common-mode level is set to VS/2.
AC
½
ADL5569
½
R
S
½
R
S
0.1µF
0.1µF
50Ω
50Ω
500Ω
500Ω
+
–
R
L
0.1µF
0.1µF
15671-103
R
G
R
G
R
F
R
F
Figure 38. Basic Structure
Data Sheet ADL5569
Rev. C | Page 15 of 23
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 39 shows the basic connections for operating the ADL5569.
Apply 5 V to the VCC and VCC2 pins and decouple with 0.1 µF
and 10 µF surface-mount ceramic capacitors in parallel to ground.
Decouple the VCOM and VCOM2 pins (Pin 7 and Pin 15) using a
0.1 µF capacitor. The PDB and PDB2 pins (Pin 6 and Pin 16) are
tied to logic high, respectively, to enable each amplifier. A
differential signal is applied to Amplifier 1 through Pin 1 (VIN)
and Pin 2 (VIP) and to Amplifier 2 through Pin 4 (VIP2) and
Pin 5 (VIN2). Each amplifier has a gain of 20 dB.
The Amplifier 1 input pins, Pin 1 (VIN) and Pin 2 (VIP), and
the output pins, Pin 13 (VON) and Pin 12 (VOP), are biased by
applying a voltage to Pin 15 (VCOM). If VCOM is left open,
VCOM equals ½ of VS. The Amplifier 2 input pins, Pin 4 (VIP2)
and Pin 5 (VIN2), and the output pins, Pin 9 (VON2) and
Pin 10 (VOP2), are biased by applying a voltage to Pin 7 (VCOM2).
If VCOM2 is left open, VCOM2 equals ½ of VS.
The ADL5569 can be ac-coupled, as shown in Figure 39, or it
can be dc-coupled if within the specified input and output
common-mode voltage ranges. Pulling the PDB and
PDB2 pins low puts the ADL5569 in sleep mode, reducing the
current consumption to 16 mA at ambient temperature.
0.01µF BALANCED
LOAD
VIP
VIN
0.01µF
VOP
VCOM
VON
0.01µF
VCC2
21
18
18 18
17
2
1
PDB
PDB2
3.3V
0.01µF
0.01µF
3.3V
215
12
8
13
1
16
6
VCC
ADL5569
14
GND
GND
11 3
0.01µF 10µF
V
S
0.01µF
EXPOSED PAD
+
½
R
S
½
R
S
BALANCED
AC
0.01µF BALANCED
LOAD
VIP2
VIN2
0.01µF
VOP2
VCOM2
VON2
0.01µF
21
18
17
0.01µF
0.01µF
47
10
9
5
½
R
S
½
R
S
BALANCED
AC
15761-104
50Ω
R
G
500Ω
R
F
GM B
50Ω
R
G
500Ω
R
F
50Ω
R
G
500Ω
R
F
GM B
50Ω
R
G
500Ω
R
F
Figure 39. Basic Connections
ADL5569 Data Sheet
Rev. C | Page 16 of 23
INPUT AND OUTPUT INTERFACING
The ADL5569 can be configured as a differential input to
differential output driver, as shown in Figure 40. The 50 Ω
resistors, R1 and R2, combined with the input balun, provide a
50 Ω input match for the 100 Ω input impedance. The input
and output 0.1 µF capacitors isolate the VVCC/VVCC2 bias from
the source and balanced load. The load is 100 Ω to provide the
expected ac performance (see the Specifications section).
VS
0.1µF
0.1µF
1:1 BAL UN
AC
50Ω
R1
R2
½
ADL5569
½ RL
½ RL
50Ω
50Ω
0.1µF
0.1µF
15671-105
+
–
Figure 40. Differential Input to Differential Output Configuration
The differential gain of the ADL5569 is dependent on the source
impedance and load, as shown in Figure 41. Determine the
differential gain (AV) by
AV = 500/50 (1)
AC
½
ADL5569
½
R
S
½
R
S
0.1µF
0.1µF
R
G
50Ω
R
G
50Ω
R
F
500Ω
R
F
500Ω
R
L
0.1µF
0.1µF
+
–
15671-106
Figure 41. Differential Input Loading Circuit
Single-Ended Input to Differential Output
The ADL5569 can also be configured in a single-ended input to
differential output configuration, as shown in Figure 42. In
this configuration, the gain of the device is reduced due to the
application of the signal to only one side of the amplifier. The input
and output 0.1 µF capacitors isolate the VVCC/VVCC2 bias from the
source and the balanced load.
The single-ended circuit configuration can be accomplished in
three steps (see Figure 42), assuming a 50 Ω RS source. First,
calculate the input resistance (RIN) of the amplifier using the
following formula:
( )
1– 2
G
IN
F
GF
R
RR
RR
=


×+

(2)
where:
RG is the series resistance internal to the amplifier.
RF is feedback resistance internal to the amplifier.
Thus, RIN = 91.7 Ω.
The next step is to calculate the termination of Resistor R2 (see
Figure 42). Because source impedance (RS) must be equal to the
parallel equivalent resistance of R2 and RIN,
IN
S
IN
R2 R
RR2 R
×
=+
Thus,
R2 = RIN × RS/(RIN − RS) (3)
When RS = 50 Ω and RIN = 91.7 Ω, R2 = 109 Ω.
The last step is to calculate the gain path rebalancing resistor,
R1 (see Figure 42), by using the following formula:
S
S
R R2
R1 R R2
×
=+
(4)
Thus, R1 = 34.0 Ω.
AC
½
ADL5569
½
½
R
S
R
G
50Ω
R
G
50Ω
R
F
500Ω
R
F
500Ω
R
L
0.1µF
0.1µF R
L
R1
0.1µF
0.1µF
R2 +
–
15671-107
Figure 42. Single-Ended Input to Differential Output Configuration
See the AN-0990 Application Note, Terminating a Differential
Amplifier in Single-Ended Input Applications, for more information
on terminating single-ended inputs. The single-ended gain
configuration of the ADL5569 is dependent on the source
impedance and load, as shown in Figure 43.
AC
½
ADL5569
½
½
R
S
R
G
50Ω
R
G
50Ω
R
F
500Ω
R
F
500Ω
R
L
0.1µF
0.1µF R
L
R1
34.2Ω
0.1µF
0.1µF
R2
109Ω
+
–
15671-108
Figure 43. Single-Ended Input Loading Circuit
Data Sheet ADL5569
Rev. C | Page 17 of 23
Determine the single-ended gain (AV1) using the following two
equations:
IN
MATCH
IN
R2 R
RR2 R
×
=+
(5)
where RMATCH is the input resistance value that matches RS,
which is calculated as follows:
500
10
50
V1
MATCH S L
S MATCH L
S
S
A
RR
R2 R
R R2 R R
R R2
R R2
=
+
×× ×
+ +
×
+

+

(6)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0500 1000 1500 2000 2500 3000 3500 4000 4500
HD2 (d Bc)
FREQUENCY (MHz)
SINGLE-ENDED
DIFFERENTIAL
15671-244
Figure 44. HD2 for Single-Ended and Differential Configurations vs.
Frequency, VOUT = 2 V p-p
GAIN ADJUSTMENT AND INTERFACING
The effective gain of the ADL5569 can be reduced by adding
two resistors in series with the inputs to reduce the gain.
AC
½
ADL5569
½
RS
½
RS
0.1µF
0.1µF
50Ω
50Ω
500Ω
500Ω
RL
0.1µF
0.1µF
RSERIES
RSHUNT RSERIES
+
–
15671-110
Figure 45. Gain Adjustment Using a Series Resistor
To find series resistor (RSERIES) for a given AV gain and RL, use
the following equation:
RSERIES = (500/AV) − 50 (7)
The necessary shunt component (RSHUNT) to match the source
impedance, RS, is expressed as
1
11
2 100
SHUNT
S SERIES
R
RR
=
−×+
(8)
The shunt resistor values for multiple target voltage gains are
listed in Table 5. The source resistance and input impedance
need careful attention when using Equation 6. Consider the
input impedance of the ADL5569 and the reactance of the ac
coupling capacitors before assuming that the impedance and
reactance of the capacitors make a negligible contribution.
To calculate the AV for a given RSERIES, use the following
equation:
500
50
V
SERIES
AR

=

+

(9)
Note that Equation 9 only gives the absolute gain and does not
take into account that the circuit introduces a 180° phase shift.
To account for this phase shift, multiply the product of
Equation 9 by −1.
Table 5. Differential Gain Adjustment Using Series Resistor
RS (Ω) Target Voltage Gain (dB) RSERIES (Ω) RSHUNT (Ω)
50
6
169
56.2
50 7 147 57.6
50 8 124 59
50 9 105 59
50 10 88.7 60.4
50 11 73.2 63.4
50 12 60.4 64.9
50 13 48.7 66.5
50 14 37.4 69.8
50 15 28 73.2
50 16 19.6 78.7
50
17
12.1
84.5
50 18 5.23 90.9
100 6 169 130
100 7 147 133
100 8 124 140
100 9 105 147
100 10 88.7 158
100 11 73.2 169
100 12 60.4 182
100 13 48.7 205
100 14 37.4 232
100 15 28 280
100 16 19.6 357
100 17 12.1 511
100 18 5.23 1050
ADL5569 Data Sheet
Rev. C | Page 18 of 23
EFFECT OF LOAD CAPACITANCE
Load capacitance, including stray capacitance from PCB traces,
affects the bandwidth and flatness of the ADL5569 frequency
response, resulting in excessive peaking. It is recommended to
add 5 Ω external series resistors to each output to isolate the
load capacitance from the outputs and to effectively reduce
peaking. Respective frequency responses resulting from the
addition of a 0.5 pF to a 2.0 pF differential load capacitance
are shown in Figure 46.
25
20
15
10
5
0
–10
–5
GAI N (dB)
15671-046
10M 10G
FRE Q UE NCY ( Hz )
100M 1G
1.0pF
0.5pF
0pF
2.0pF
Figure 46. Frequency Response for Various Load Capacitances, RL = 100 Ω
GSPS ADC INTERFACING
A wideband data acquisition system using the ADL5569 together
with the AD9689, a dual 14-bit ADC, was developed and tested as
shown in Figure 49 for ac-coupled applications. The amplifier
output common-mode voltage is set to AVDD/2 with the voltage
divider formed by the two 10 kΩ resistors on the VCOM pin.
However, the VCOM pin can be left open (with a decoupling
capacitor as described in Table 4), because there is an internal
divider to pull the node to VCC/2 in such cases. The resistor
capacitor (RC) filter after the amplifier works with the pole formed
by the ADC input capacitance to attenuate the broadband noise
and out of band harmonics generated by the amplifier. The RC
filter also blocks sharp switching pulses, that is, charge injection
from the ADC internal sampling circuitry, from reaching the
amplifier outputs and creating nonlinear effects. An additional
band-pass filter, specific to the system rejection requirements,
is also needed in front of the ADL5569 amplifier to prevent
unwanted signals from compressing the amplifier as well as from
reaching the ADC. This filter is usually added during bench testing.
See the AN-835 Application Note, Understanding High Speed ADC
Testing and Evaluation, for additional testing information and
setups.
The signal-to-noise ratio (SNR) and SFDR with respect to full
scale (FS) of the ADC system, is shown in Figure 47 and Figure 48.
40
45
50
55
60
65
70
0500 1000 1500 2000 2500 3000
SNRFS (dBFS)
FREQUENCY (MHz)
AC-COUPLED
DC-COUPLED
15671-247
NOTE: ALL TESTING WAS DONE AT –3dBFS.
Figure 47. ADC System SNR Referred to Full Scale (SNRFS) vs. Frequency
15671-248
30
40
50
60
70
80
90
0500 1000 1500 2000 2500 3000
SF DR ( dBc)
FREQUENCY (MHz)
AC-COUPLED
DC-COUPLED
NOTE: ALL TESTING WAS DONE AT –3dBFS.
Figure 48. ADC System SFDR vs. Frequency
Data Sheet ADL5569
Rev. C | Page 19 of 23
ADL5569
AVDD 5.0V
AVDDx DRVDDx
30Ω
50Ω
50Ω
10kΩ VCOM
VIP VCC
PDB
EPAD
VIN
AVDD
5.0V 10kΩ 200Ω 0.35pF
ADC
INTERNAL
INPUT Z
AD9689
V
CM
30Ω
5Ω
5Ω
10Ω
10Ω
0.1µF
ANALOG
INPUT TCM2-43X+
INPUT
Z = 50Ω
0.1µF
0.1µF
0.1µF
50Ω
50Ω
5Ω 2.7nH
2.7nH
5Ω
15671-115
AVDD 3.3V
5.1nH
0.1µF
0.1µF
0.1µF
0.5pF 1pF
Figure 49. Wideband 3.2 GHz Bandwidth AC-Coupled ADC Interfacing Example: ADL5569 Driving the AD9689
Two tone intermodulation distortion performance (IMD2 and
IMD3) is shown in Figure 50. The relative pass-band frequency
response for this signal chain with a wideband antialiasing filter
is shown in Figure 51.
15671-250
–80
–75
–70
–65
–60
–55
–50
–45
–40
100 200 300 400 500 600 700 800 900 1000
IMD2 AND IM D3 LEVEL (d Bc)
FREQUENCY (MHz)
IMD2
IMD3 AC-COUPLED
DC-COUPLED
NOT E: ALL T EST ING W AS DONE AT – 9 dBF S FOR BOTH T ONES.
Figure 50. Measured Two Tone IMD2/IMD3 Performance
15671-114
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
10M 100M 1G 10G
FUNDAM E NTAL POW E R ( dBF S )
FREQUENCY (MHz)
AC-COUPLED
DC-COUPLED
NOTE: ALL TESTING WAS DONE AT –3dBFS.
Figure 51. Measured Relative Frequency Response
For dc applications, special requirements must be completed for
the ADL5569 to accommodate a dc signal and level shift the
amplifier to meet the common-mode voltage requirements of
the companion converter. Figure 52 shows a 1.5 GHz design
example of the ADL5569 using dual supplies of +3.3 V for the
VCC and VCC2 pins and −2.0 V for the ground and exposed
pad (EP) pins. By using these dual supplies, the internal logic of
the power-down pins of the device (PDB and PDB2) is also
level shifted to 1.0 V to enable the device.
The example shown in Figure 52 provides a single-ended input
design, with an input common-mode voltage of 0.0 V. The
output common-mode voltage is designed to accommodate
1.4 V to interface with the AD9689 analog inputs. The
VCOM pin cannot be regarded as high-Z for the purposes of a
voltage divider calculation for the 2 kΩ and 15.4 kΩ resistors.
The 1.5 GHz bandwidth limitation of this design is not due to
any of the passive components, but it is an inherent practical
limitation of the ADL5569 and AD9689/AD9208 combination.
ADL5569 Data Sheet
Rev. C | Page 20 of 23
15671-152
ADL5569
AVDD +3. 3V
DRVDD
2kΩ VCOM
VIP VCC
PDB VOP
VON
EPAD
VIN
AVDD +3. 3V 15.4kΩ 200Ω 0.35pF
ADC
INTERNAL
INPUT Z
AD9689
AND
AD9208
V
CM
ANALOG
INPUT
INPUT
Z = 50Ω
0.1µF
AVDD –2.0V
AVDD DVDD
180Ω
5Ω
5Ω
10Ω
10Ω
650Ω 750Ω
750Ω
33Ω
AVDD 3.3V
5.1nH
100Ω
650Ω
AVDD –2.0V
AVDD –2.0V AVDD –2. 0V
VIN = V IP = 0.0V
VCOM = + 1.4V
VOP = VON = +1.4
AVDD +3. 3V
AVDD +3. 3V
VIN+
VIN–
Figure 52. 1.5 GHz Bandwidth, DC-Coupled ADC Interfacing Example: ADL5569 Driving the AD9689 and AD9208
SOLDERING INFORMATION AND RECOMMENDED
LAND PATTERN
Figure 53 shows the recommended land pattern for the ADL5569.
The ADL5569 is contained in a 2.5 mm × 3 mm LFCSP, which
has an exposed ground pad (EPAD). This pad is internally
connected to the ground of the chip. To minimize thermal
impedance and ensure electrical performance, solder the pad to
the low impedance ground plane on the PCB. To further reduce
thermal impedance, it is recommended that the ground planes
on all layers under the pad be stitched together with vias.
For more information on land pattern design and layout, refer
to the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
The land pattern on the ADL5569-EVALZ provides a simulated
thermal resistance (θJA) of 90.5°C / W.
15671-117
Figure 53. Recommended Land Pattern
EVALUATION BOARD
Figure 54 shows the general block diagram of the ADL5569-
EVALZ evaluation board. The schematic of the ADL5569-
EVALZ is shown in Figure 55 and has several options. The
ADL5569-EVALZ is powered by a single 5 V supply. The power
supply is decoupled by 10 µF and 0.1 µF capacitors. On-board
regulators provide a 2.5 V common-mode voltage and 3 V logic
supply voltage to enable and disable the power-down feature.
Several termination options are also provided to allow the user
to terminate unused inputs and outputs of the amplifier for
single-ended applications.
For more evaluation board options on the ADL5569, contact
the Analog Devices sales.
0.1µF
0.1µF
VIN
VCOM
VIP
0.1µF
0.1µF
VS
0.1µF
ADL5569
AMPLIFIER 1
10µF
15671-116
SMA
SMA
SMA
SMA
0.01µF
Figure 54. General Block Diagram of the ADL5569-EVALZ Evaluation Board
Data Sheet ADL5569
Rev. C | Page 21 of 23
SINGLE-ENDE D CONFIG URAT ION TO DIFFERNTI AL , GAI N=18DB
CHANGE R1 = 0Ω, R 2= DNI, R3 = 100Ω. R4 = 25Ω
10µF
10µF
142-0701-851
AVDD_3P3V
VCOM
AVDD_3P3V
142-0701-851
0.1µF
0.1µF
5.1
142-0701-851
142-0701-851 0.001µF
142-0701-851
35.7kΩ
142-0701-851
0
10.7kΩ
35.7kΩ
35.7kΩ
35.7kΩ
DNI 10kΩ
10kΩ
10kΩ
16.9kΩ
4.7µF
AVDD_3P3V
0.001µF
4.7µF 4.7µF
33NH
3137-1-00-15-00-00-08-0
AVDD_3P3VAVDD_P5V
33NH
4.7µF
4.7µF
ADM7170ACPZ-5.0
4.7µF
TSW-102-08-G-S
DNI
5.1
120OHM AT 100MEGHZ
VCOM (2.5V)
10µF
4.99kΩ
4.99kΩ
0.01µF
AVDD_P5V
0.01µF
0.01µF
0.1µF
35.7kΩ
0.01µF
35.7kΩ
35.7kΩ
0.1µF
0
5.1
DNI
0
DNI
DNI
0.1µF
0
ADM7170ACPZ-5.0
0.1µF
0.01µF
5.1
142-0701-851
AVDD_3P3V
0.01µF
AVDD_3P3V
3137-1-00-15-00-00-08-0
3137-1-00-15-00-00-08-0
142-0701-851
0.01µF
DNI DNI
10kΩ
0.01µF
AVDD_P5V
0.01µF
DNI
ADL5569
1µF
1µF
35.7kΩ
0.01µF
VCOM
R1
R2
R3
R4
C2
C1
A1
3
11
PAD
16
6
14
8
15
7
1
5
2
4
13
9
12
10
R6
R7
R9
R10
R5
P1
1
2
3
C3
P2
1
2
3
C4
R8
C9
C10
R13
R14
R11 R12 R16R15
P3
1
2
E1
1 2
C8C7 C11
C6
C5
U1
5
PAD6
3
4
8
71
2
C12 C16 C20
C14
C24C18
E2
1 2
R17
R18
R21
C22
TP1
1
C15
C13
U2
5
PAD6
3
4
8
71
2
R20
R22
C17
R19
C19 C21
E3
1 2
C23 C25
TP2
1
R23
R25
C26
C27
R26
R24
R31
R27
R29
C28
R32
R30
R28
C29
J3
1
2 3 4 5
J4
1
2 3 4 5
J1
1
2 3 4 5
J2
1
2 3 4 5
J6 1
2345
J5 1
2345
J8
1
2345
J7
1
2345
TP3
1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
PAD
PDB1
VCOM1
VCC1
VON1
VOP1
GND
VOP2
VON2
VCC2
VCOM2
PDB2
VIN2
VIP2
GND
VIP1
VIN1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND
AGND
AGND AGND AGND
AGND
AGND EP
VIN
VIN
GND
EN
SS
SENSE
VOUT
VOUT
AGND
AGND
AGND
AGND AGND AGND
15671-118
Figure 55. ADL5569-EVALZ Evaluation Board Schematic
ADL5569 Data Sheet
Rev. C | Page 22 of 23
Table 6. Bill of Materials
Qty. Reference Designator Description Manufacturer Part Number
1 A1 IC, dual-channel amplifier Analog Devices ADL5569
10 C1 to C6, C8 to C11 0.01 µF capacitors, ceramic, X7R Murata GRM033R71A103KA01D
6 C12, C13, C16, C17, C20,
C21
4.7 µF capacitors, ceramic, X5R Murata GRM155R60J475ME87D
2 C14, C15 0.001 µF capacitors, ceramic, X7R Murata GRM033R71E102KA01D
2 C18, C19 1 µF capacitors, ceramic, X5R Taiyo Yuden AMK063ABJ105MP-F
6 C22, C23, C26 to C29 0.1 µF capacitors, ceramic, X5R Murata GRM033R60J104KE19D
2 C24, C25 10 µF capacitors, ceramic X5R Taiyo Yuden AMK105CBJ106MV-F
1 C7 10 µF capacitor ceramic, X5R Murata GRM21BR61C106KE15L
1
E1
120 Ω at 100 MHz, ferrite bead, 0.07 Ω, 1.5 A
Murata
BLM18SG121TN1D
2 E2, E3 33 nH, chip inductors, 0.06 Ω, 1.3 A Coilcraft, Inc. 0402AF-330XJL
8 J1 to J8 PCB SMA connectors, 50 Ω, end launch jack Cinch Connectivity Solutions 142-0701-851
2 P1, P2 Connector headers, straight, three position Samtec TSW-103-08-G-S
1 P3 Connector PCB header, two position Samtec TSW-102-08-G-S
8 R1 to R4, R23 to R26 35.7 kΩ resistors, precision thick film chip Panasonic ERJ-1GEF3572C
4 R13, R14, R29, R30 0 Ω resistors, 0201 Panasonic ERJ-1GE0R00C
1 R17 16.9 kΩ resistor, 0201 Panasonic ERJ-1GEF1692C
1 R19 10.7 kΩ resistor, 0402 Vishay Precision Group CRCW040210K7FKED
2 R21, R22 4.99 kΩ resistors, 0201 Samsung RC0603F4991CS
4 R5, R8, R18, R20 10 kΩ resistors, 0201 Panasonic ERJ-1GNF1002C
4 R6, R7, R9, R10 5.1 Ω resistors, 0201 Yageo RC0201JR-075R1L
3 TP1, TP2, TP3 Connector PCB pin test points Mill-Max 3137-1-00-15-00-00-08-0
2 U1, U2 IC ultralow noise, high PSRR, low dropout
(LDO) regulators
Analog Devices ADM7170ACPZ-5.0
15671-119
Figure 56. Layout of the ADL5569-EVALZ Evaluation Board, Top Layer
15671-120
Figure 57. Layout of the ADL5569-EVALZ Evaluation Board, Bottom Layer
Data Sheet ADL5569
Rev. C | Page 23 of 23
OUTLINE DIMENSIONS
1
BOTTOM VIEW
TOP VIEW
SIDE VIEW
16
6
8
9
13 14
5
2.60
2.50
2.40
3.10
3.00
2.90
0.60
0.55
0.50 0. 05 MAX
0.02 NO M
0.15 REF
COPLANARITY
0.08
PIN 1
INDICATOR
11-01-2018-A
PKG-005452
EXPOSED
PAD
SEATING
PLANE
0.30
0.25
0.18
0.45
0.40
0.35
0.50
BSC
1.40
1.30
1.20
0.40
0.30
0.20
0.45 REF
0.70 REF
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
Figure 58. 16-Lead Lead Frame Chip Scale Package [LFCSP]
2.5 mm × 3 mm Body and 0.55 mm Package Height
(CP-16-44)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADL5569BCPZ −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-44 ET
ADL5569BCPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-44 ET
ADL5569-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15671-0-11/18(C)