ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 1 -
GENERAL DESCRIP TIO N
The AK5386 is a stereo A/D Converter with wide sampling rate of 8kHz ∼ 216kHz and is su itable fo r
consumer to professional audi o system. The AK5386 achieves high accuracy and low cost by using
Enhanced dua l bit ∆Σ techniques. The AK5 386 requires no exte rnal co mpone nt s beca use th e analog
inputs are single-ende d. The au dio int erface has two fo rmats (MSB just ified, I2S) and ca n co rrespon d to
various systems like DVD Recorder, AV Receiver, PC Sound card and Music Instrument recording.
FEATURES
Single-ended Input
Digital HPF for DC-Offse t ca n cel
S/(N+D): 96 dB
DR: 110 dB
S/N: 110dB
Linear Phase Digital Anti-Alias Filtering
Passband: 0 ∼ 21.768kHz (@ fs=48kHz)
Passband Ripple: ±0.005dB
Stopband Attenuation: 80dB
Master Clock: 512fs/768fs (Normal Speed)
256fs/384fs (Double Speed)
128fs/192fs (Quad Speed)
Sampling Frequency:
Normal Speed: 8kHz ∼ 54kHz (512fs)
8kHz ∼ 48kHz (768fs)
Double Speed: 54k Hz ∼ 108kHz (25 6 fs)
48kHz ∼ 96 kHz ( 384 fs)
Quad Speed: 108kHz ∼ 216k Hz ( 128 fs)
96kHz ∼ 19 2kHz (192 fs)
Master / Slave Mode
Audio Interface: 24bit MSB justified / I2S se le ctabl e
Input level: CMOS
Power Supply:
Analog: 4.5 ∼ 5.5V
Digital: 2.7 ∼ 3.6V (Norma l Spee d)
3.0
∼ 3.6V (Double Speed, Quad Speed)
Ta = −40 ∼ 85°C
Small 16pin TSSOP Package
AK5357 /5 8/ 59/81 Pin-compatible
Si ng l e-ended 24-Bit 192kHz ∆Σ ADC
AK5386
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 2 -
∆Σ
Modulator
MCLK
A
INL LRCK
SCLK
SDTO
DIF
VCOM
Clock Divid er
A
INR
A
GNDV
A
Decimation
Filter
Serial I/O
Interface
Vol tag e Re ference
CKS1
DGNDVD
CKS2
∆Σ
Modulator Decimation
Filter
PDN
CKS0
Bl ock Di a g r a m
Compatibility with AK5357, AK5358, AK5359, AK5381 and AK5386
AK5357 AK5358 AK5381 AK5359 AK5386
fs 4kHz to 96kHz 8kHz to 96kHz 4kHz to 96kHz 8kHz to 216kHz 8kHz to 216kHz
S/(N+D) 88dB 92dB 96dB 94dB 96dB
DR 102dB 102dB 106dB 102dB 110dB
MCLK @ 48kHz 256/512/384/768fs 256/512/384/768fs 256/512/384/768fs 256/512/384/768fs 512/768fs
VIH @ TTL Level
Mode 2.2V 2.2V 2.4V Not Available Not Available
VA(Analog Supply) 2.7 to 5.5V 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V 4.5 to 5.5V
2.7 to 5.5V 2.7 to 3.6V
VD (Digital Supply) 2.7 to 5.5V 2.7 to 5.5V 3.0 t o 5. 5 V@
fs=96kHz 2.7 to 5.5V 3.0 to 3.6V @
fs=96k, 192kHz
HPF Disable Available Not Available Available Available Available
Operating
Temperature
ET: −20∼+85°C
VT: −40∼+85°C ET: −20∼+85°CET:
−20∼+85°C
VT: −40∼+85°C
XT: −40∼+85°C
ET: −20∼+85°C
VT: −40∼+85°C VT: −40∼+85°C
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 3 -
Ordering Guide
AK5386VT −40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD5386 Evaluation Board for AK5386
Pin Layo ut
CKS1
VCOM
VD
DGND
AINR
AINL
AGND
VA
Top View
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
DIF
PDN
LRCK
MCLK
SCLK
CKS2
CKS0
SDTO
PIN / FUNCTION
No. Pin Name I/O Function
1 AINR I Rch Analog Input Pin
2 AINL I Lch Analog Input Pin
3 CKS1 I Mode Select 1 Pin
4 VCOM O Com mon Voltage Output Pin, VA/2
Bias voltage of ADC input.
5 AGND - Analog Ground Pin
6 VA - Analog Power Supply Pin, 5V
7 VD - Digital Power Suppl y Pin, 3.3V
8 DGND - Digital Ground Pin
9 SDTO O Audio Serial Data Output Pin
“L” Output at Power-down mode.
10 LRCK I/O Output Chan nel Clock Pin
“L” Output in Master Mode at Power-down mode.
11 MCLK I Master Clock In put Pin
12 SCLK I/O Audio Se rial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
13 PDN I Power Down & Reset Mode Pi n
“H”: Power up, “L”: Power down & Reset
The AK5386 must be reset once upon power-up.
14 DIF I Audio Interface Format Pin
“H”: 24bit I2S Compatible, “L”: 24bit MSB justified
15 CKS2 I Mode Select 2 Pin
16 CKS0 I Mode Select 0 Pin
Note: Do not allow all digital input pins except for analog input pins (AINL and AINR pins) to float.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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H a ndl ing of U nuse d Pin
The unused i nput pins should be processed appropriatel y as below.
Classification Pin Name Setting
AINL This pin should be open.
Analog AINR This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter Symbol min max Units
Power Su p p l i e s:
(Note 2) Analog
Digital VA
VD −0.3
−0.3 6.0
6.0 V
V
Input Curr ent, Any Pin Except Supplies IIN - ±10 mA
Analog Input Voltage (AINL, AINR, CKS1 pins) VINA −0.3 VA+0.3 V
Digital I nput Voltage (Note 3) VIND −0.3 VD+0.3 V
Ambi ent T emper a t u r e (power ed app l ied ) Ta -4 0 8 5 °C
Storage Tem perature Tstg −65 150 °C
Note 1. All voltages with r espect to ground.
Note 2. AGND and DGND must be conn ected to the sa me analog ground plan e.
Note 3. DIF, PDN, SCLK, MC LK, LRCK, CKS0 and CKS2 pins
WARNING: Operation at or beyond these limits ma y result in permanent damage to the device.
Norma l operation is not guaranteed at these extremes.
RECOMMENDED OPERAT I NG CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter Symbol min typ max Units
Power Su p p l i e s
(Note 4)
Analog
Digita l: Norm al Speed
Double/Quad Speed
VA
VD
VD
4.5
2.7
3.0
5.0
3.3
3.3
5.5
3.6
3.6
V
V
V
Note 4. The power up sequence between VA and VD is n ot critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in t his da tasheet.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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ANAL O G CHARACTERISTICS
(Ta=25°C; VA =5.0V, VD=3.3V; AGND=DGN D= 0V; fs=48kHz, 96kHz, 192kHz; SCLK=64fs; Signal
Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz,
40Hz ∼ 40kHz at fs=192kHz; unless ot herwise specified)
Parameter min typ max Units
ADC Analog Input Char a ct er i stic s:
Resolution 24 Bits
Input Voltage (Note 5) 2.7 3.0 3.3 Vpp
fs=48kHz −1dBFS 86 96 - dB
BW= 20kHz −60dBFS - 47 - dB
fs=96kHz −1dBFS 86 92 - dB
BW= 40kHz −60dBFS - 42 - dB
fs=192kHz −1dBFS - 90 - dB
S/(N+D)
BW= 40kHz −60dBFS - 42 - dB
DR (−60dBFS with A-weighted) 102 110 - dB
S/N (A-weighted) 102 110 - dB
Input Resistance 4 6 - kΩ
Interchannel Isolat ion 95 115 - dB
Interchannel Gain Mismatch - 0.1 0.5 dB
Gain Drift - 100 - ppm/°C
Power Supply Rejection (Note 6) - 50 - dB
Power Supplies
Power Supply Curren t
Norm al Operation (PDN pin = “H”)
VA
VD (fs=48kHz)
VD (fs=96kHz)
VD (fs=192kHz)
Power down mode (PDN pin = “L”) (Note 7)
VA+VD
-
-
-
-
-
20
7
10
10
10
30
11
15
15
100
mA
mA
mA
mA
µA
Note 5. Th is val ue is the ful l scale (0dB) of the in put vol tag e. Input voltage is pr oporti on al to VA vol tage.
Vin = 0.6 x VA (Vpp).
Note 6. PSR is applied to VA and VD wit h 1kHz , 50mVpp.
Note 7. All digital input pins are held VD or DGND.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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FILTER CHARACTE RIST ICS (fs=48kHz)
(Ta=−40 ∼ 85°C; VA = 4.5 ∼ 5. 5 V; VD =2 . 7 ∼ 3.6V)
Parameter Symbol min typ max Units
ADC Dig ita l Filt e r (De ci mati on LPF):
Passband (Note 8)
±0.02dB
−0.1dB
−0.2dB
−3.0dB
PB
0
-
-
-
-
221.
22.3
23.5
21.768
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 26.5 - - kHz
Passband Ripple PR - - ±0.005 dB
Stopband Attenuation SA 80 - - dB
Gr oup Dela y Dist or t ion ∆GD - 0 - µs
Group Delay (Note 9) GD - 29.4 - 1/fs
ADC Dig it al Fil te r ( HP F):
Frequency Response (Note 8)
−3dB
−0.1dB FR
-
- 1.0
6.5 -
- Hz
Hz
FILTER CHARACTE R IST ICS (fs=9 6 kHz)
(Ta=−40 ∼ 85°C; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
ADC Dig ita l Filt e r (De ci mati on LPF):
Passband (Note 8)
±0.02dB
−0.1dB
−0.2dB
−3.0dB
PB
0
-
-
-
-
44.3
44.6
47.0
43.536
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 53.0 - - kHz
Passband Ripple PR - - ±0.005 dB
Stopband Attenuation SA 80 - - dB
Gr oup Del ay Dis t or ti on ∆GD - 0 - µs
Group Delay (Note 9) GD - 29.4 - 1/fs
ADC Dig it al Fil te r ( HP F):
Frequency Response (Note 8)
−3dB
−0.1dB FR
-
- 2.0
13.0 -
- Hz
Hz
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 7 -
FILTER CHARACTE RI STI CS (fs=1 92k Hz)
(Ta=−40 ∼ 85°C; VA = 4.5 ∼ 5. 5 V; VD =3 . 0 ∼ 3.6V)
Parameter Symbol min typ max Units
ADC Dig ita l Filt e r (De ci mati on LPF):
Passband (Not e 8)
±0.1dB
−0.2dB
−3.0dB
PB
0
-
-
-
52.9
90.1
43.8
-
-
kHz
kHz
kHz
Stopband SB 112 - - kHz
Passband Ripple PR - - ±0.005 dB
Stopband Attenuation SA 72 - - dB
Gr oup Dela y Dist or t ion ∆GD - 0 - µs
Group Delay (Note 9) GD - 16.5 - 1/fs
ADC Dig it al Fil te r ( HP F):
Frequency Response (Note 8)
−3dB
−0.1dB FR
-
- 4.0
26.0 -
- Hz
Hz
Note 8. The passband and stopband frequencies scale with fs. For example, PB (±0.02dB ) at fs = 48k H z is 0 .4535 × fs. The
reference frequency of these resp onse is 1kHz.
Note 9. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting
of 24bi t data both channels to the ADC output register for ADC.
DC CHARACTERIST ICS
(Ta=−40 ∼ 85°C; VA = 4.5 ∼ 5. 5 V; VD =2 . 7 ∼ 3.6V at Normal Speed, VD=3.0 ∼ 3.6V at Double/Quad Spee d)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 70%VD
- -
- -
30%VD V
V
High-Level Output Voltage (Iout=−1mA)
Low-Level Output Voltage (Iout=1mA) VOH
VOL VD−0.5
- -
- -
0.5 V
V
Input Leakage Cur r ent Iin - - ±10 µA
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 8 -
SWITCHING CHARACTERIS TICS (Normal Speed)
(Ta=−40 ∼ 85°C; VA= 4. 5 ∼ 5.5V; VD=2.7 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency: 512fs
768fs
Pulse Width Low
Pulse Width High
fCLK
fCLK
tCLKL
tCLKH
4.096
6.144
0.4/fCLK
0.4/fCLK
-
-
-
-
27.648
36.864
-
-
MHz
MHz
ns
ns
LRCK
Frequency: 512fs
768fs fs
fs 8
8 -
- 54
48 kHz
kHz
Duty Cycle
Sl a ve mode
Master mode
45
- -
50 55
- %
%
Audio Interface Timing
Slave mode
SCLK Peri od
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SC LK “↑” (Note 10)
SCLK “ ↑” to LRCK Edge (Note 10)
LRCK to SDTO (MSB) (Except I2S m od e)
SCLK “↓” to SDTO
tSCK
tSCKL
tSCKH
tLRSH
tSHLR
tLRS
tSSD
1/128fs
60
60
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
40
40
ns
ns
ns
ns
ns
ns
ns
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
fSCK
dSCK
tMSLR
tSSD
-
-
−20
−20
64fs
50
-
-
-
-
40
40
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (Note 11)
PDN “↑” to SDTO valid at Slave Mode (Note 12)
PDN “↑” to SDTO valid at Master Mode (Note 12)
tPD
tPDV
tPDV
150
-
-
-
4132
4129
-
-
-
ns
1/fs
1/fs
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 9 -
SWITCHING CHARACTERISTI CS (Doubl e / Quad Speed)
(Ta=−40 ∼ 85°C; VA= 4. 5 ∼ 5.5V; VD=3.0 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency: 128fs, 256fs
192fs, 384fs
Pulse Width Low
Pulse Width High
fCLK
fCLK
tCLKL
tCLKH
13.824
18.432
0.4/fCLK
0.4/fCLK
-
-
-
-
27.648
36.864
-
-
MHz
MHz
ns
ns
LRCK
Double Speed:256fs fs 54 - 108 kHz
384fs fs 48 - 96 kHz
Quad Speed: 128fs fs 108 - 216 kHz
Frequency:
192fs fs 96 - 192 kHz
Duty Cycle
Slave mode
Master m ode
45
- -
50 55
- %
%
Audio Interface Timing
Slave mode
SCLK Period: Double Speed
Quad Speed
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SC LK “↑” (Note 10)
SCLK “ ↑” to LRCK Edge (Note 10)
LRCK to SDTO (MSB) (Except I2S m od e)
SCLK “↓” to SDTO
tSCK
tSCK
tSCKL
tSCKH
tLRSH
tSHLR
tLRS
tSSD
1/128fs
1/64fs
33
33
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Master mode
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
fSCK
dSCK
tMSLR
tSSD
-
-
−20
−20
64fs
50
-
-
-
-
20
20
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (Note 11)
PDN “↑” to SDTO valid at Slave Mode (Note 12)
PDN “↑” to SDTO valid at Master Mode (Note 12)
tPD
tPDV
tPDV
150
-
-
-
4132
4129
-
-
-
ns
1/fs
1/fs
Note 10. SCLK r isi n g edge must n ot occu r at t he sa m e time a s LRCK edg e.
Note 11. The AK5386 can be reset by bringing the PDN pin = “L”
Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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Timing Diagram
1/fCLK
MCLK
tCLKH tCLKL
VIH
VIL
1/fs
LRCK VIH
VIL
tSCK
SCLK
tSCKH tSCKL
VIH
VIL
Clock Tim ing
LRCK VIH
VIL
tSHLR
SCLK VIH
VIL
tLRS
SDTO 50%VD
tLRSH
tSSD
Audio Interface Tim i ng (Slave mode)
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 11 -
LRCK
SCLK 50%VD
SDTO 50%VD
tSSD
tMSLR dSCK
50%VD
Audio Int erface Ti min g (Master mode)
PDN VIH
VIL
tPDV
SDTO 50%VD
tPD
Power Down & Reset Timi ng
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 12 -
OPERATION OVERVIEW
Syste m Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized wi th
MCLK, however th e phase is not critical. Table 1 shows the relationship of typical sampling frequen cy and the system
clo ck f requenc y . MC LK f re quenc y , SCL K f re quenc y , H PF (O N or OFF) and maste r/slave are se lec ted b y CKS 2-0 pins as
shown in Table 3. When MCLK is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the A K5 386 may draw e x c e s s curre nt due to i ts use o f inte rnal dynamica lly re f res hed lo gi c. If the exte rnal clo c ks are not
present, place the AK5386 in power-down mode (PDN pin = “L”). In master mode, the master cl ock (MCLK) must be
provided un less PDN pin = “L”.
MCLK
fs 128fs 192fs 256fs 384fs 512fs 768fs
32kHz N/A N/A N/A N/A 16.384MHz 24.576MHz
44.1kHz N/A N/A N/A N/A 22.5792MHz 33.8688MHz
48kHz N/A N/A N/A N/A 24.576MHz 36.864MHz
96kHz N/A N/A 24.576MHz 36.864MHz N/A N/A
192kHz 24.576MHz 36.864MHz N/A N/A N/A N/A
Table 1. System Clock Example
Mode Sampling Frequency MCLK
8kHz ≤ fs ≤ 54kHz 512fs
Normal Speed 8kHz ≤ fs ≤ 48kHz 768fs
54kHz < fs ≤ 108kHz 256fs
Double Speed 48kHz < fs ≤ 96kHz 384fs
108kHz < fs ≤ 216kHz 128fs
Quad Speed 96kHz < fs ≤ 192kHz 192fs
Table 2. Sampl ing Frequency Range
CKS2 pin CKS1 pin CKS0 pin HPF Master/Slave MCLK SCLK
L L L ON Slave
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
≥ 48fs or 32f s
(Note 13)
L L H OFF Slave
128/192fs (Quad Speed)
256/384fs (Double Speed)
512/768fs (Normal Speed)
≥ 48fs or 32f s
(Note 13)
L H L ON Master 256fs (Double Speed) 64fs
L H H ON Master 512fs (Normal Speed) 64fs
H L L ON Master 128fs (Quad Speed) 64fs
H L H ON Master 192fs (Quad Speed) 64fs
H H L ON Master 384fs (Double Speed) 64fs
H H H ON Master 768fs (Normal Speed) 64fs
Table 3. Mode Select
Note 13. SDTO outputs 16bit data at SCLK=32fs.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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Audio Interface Format
Two kinds of data formats can be ch osen with th e DIF pin (Ta ble 4). In both modes, the serial data is in MSB first, 2’s
compleme nt format. The SDTO is clocked out on the falling edge o f SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode DIF pin SDTO LRCK SCLK Figure
0 L 24bit, MSB justified H/L ≥ 48fs or 32fs Fi gu r e 1
1 H 24bit, I2S Compatible L/H ≥ 48fs or 32fs Fi gu re 2
Table 4. Audio Interface Format
LRCK
SCLK(64fs)
SDTO(o)
0
23 22
12
4 0
20 21 24 31 0 12
23 22 0
10
23
2220 21 31
23:MSB, 0:LSB
Lch Data Rch Data
24
321
22 23 23
1234
Figure 1. Mode 0 Timing
LRCK
SCLK(64fs)
SDTO(o)
0
23 22
12
4 0
2521 24 0 12
23 22 0
1022 2521 24
321
22 23 23
1234
3
23:MSB, 0:LSB
Lch Data Rch Data
Figure 2. Mode 1 Timing
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz)
and scales with sampling rate (fs).
HPF is contr olled by CKS2-0 pin s (Table 3). If HPF settin g (ON/OFF) is chan g ed at oper atin g, click noise occur s by
chan gin g DC offset. It is recommended t hat HPF settin g is chan g ed at PDN pin = “L”.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
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Power down
The AK5386 is placed i n t h e power-d own mode by brin g ing PDN pi n “L” an d the d ig it al fil t er is al so reset a t th e sam e
time. This reset should alw ays be done after po wer-up. In the powe r-down mode, the VCOM are AGND level. An analog
ini tia l iz a t ion cycle st a r ts aft er exi tin g th e power - down mode. T h erefor e, t h e outp u t d a ta S DT O becomes a vai l a ble a fter
4129 cycles of LR C K c lo c k in mas ter mode o r 4132 cycles o f LR CK c loc k in slave mo de . During initialization, the ADC
digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data
correspondin g to the input signals after the end of initialization (Settling approximately takes the group delay time).
Normal Operation
Internal
State
PDN
Power-down Initialize Normal Operation
(1)
Idle Noise
GD GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(2)
(3)
(4)
“0”data Idle Noise
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output c orresponding to analog input has t he group delay ( GD).
(3) A/D outputs “0” data at the power-down state.
(4) W hen the e xte rnal clocks (M CL K , S CL K and L RCK ) a re s to pp e d, the A K5 386 should b e in the power-do w n st ate.
Fi gure 3. Power-d own/ u p sequen ce exam p le
System Reset
Th e AK5386 should be r eset on ce by brin ging PDN pin “L” after power-up. In slave mode, the inter nal tim ing starts
clockin g by the rising edg e (falling edge at mode 1) of LRCK after exiti ng from reset and power down state by MC LK.
The AK5 386 is po w er dow n state until LRCK i s input. In master mode , the internal timing starts w he n MCL K is input.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 15 -
SYSTEM DESIGN
Figure 4 show s the sy stem conne ction diagram. An evaluation board is available which demonstrates applicatio n circuits,
the optimum layout, power supply arrangements and measurement results.
AK5386
8
7
6
3
2
1
9
10
11
12
13
14
15
16
AINL
VCOM
AGND
DGND
AINR
SDTO
LRCK
MCLK
SCLK
PDN
+0.1u
CKS1
VA
VD
Analog 5V
DIF
CKS2
CKS0
10u
10u
0.1u
Reset
5
4
Audio
Controller
Mode
Control
+
2.2u
An alog Gro und System G r ound
Lch I n
Rc h I n
Dig ital 3.3V
Notes:
- A GND and D G ND o f the AK 5386 shoul d b e distribute d s e parately fro m the gro u nd of ex ternal digital de vic e s
(MPU, DSP etc.).
- All digital in put pin s should not be left floating.
- The CKS1 pin should be connected to VA or AGND.
Figure 4. Typical Connection Diagram
Analog Ground Digital Ground
System
Controller
A
INR1
A
INL2
CKS13
VCOM4
A
GND5
V
A
6
VD7
DGND8
16
15
14
13
12
11
10
9
CKS0
CKS2
DIF
PDN
SCLK
MCLK
LRCK
SDTO
AK5386
Figure 5. Groun d Layout
Note: AGND and DGND must be connected to the same analog ground pl ane.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 16 -
1. Grounding and Power Supply Decoupling
The AK5386 requires care ful attentio n to po w er supply and grounding arrange ments. To minimize co upl ing fro m digital
noise, decoupling capa citors should be connected to VA and VD respectively. VA is supplied from the analog supply in
the system, and VD is supplied from the digital supply in the system. The power up sequen ce is not critical between VA
and VD . AGND and DGND of the AK5386 must be connected to one analog ground plane. Syst e m analo g
ground and digital ground should be con n ected together near t o where the supplies are brought onto the prin ted circuit
boa rd. Decoup ling cap acitors should be as near to the AK5386 as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference
The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND w ith a 0.1µF
ceramic capacitor. A capaci tor 2.2µF at ta ched t o VCOM pin eliminates the effects of high freq uency noise. No load
current may b e draw n fro m thes e pins. All signals, es pec ially clo cks , s hould b e ke pt aw ay from the VA and VCO M pins
in order to avoid unwanted coupling into th e AK5386.
3. Analog Inputs
The ADC inputs are single-ended and inter nally biased to the common voltage (50%VA) with 6kΩ (typ, @fs=48kHz,
96kHz, 19 2kHz) res is tance . The input sig nal range s c ale s with the s upp ly voltage and nominally 0.6xV A Vp p (typ). The
ADC output d ata form at is 2’s complement. The internal HPF removes the DC offset.
The AK5386 samples t he analog in puts at 128fs (@ fs=48kHz), 64fs (@ fs=96kHz) or 32fs(@ fs=192kHz). The digital
fil ter rejects noise above the stop band except for multiples of 64fs or 32fs. The AK5386 includes an anti-alia sing filter
(RC filter) to attenu ate a noise ar ound 128fs, 64fs or 32fs.
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 17 -
PACKAGE
0.1±0.1
0
∼
10°
Detail A
Seating Plane 0.10
0.17
±
0.05
0.22±0.1 0.65
5.0 1.10max
A
18
916
16
p
in TSSO P
(
Unit: mm
)
4.4
6.4±0.2
0.5±0.2
Materi al & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame sur face treatment: Solder (Pb free) p la te
ASAHI KASEI [AK5 386 ]
MS0579-E-00 2006/12
- 18 -
MARKING
AKM
5386VT
XXYYY
1) Pin #1 in dication
2) Date Code: XXYYY (5 digit s )
XX: Lot#
YYY: Date Code
3) Marketing Code: 5386VT
Revisi on History
Date (YY/MM /DD) Revision Reason Page Contents
06/12/13 00 First Edition
I MP O RTA NT NO T I CE
• Th ese pr oduc ts and the ir spec if i cat i ons are s ubj ect t o cha nge w it hou t no ti ce. B ef ore cons id eri ng
any use o r ap pl ic ati on , co nsu lt th e Asahi Ka sei Mi cr osyst em s Co. , Ltd . ( AK M) sa le s o f f ic e or
aut hor iz ed di str i but or conc ern in g t hei r c urr ent sta tu s.
• AKM assum e s no l iab i lity for i nfringement of any p at e nt , in t ell ec t u al pr o pe rt y , or ot h er r i gh t in t h e
appl ication or use of an y inf ormation contained herein.
• Any exp ort of t he se pro duc ts, or d ev i ces or system s con tai nin g them , m ay requi re a n ex por t
license or other off i ci al approv al under the law and regulations of the count ry of export pertaining
to custom s and tariff s, currency ex change, or strategic material s.
• AKM prod uc ts are neithe r inten de d no r auth orize d for us e as critical componen ts in any sa fety, life
supp ort, or ot her haz ar d re lat ed dev i ce or sy stem , and AKM assu me s no r espon si bi l it y rel at i ng t o
any such use, ex cept with the express writ ten consent of the Representativ e Director of AKM. As
used here:
a. A hazard related device or system is one designed or intended for life support or maintenance
of safe ty or for applica tions in medicine , aero sp ace, nu clear ene rgy, or other fields , in whic h its
failure to f unction or perform m ay reasonably be ex pected to result in loss of lif e or in
signi ficant injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be ex pected
to result, whether directly or i ndirectly, i n the loss of the safety or eff ect iv eness of the dev ice
or system co ntai ni ng it , and whic h m ust t here f ore m eet v ery hig h stand ards of pe rf orm anc e
and rel iability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
oth er wise pl ac e s the pr od uc t with a t h i r d pa r t y t o no t i fy t h at pa r t y i n ad vance of t he ab ove co nt e nt
a nd con dition s , an d the buy er or dis tr ibu tor ag ree s to assume an y an d a ll resp on s ibility and lia bility
f or a nd h old AK M h arm l ess f r om any and a ll clai m s ari si ng f r om th e use o f sai d p roduc t i n th e
abse nce of such notification.
