©2012 Integrated Device Technology, Inc.
SEPTEMBER 2012
DSC 2738/17
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
12L
A
0L
2738 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/W
L
SEM
L
INT
L
M/S
BUSY
R
I/O
0R
-I/O
7R
A
12R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
13
13
IDT7005S/LHIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Features
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
◆Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆Interrupt Flag
◆On-chip port arbitration logic
◆Full on-chip hardware support of semaphore signaling
between ports
◆Fully asynchronous operation from either port
◆Devices are capable of withstanding greater than 2001V
electrostatic discharge
◆Battery backup operation—2V data retention
◆TTL-compatible, single 5V (±10%) power supply
◆Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
thin quad flatpack
◆Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆Green parts available, see ordering information
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
2
Description
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power. Low-power (L) versions
offer battery backup data retention capability with typical power consump-
tion of 500µW from a 2V battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military
grade product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML making it ideally suited to military temperature applica-
tions demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2738 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
987 6543 2168676665
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
V
CC
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
GND
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R/W
L
11
10
M/S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
GND
I/O
0R
V
CC
A
4R
BUSY
L
GND
BUSY
R
INT
R
A
12R
I/O
7R
N/C
GND
OE
R
R/W
R
SEM
R
CE
R
OE
L
SEM
L
CE
L
N/C
I/O
0L
I/O
1L
IDT7005J or F
J68-1
(4)
F68-1
(4)
68 Pin PLCC / FLATPACK
Top View
(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N/C
A
12L
N/C
A
11R
N/C
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
,
11/16/01
INDEX
7005PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
GND
M/S
OE
L
A
5L
I/O
1L
R/W
L
CE
L
SEM
L
V
CC
N/C
N/C
OE
R
CE
R
R/W
R
SEM
R
A
12R
GND
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6L
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
I/O
0L
2738 drw 03
.
11/16/01
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
3
Pin Names
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18in x 1.18in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
Pin Configurations(1,2,3) (con't.)
2738 drw 04
51 50 48 46 44 42 40 38 36
53
55
57
59
61
63
65
67
68
66
1357911 13 15
20
22
24
26
28
30
32
35
ABCDEFGH JK L
47 45 43 41 34
21
23
25
27
29
31
33
2 4 6 8 10 12 14 16
18 19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49 39 37
A
5L
INT
L
N/C
SEM
L
CE
L
V
CC
OE
L
R/W
L
I/O
0L
N/C
GND GND
I/O
0R
V
CC
N/C
OE
R
R/W
R
SEM
R
CE
R
GND BUSY
R
BUSY
L
M/SINT
R
N/C
GND
A
1R
N/C
N/C
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
IDT7005G
G68-1(4)
68-Pin PGA
Top View(5)
,
11/19/01
Left Port Right Port Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
12L
A
0R
- A
12R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
2738 tbl 01
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
4
Truth Table I: Non-Contention Read/Write Control
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage(1,2)
Absolute Maximum Ratings(1)
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Truth Table II: Semaphore Read/Write Control(1)
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2 Industrial temperature: for specific speeds, packages and powers contact
your sales office.
NOTE:
1. A0L – A12L is not equal to A0R – A12R
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10%
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. These parameters are determined by device characterization but are not
production tested (TQFP Package only).
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Inputs
(1)
Outputs
Mode
CE
R/W
OE SEM
I/O
0-7
H X X H High-Z Deselected: Power-Down
LLXHDATA
IN
Write to Memory
LHLHDATA
OUT
Read Memory
X X H X High-Z Outputs Disabled
2738 tbl 02
Inputs
(1)
Outputs
Mode
CE
R/W
OE SEM
I/O
0-7
HHL LDATA
OUT
Read in Semaphore Flag Data Out
H↑XLDATA
IN
Write I/Oo into Semaphore Flag
LXXL
____
Not Allowed
2738 tbl 03
Symbol Rating
Commercial
& Industrial Military Unit
V
TE RM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature Under
Bias
-55 to +125 -65 to +135 oC
T
STG
Storage
Temperature
-65 to +150 -65 to +150 oC
I
OUT
DC Output Current 50 50 mA
2738 tbl 04
Grade Ambient
Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5.0V
+
10%
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
COV 5.0V
+
10%
2738 tbl 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(2)
V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
2738 tbl 06
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Output Capacitance V
OUT
= 3dV 10 pF
2738 tbl 07
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Data Retention Waveform
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
NOTES:
1. TA = +25°C, VCC = 2V, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
DATA RETENTION MODE
V
CC
CE
2738 drw 05
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
V
DR
2V
>
Symbol Parameter Test Conditions
7005S 7005L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Output Leakage Current CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2738 tbl 08
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
for Data Retention V
CC
= 2V 2.0
___ ___
V
I
CCDR
Data Retention Current CE > V
HC
V
IN
> V
HC
or < V
LC
Mil. & Ind.
___
100 4000 µA
Com'l.
___
100 1500
t
CDR
(3)
Chip Deselect to Data Retention Time SEM > V
HC
0
___ ___
ns
t
R
(3)
Operation Recovery Time t
RC
(2)
___ ___
ns
2738 t bl 09
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 5V, TA = +25°C and are not production tested. ICC DC = 120mA (typ)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the port opposite port "A".
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating Current
(Bo th Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L
170
160
310
260
170
160
310
260
160
150
290
240
155
145
265
220
mA
MIL &
IND
S
L
____
____
____
____
____
____
____
____
160
150
370
320
155
145
340
280
I
SB1
Standby Current
(Bo th Ports - TTL
Level Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L
20
10
60
60
20
10
60
50
20
10
60
50
16
10
60
50
mA
MIL &
IND
S
L
____
____
____
____
____
____
____
____
20
10
90
70
16
10
80
65
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L
105
95
190
160
105
95
190
160
95
85
180
150
90
80
170
140
mA
MIL &
IND
S
L
____
____
____
____
____
____
____
____
95
85
240
210
90
80
215
180
I
SB3
Full Standby Current (Both
Po rts - All CMOS Level
Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
MIL &
IND
S
L
____
____
____
____
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L
100
90
170
140
100
90
170
140
90
80
155
130
85
75
145
120
mA
MIL &
IND
S
L
____
____
____
____
____
____
____
____
90
80
225
200
85
75
200
170
2738 tbl 10
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military
Only
Symbol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2 )
Max. Unit
I
CC
Dynamic Operating
Current
(Bo th Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L
150
140
250
210
150
140
250
210
____
____
____
____
mA
MIL &
IND
S
L
150
140
300
250
150
140
300
250
140
130
300
250
I
SB1
Standby Current
(Bo th Ports - TTL
Level Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L
13
10
60
50
13
10
60
50
____
____
____
____
mA
MIL &
IND
S
L
13
10
80
65
13
10
80
65
10
8
80
65
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L
85
75
155
130
85
75
155
130
____
____
____
____
mA
MIL &
IND
S
L
85
75
190
160
85
75
190
160
80
70
190
160
I
SB3
Full Standby Current
(Bo th Ports - All
CMOS Level Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
____
____
____
____
mA
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L
80
70
135
110
80
70
135
110
____
____
____
____
mA
MIL &
IND
S
L
80
70
175
150
80
70
175
150
75
65
175
150
2738 tb l 11
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
7
AC Test Conditions
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Figure 1. AC Output Test Load Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
1250Ω
30pF
775Ω
DATA
OUT
BUSY
INT
5V 5V
1250Ω
5pF*
775Ω
DATA
OUT
2738 drw 06
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2738 tbl 12
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
17
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
17
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
17
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2,5)
0
____
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
15
____
17
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM) 10
____
10
____
10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
17
____
20
____
25 ns
2738 tbl 13a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
IDT7005X70
Military
Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
70
____
ns
t
AA
Address Access Time
____
35
____
55
____
70 ns
t
ACE
Chip Enable Access Time
(3)
____
35
____
55
____
70 ns
t
AOE
Output Enable Access Time
____
20
____
30
____
35 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
PU
Chip Enab le to Power Up Time
(2,5)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
35
____
50
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM) 15
____
15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55
____
70 ns
2738 tbl 13b
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
t
RC
R/W
CE
ADDR
t
AA
(4)
OE
2738 drw 07
t
ACE
(4)
t
AOE
(4)
t
LZ
(1)
t
OH
t
HZ
(2)
t
BDD
(3,4)
DATA
OUT
BUSY
OUT
VALID DATA
(4)
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
2738 drw 08
t
PU
I
CC
I
SB
t
PD
,
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
9
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
Symbol Parameter
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
17
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write 12
____
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
12
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
12
____
15 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
____
12
____
15 ns
t
OW
Output Active from End-of-Write
(1,2,4)
0
____
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window 5
____
5
____
5
____
5
____
ns
2738 tbl 14a
Symbol Parameter
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military Only
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
t
WC
Write Cycle Time 35
____
55
____
70
____
ns
t
EW
Chip Enable to End-of-Write
(3)
30
____
45
____
50
____
ns
t
AW
Address Valid to End-of-Write 30
____
45
____
50
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 25
____
40
____
50
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
30
____
40
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25
____
30 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
15
____
25
____
30 ns
t
OW
Output Active from End-of-Write
(1, 2,4 )
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window 5
____
5
____
5
____
ns
2738 tbl 14b
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
CE
or
SEM
(9)
R/W
t
WC
t
HZ
(7)
t
AW
t
WR
(3)
t
AS
(6)
t
WP
(2)
DATA
OUT
t
WZ
(7)
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(4) (4)
2738 drw 09
2738 drw 10
tWC
tAS
(6)
tWR
(3)
tDW tDH
ADDRESS
DATAIN
CE or SEM
(9)
R/W
tAW
tEW
(2)
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
SEM
2738 drw 11
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
VALID ADDRESS
DATA
IN
VALID DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
t
ACE
SEM
"A"
2738 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE “A”
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE “B”
(2)
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
12
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
17
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
17
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
15
____
17
____
20
____
20 ns
t
BDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17
____
17 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
18
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
30
____
45
____
50 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
25
____
35
____
35 ns
2738 tbl 15a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind &
Military
7005X70
Military
Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40
____
40 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
40
____
40 ns
t
BDC
BUSY Access Time from Chip Enable High
____
20
____
35
____
35 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Date
(3)
____
35
____
40
____
45 ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
25
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
____
95 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
____
80 ns
2738 tbl 15b
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13
2738 drw 13
t
DW
t
APS
(1)
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
Timing Waveform of Write with Port-to-Port Read with BUSY(2,5)
(M/S = VIH)(4)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version..
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
Timing Waveform of Write with BUSY
2738 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
(3)
R/W
"B"
t
WH
(1)
(2)
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
14
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
NOTES:
1. 'X' in part number indicates power rating (S or L).
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
2738 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
(2)
t
BAC
t
BDC
2738 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
(2)
t
BAA
t
BDA
MATCHING ADDRESS "N"
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
INS
Inte rrupt Set Time
____
15
____
15
____
20
____
20 ns
t
INR
Inte rrupt Reset Time
____
15
____
15
____
20
____
20 ns
2738 tbl 16a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military
Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Inte rrupt Set Time
____
25
____
40
____
50 ns
t
INR
Inte rrupt Reset Time
____
25
____
40
____
50 ns
2738 tbl 16b
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
15
Waveform of Interrupt Timing(1)
Truth Table III — Interrupt Flag(1,4)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
2738 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
(2)
CE
"A"
R/W
"A"
t
AS
(3)
t
WC
t
WR
(4)
t
INS
(3)
INT
"B"
2738 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
(2)
CE
"B"
OE
"B"
t
AS(3)
t
RC
t
INR(3)
INT
"B"
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
12L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
12R
-A
0R
INT
R
LLX1FFFXXXX X L
(2)
Set Right INT
R
Flag
XXXXXXLL1FFFH
(3)
Reset Right INT
R
Flag
XXX X L
(3)
L L X 1FFE X Set Left INT
L
Flag
XLL1FFEH
(2)
X X X X X Reset Left INT
L
Flag
2738 tbl 17
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
16
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are
push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functional Description
The IDT7005 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7005 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX), where a write is defined as CE = R/W= VIL per Truth Table III.
The left port clears the interrupt through access of address location 1FFE
when CE = OE = VIL. For this example, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes to
memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the
right port must read the memory location 1FFF. The message (8 bits) at
1FFE or 1FFF is user-defined, since it is an addressable SRAM location.
If the interrupt function is not used, address locations 1FFE and 1FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table III for the interrupt operation.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
12L
A
OR
-A
12R
BUSY
L
(1)
BUSY
R
(1 )
X X NO MATCH H H Normal
HXMATCHHHNormal
XHMATCHHHNormal
L L MATCH (2) (2) Write Inhibit
(3)
2 738 tbl 18
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2738 tbl 19
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
17
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 7005 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7005 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT7005 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration on a master is based on the chip enable and
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to observe
this timing can result in a glitched internal write inhibit signal and corrupted
data in the slave.
Semaphores
The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7005 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7005's hardware semaphores,
which provide a lockout mechanism without requiring complex program-
ming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
2738 drw 19
MASTER
Dual Port
RAM
BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (R)
CE
BUSY (L)
BUSY (R)
DECODER
BUSY (L) BUSY (L)
BUSY (L) BUSY (L)
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
18
cause either signal (SEM or OE) to go inactive or the output will
never change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests arrive
at the same time, the assignment will be arbitrarily made to one port or
the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT7005’s Dual-Port RAM. Say the 8K x 8 RAM
was to be divided into two 4K x 8 blocks which were to be dedicated at any
one time to servicing either the left or right port. Semaphore 0 could be used
to indicate the side which would control the lower section of memory, and
configurations. The IDT7005 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7005 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location,that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
19
Semaphore 1 could be defined as the indicator for the upper section of
memory.
To take a resource, in this example the lower 4K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 4K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 4K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
Figure 4. IDT7005 Semaphore Logic
D
0
2738 drw 20
DQ
WRITE
D
0D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ
SEMAPHORE
READ
,
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
20
Ordering Information
NOTES:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
Datasheet Document History
12/21/98: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 & 3 Added additional notes to pin configurations
06/03/99: Changed drawing format
11/10/99: Replaced IDT logos
08/07/00: Page 1 Added copywright info
Fixed overbar errors
Page 4 Increated storage temperature parameter
Clarified TA Parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±500mV to 0mV in notes
09/18/01: Page 2 & 3 Added date revision for pin configurations
Page 14 Replaced one copy of table 13b with 13a for 15, 17,20 & 25ns speeds for AC Electrical Characteristics
INTERRUPT TIMING
2738 drw 21
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38538 QML
PF
G
J
F
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
68-pin Flatpack (F64-1)
15
17
20
25
35
55
70
Commercial Only
Commercial Only
Commercial, Industrial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
Military Only
S
L
Standard Power
Low Power
XXXXX
Device
Type
64K (8K x 8) Dual-Port RAM7005
Speed in nanoseconds
A
GGreen
(2)
A
Blank
8
Tube or Tray
Tape and Reel
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
21
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History (continued)
01/31/06: Page 1 Added green availability to features
Page 20 Added green indicator to ordering information
10/21/08: Page 20 Removed "IDT" from orderable part number
09/17/12: Pages 6,7,9,12,& 14 In all of the DC & AC Electrical tables the 7005X20 speed grade
changed from 7005X20 Com'l & Military to include Ind making it
Com'l, Ind & Military
Page 20 Added T& R indicator to ordering information
