AS1153, AS1157
Dual LVDS Receiver
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Datasheet
1 General Description
The AS1153, AS1157 are dual flow-through L VDS (low-voltage differ-
ential signaling) receivers which accept LVDS differential inputs and
convert them to LVCMOS outputs. The receivers are perfect for low-
power low-noise applications requiring high signaling rates and
reduced EMI emissions.
The devices are guaranteed to receive data at speeds up to
260Mbps (130MHz) over controlled impedance media of approxi-
mately 100Ω. Supported transmission media are PCB traces, back-
planes, and cables.
The AS1153, AS1157 features integrated parallel termination resis-
tors (nominally 107Ω), which eliminate the requirement for discrete
termination resistors, and reduce stub lengths. The AS1153, AS1 157
uses high impedance inputs and requires an external termination
resistor when used in a point-to-point connection.
The integrated Failsafe feature sets the output high if the inputs are
open, undriven and terminated, or undriven and shorted.
All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-
through pinout simplifies PC board layout and reduces crosstalk by
separating the LVDS inputs and LVCMOS outputs.
The devices are available in a 8-pin SOIC package.
Figure 1. AS1153, AS1157 - Block Diagram
2 Key Features
Flow-Through Pinout
Guaranteed 260Mbps Data Rate
300ps Pulse Skew (Max)
Conform to ANSI TIA/EIA-644 LVDS Standards
Single +3.3V Supply
Operating Temperature Range: -40°C to +85ºC
Failsafe Circuit
Integrated Termination (AS1157)
8-pin SOIC Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/
Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/
Routers, Backplane Interconnect, Clock Distribution Computers,
Intelligent Instruments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Battery-Powered
Equipment.
AS1153/57
IN1-
IN1+
IN2+
IN2-
VCC
OUT1
OUT2
GND
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AS1153, AS1157
Datasheet - Pinout and Packaging
4 Pinout and Packaging
Pin Assignments
Figure 2. Pin Assignments (Top Vie w)
Pin Descriptions
Table 1. Pin Descriptions
Pin Number Pin Name Description
1IN1-
Inverting Differential Receiver Input
2IN1+
Noninverting Differential Receiver Input
3IN2+
Noninverting Differential Receiver Input
4IN2-
Inverting Differential Receiver Input
5GND
Ground
6OUT2
LVCMOS/LVTTL Receiver Output
7OUT1
LVCMOS/LVTTL Receiver Output
8VCC
Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.
VCC
OUT1
OUT2
GND
IN1-
IN1+
IN2+
IN2-
AS1153/57
1
2
3
4
8
7
6
5
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AS1153, AS1157
Datashee t - A b s o l u t e M a x i mu m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Min Max Units Comments
Electrical Parameters
VCC to GND -0.3 5.0 V
INx+, INx- to GND -0.3 5.0 V
OUTx+, OUTx- to GND -0.3 Vcc + 0.3 V
Electrostatic Discharge
Electrostatic Discharge HBM +/- 4 kV Norm: MIL 883 E method 3015, INx+, INx-
Temperature Ranges and Storage Conditions
Thermal Resistance ΘJA 128 ºC/W Typical 4-layer application
Junction Temperature +150 ºC
Storage Temperature Range -55 +125 ºC
Package Body Temperature +260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Humidity non-condensing 5 85 %
Moisture Sensitive Level 1 Represents a max. floor life time of unlimited
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AS1153, AS1157
Datasheet - Electrical Characteristics
6 Electrical Characteristics
DC Electrical Characteristics
VCC = +3.0 to +3.6V, Differential Input Voltage |VID| = +0.1 to +1.0V, Common-Mode Voltage VCM = |VID/2| to
2.4V - |VID/2|,TAMB = -40°C to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified).
Table 3. DC Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
Operating Temperature Range TAMB -40 +85 °C
LVDS Inputs (INx+, INx-)
Differential Input High
Threshold VTH 100 mV
Differential Input Low
Threshold VTL -100 mV
Input Current1
(AS1153)
1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH,
VTL, and VID.
IINx+, IINx-0.1V ≤ |VID| ≤ 0.6V -20 20 µA
0.6V ≤ |VID| ≤ 1.0V -25 25 µA
Differential Input Resistance
(AS1157) RDIFF VCC = 3.6V or 0, Figure 18 on page 9 90 107 132 Ω
Differential Input Resistance
(AS1153) RDIFF2
2. 2xRIN = RDIFF
VCC = 3.6V or 0, Figure 18 on page 9 40 100 kΩ
LVCMOS/LVTTL Outputs (OUTx)
Output High Voltage
(Table 5) VOH
IOH = -4.0mA
(AS1153)
Open, undriven short, or undriven 100Ω
parallel termination 2.7 3.2
V
VID = +100mV 2.7 3.2
IOH = -4.0mA
(AS1157)Open or undriven short 2.7 3.2
VID = +100mV 2.7 3.2
Output Low Voltage VOL IOL = +4.0mA, VID = -100mV 0.1 0.25 V
Output Short-Circuit
Current3
3. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note: All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality
Control) methods.
IOS VID = 100mV, VOUTx = 0 15 mA
Supply
Supply Current ICC Inputs open 0.6 2 mA
|VID| = 200mV 4.5 8 mA
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AS1153, AS1157
Datasheet - Electrical Characteristics
AC Electrical Characteristics
VCC = +3.0 to +3.6V, CLOAD = 10pF, Differential Input V oltage |VID| = 0.2 to 1.0V, Common-Mode V oltage VCM = |VID/2| to 2.4V -|VID/2|, Input Rise
and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V,
TAMB = +25ºC (unless othe rwise specified). 1, 2
Notes:
1. AC parameters are guaranteed by design and characterization.
2. CL includes scope probe and test jig capacitance.
3. tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
4. tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device.
5. tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same
VCC and within 5ºC of each other.
6. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
7. fMAX generator output conditions:
a. Rise time = fall time = 1ns (0 to 100%)
b. 50% duty cycle
c. VOH = +1.3V
d. VOL = +1.1V
8. Output criteria:
a. Duty cycle = 60% to 40%
b. VOL = 0.4V (max)
c. VOH = 2.7V (min)
d. Load = 10pF
Table 4. AC Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
Differential Propagation Delay High-to-Low tPHLD Figure 20 on page 11 and Figure 21 on
page 12 11.83.1ns
Differential Propagation Delay Low-to-High tPLHD Figure 20 on page 11 and Figure 21 on
page 12 11.83.1ns
Differential Pulse Skew
(tPHLD - tPLHD) 3tSKD1 Figure 20 on page 11 and Figure 21 on
page 12 250 600 ps
Differential Channel-to-Channel Skew 4tSKD2 Figure 20 on page 11 and Figure 21 on
page 12 600 ps
Differential Part-to-Part Skew 5tSKD3 Figure 20 on page 1 1 and Figure21 on
page 12 0.8 ns
Differential Part-to-Part Skew 6tSKD4 Figure 20 on page 1 1 and Figure21 on
page 12 1.5 ns
Rise Time tTLH Figure 20 on page 11 and Figure 21 on
page 12 0.4 1.0 ns
Fall Time tTHL Figure 20 on page 11 and Figure 21 on
page 12 0.4 1.0 ns
Maximum Operating Frequency 7, 8 fMAX All Channels Switching 130 160 MHz
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AS1153, AS1157
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
VCC = +3.3V, VCM = +1 .2V, |VID| = 0.2V, CLOAD = 10pF, TAMB = +25ºC, unless otherwise noted.
Figure 3. Supply Current vs. Frequency Figure 4. Supply Current vs. Temperature
Figure 5. Diff. Threshold Voltage vs. VCC Figure 6. Output Short-Circuit Current vs. VCC
Figure 7. Output Low Voltage vs. VCC Figure 8. Output High Voltage vs. VCC
0
5
10
15
20
-45 -30 -15 0 15 30 45 60 75 90
Temperature(°C)
Supply Cur r ent (mA) .
0
10
20
30
40
50
0 50 100 150 200 250 300
F r equenc y (MHz)
Supply Cur r ent (mA) .
All Channels Switching
One Channel Switching
f = 100MHz
f = 1MHz
Low to High
High to Low
0
5
10
15
20
25
30
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
Dif ferential Output V oltage (mV ) .
0
20
40
60
80
100
120
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age( V)
O utput S hor t Cir c uit Curr ent ( m A )
.
VTH
VTL
2.7
2.8
2.9
3
3.1
3.2
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age ( V)
Output Voltage (V ) .
72
72,5
73
73,5
74
74,5
75
3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Volt age ( V)
O utput V oltage (m V ) .
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AS1153, AS1157
Datasheet - Typical Operating Characteristics
Figure 9. Differential Propagation Delay vs. VCC Figure 10.
Differential Propagation Delay vs. Temp.
Figure 11. Differential Propagation Delay vs. VCM Figure 12. Differential Propagation Delay vs. VID
Figure 13. Differential Propagation Delay vs. Load
1.75
1.8
1.85
1.9
1.95
2
2.05
-45 -30 -15 0 15 30 45 60 75 90
Temperature(°C)
Dif f. P r opagation Delay ( ns ) .
1.7
1.74
1.78
1.82
1.86
1.9
1.94
3 3.1 3.2 3.3 3.4 3.5 3.6
S upply Volt age( V)
Dif f. P r opagation Delay ( ns ) .
tPHLD
tPLHD tPHLD
tPLHD
0.75
1
1.25
1.5
1.75
2
2.25
0.1 0.5 0.9 1.3 1.7 2.1 2.5
Dif ferential-Input Volt age( V)
Dif f. P r opagation Delay ( ns ) .
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
00.511.522.5
Common-Mode Volt age( V)
Dif f. P r opagation Delay ( ns ) .
tPHLD
tPLHD
tPHLD
tPLHD
0
0.5
1
1.5
2
2.5
3
10 15 20 25 30 35 40 45 50
Capacitive Load (pF)
Dif f. P r opagat ion Delay ( ns ) .
tPHLD
tPLHD
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AS1153, AS1157
Datasheet - Typical Operating Characteristics
Figure 14. Differential Pulse Skew vs. VCC Figure 15. Transition Time vs. Capacitive Load
Figure 16. Transition Time vs. VCC Figure 17. Transition Time vs. Temperature
400
600
800
1000
1200
1400
1600
10 15 20 25 30 35 40 45 50
Capacitive Load ( pF )
T r ans ition Tim e ( ps ) .
tTHL
tTLH
0
50
100
150
200
250
300
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age( V)
Dif ferential Puls e S kew ( ps ) .
300
325
350
375
400
425
450
475
-45 -30 -15 0 15 30 45 60 75 90
Temperature(°C)
T r ans ition Tim e ( ps ) .
340
350
360
370
380
390
400
3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Volt age( V)
T r ans ition Tim e ( ps ) .
tTLH
tTHL
tTHL
tTLH
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AS1153, AS1157
Datasheet - Detailed Description
8 Detailed Description
The AS1153, AS1157 are 260Mbps, dual-channel LVDS receivers intended for high-speed, point-to-point, low-power applications. Each inde-
pendent channel accepts and converts an LVDS input to an LVTTL/LVCMOS output. The devices are capable of detecting differential signals
from 100mV to 1V within an input voltage range of 0 to 2.4V.
The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input voltage range, a ±1V volt-
age shift in the signal relative to the receiver is allowed. Thus, a difference in ground references of the transmitter and the receiver, as well as the
common mode effect of coupled noise, can be tolerated.
LVDS Interface
The L VDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by
the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication stan-
dards, resulting in higher data rates, reduced power consumption and EMI emissions, and less susceptibility to noise.
The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground.
The AS1157 has an integrated termination resistors connected internally across each receiver input. This internal termination saves board
space, eases layout, and reduces stub length compared to an external termination resistor . In other words, the transmission line is terminated on
the IC.
Failsafe Circuit
The devices contain an integrated Failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or undriven and shorted.
Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are high impedance. A short
condition also can occur because of a cable failure. The Failsafe circuit of the AS1153, AS1157 automatically sets the output high if any of these
conditions are true.
The Failsafe input circuit (see Figure 18) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). If the input is driven
to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the Failsafe circuit is not activated. If the
inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the Failsafe
circuit pulls both inputs above VCC - 0.3V, activating the Failsafe circuit and thus forcing the device output high.
Figure 18. Failsafe Input Circuit
VCC - 0.3V
RIN2
RIN1
RIN1
RDIFF
AS1157
VCC - 0.3V
RIN2
RIN1
RIN1
AS1153
INx-
OUTx
INx+
INx-
OUTx
INx+
VCC VCC
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AS1153, AS1157
Datasheet - Applications
9 Applications
Figure 19. Typical Application Circuit
Power-Supply Bypassing
To bypa ss VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the
smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1153, AS1157.
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor must also be matched to
this characteristic impedance.
Eliminate reflections and ensure that noise couples as common mode by running differential traces close together.
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data recovery of the devices.
Route each channel’s dif ferential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a
constant distance between the differential traces to avoid irregularities in differential impedance.
Avoid 90° turns (use two 45° turns).
Minimize the number of vias to further prevent impedance irregularities.
Table 5. Function Table
Input Output
INx+INx-OUTx
VID ≥ +100mV H
VID ≤ +100mV L
AS1153 – Open, undriven short, or undriven
100Ω parallel termination H
AS1157 – Open or undriven short
LVDS
Signals
107Ω
LVTTL/LVCMOS
Data Inputs LVTTL/LVCMOS
Data Outputs
100Ω Shielded Twisted Cable or Microstrip PC Board Traces
Tx Rx
AS1157
LVDS Receiver
AS1154
0.1µF0.001µF
+3.3V
0.1µF0.001µF
+3.3V
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AS1153, AS1157
Datasheet - Applications
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches.
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Ba l-
anced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections, and reduce EMI.
The AS1157 has integrated termination resistors connected across the inputs of each receiver. The value of the integrated resistor is spec i-
fied in Table 3.
The AS1153 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission
line and be placed as close to the receiver inputs as possible. Termination resistance values may range between 90 to 132Ω depending on
the characteristic impedance of the transmission medium. Use 1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent coupling.
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Propagation Delay and Transition Time Test Circuit
INx+
50Ω50Ω
INx-
OUTx
CL
Pulse
Generator**
* 50Ω required for pulse generator .
** When testing the AS1157, adjust the pulse generator output
to account for intern al termination resistor.
Receiver
AS1153, AS1157
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AS1153, AS1157
Datasheet - Ordering Information
11 Ordering Information
The devices are available as the standard products shown in Table 7.
Note: All products are RoHS compliant.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Table 7. Ordering Information
Ordering Code Marking Description Delivery Form Package
AS1153 AS1153 Dual LVDS Receiver Tubes 8-pin SOIC
AS1153-T AS1153 Dual LVDS Receiver Tape and Reel 8-pin SOIC
AS1157 AS1157 Dual LVDS Receiver, with termina tion Tubes 8-pin SOIC
AS1157-T AS1157 Dual LVDS Receiver, with termination Tape and Reel 8-pin SOIC
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AS1153, AS1157
Datasheet
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All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
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austriamicrosystems AG makes no warranty, express, statutory , implied, or by description regarding the information set forth herein or regarding
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