CY8C24123A
CY8C24223A
CY8C24423A
PSoC® Programmable System-on-Chip
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-12028 Rev. *W Revised May 3, 2017
PSoC® Programmable System-on -Chip
Features
■Powerful Harvard-architecture processor
❐M8C processor speeds up to 24 MHz
❐8 × 8 multiply, 32-bit accumulate
❐Low power at high speed
❐Operating voltage: 2.4 V to 5.25 V
❐Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐Industrial temperature range: –40 °C to +85 °C
■Advanced peripherals (PSoC® blocks)
❐Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐Complex peripherals by combining blocks
■Precision, programmable clocking
❐Internal ±5% 24- / 48-MHz main oscillator
❐High accuracy 24 MHz with optional 32 kHz crystal and
phase-locked loop (PLL)
❐Optional external oscillator up to 24 MHz
❐Internal oscillator for watchdog and sleep
■Flexible on-chip memory
❐4 KB flash program storage 50,000 erase/write cycles
❐256-bytes SRAM data storage
❐In-system serial programming (ISSP)
❐Partial flash updates
❐Flexible protection modes
❐Electronically erasable programmable read only memory
(EEPROM) emulation in flash
■Programmable pin configurations
❐25-mA sink, 10-mA source on all GPIOs
❐Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐Eight standard analog inputs on all GPIOs, and
four additional analog inputs with restricted routing
❐Two 30 mA analog outputs on all GPIOs
❐Configurable interrupt on all GPIOs
■New CY8C24x23A PSoC device
❐Derived from the CY8C24x23 device
❐Low power and low voltage (2.4 V)
■Additional system resources
❐I2C slave, master, and multi-master to 400 kHz
❐Watchdog and sleep timers
❐User-configurable low-voltage detection (LVD)
❐Integrated supervisory circuit
❐On-chip precision voltage reference
■Complete development tools
❐Free development software (PSoC Designer™)
❐Full-featured, in-circuit emulator (ICE), and programmer
❐Full-speed emulation
❐Complex breakpoint structure
❐128 KB trace memory
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 4KB
Digital
Block
Array
Multiply
Accum.
Switch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
I2C
Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Analog
Block
Array
Logic Block Diagram
Errata: For information on silicon errata, see “Errata” on page 67. Details include trigger conditions, devices affected, and proposed workaround.
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More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. Following is an abbreviated list for PSoC 1:
■Overview: PSoC Portfolio, PSoC Roadmap
■Product Selectors: PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
In addition, PSoC Designer offers a device selection tool within
PSoC 1, at the time of creating a new project.
■Datasheets: Describe and provide electrical specifications for
all the PSoC 1 family of devices. Visit the PSoC 1 datasheets
web page for a complete list
■Application notes and code examples:
❐Visit the PSoC 1 Code Examples web page for a comprehen-
sive list of code examples
❐Cypress offers a large number of PSoC application notes
covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started
with PSoC 1 are:
•AN75320: Getting Started with PSoC® 1
•AN2094: PSoC®1 - Getting Started with GPIO
•AN2015: PSoC® 1 - Getting Started with Flash & E2PROM
•AN2014: Basics of PSoC® 1 Programming
•AN32200: PSoC® 1 - Clocks and Global Resources
•AN2010: PSoC®1 Best Practices and Recommendations
■Technical Reference Manual (TRM):
❐Visit the PSoC 1 TRM page for the complete list of TRMs.
Following documents provide detailed descriptions of the Ar-
chitecture, Programming specification and Register map de-
tails of CY8C2XXXX PSoC 1 device family.
• PSoC1 CY8C2XXXX TRM
•PSoC1 ISSP Programming Specifications
■Development Kits:
❐CY3210 - CY8C24x23 PSoC(R) Evaluation Pods (EvalPod)
are 28-pin PDIP adapters that seamlessly connect any PSoC
device to the 28-pin PDIP connector on any Cypress PSoC
development kit. CY3210-24x23 provides evaluation of the
CY8C24x23A PSoC device family on any PSoC developer
kit. PSoC developer kits are sold separately.
❐Visit the PSoC® 1 Kits page and refer the Kit Selector Guide
document to find out the suitable development kits and
debuggers for all PSoC 1 families.
■The CY3217-MiniProg1 and CY8CKIT-002 PSoC® MiniProg3
device provide an interface for flash programming.
■Knowledge Base Articles (KBA): Provide design and appli-
cation tips from experts on the devices/kits. For example, Flash
read/write access from firmware, explains how we can read
and write to flash in PSoC 1 devices
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see Figure 1). With PSoC Designer, you can:
1. Drag and drop user modules to build your hardware system
design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Designer IDE C compiler
3. Configure user module
4. Explore the library of user modules
5. Review user module datasheets
Figure 1. PSoC Designer Features
12
3
4
5
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Contents
PSoC Functional Overview ..............................................4
PSoC Core .................................................................. 4
Digital System ............................................................. 4
Analog System ............................................................5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants ....................................................7
Solutions Library ..........................................................7
Technical Support ....................................................... 7
Development Tools .......................................................... 8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer .......................................9
Select User Modules ...................................................9
Configure User Modules ..............................................9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................ 10
8-Pin Part Pinout ....................................................... 10
20-Pin Part Pinout .....................................................11
28-Pin Part Pinout .....................................................12
32-Pin Part Pinout .....................................................13
56-Pin Part Pinout .....................................................14
Register Reference ......................................................... 15
Register Conventions ................................................15
Register Mapping Tables ..........................................15
Electrical Specifications ................................................18
Absolute Maximum Ratings ....................................... 18
Operating Temperature .............................................19
DC Electrical Characteristics ..................................... 19
AC Electrical Characteristics ..................................... 37
Packaging Information ................................................... 51
Packaging Dimensions .............................................. 51
Thermal Impedances ................................................. 57
Capacitance on Crystal Pins ..................................... 57
Solder Reflow Specifications ..................................... 57
Development Tool Selection ......................................... 58
Software .................................................................... 58
Development Kits ...................................................... 58
Evaluation Tools ........................................................ 58
Device Programmers ................................................. 59
Accessories (Emulation and Programming) .............. 59
Ordering Information ...................................................... 60
Ordering Code Definitions ......................................... 60
Acronyms ........................................................................ 61
Acronyms Used ......................................................... 61
Reference Documents .................................................... 61
Document Conventions ................................................. 62
Units of Measure ....................................................... 62
Numeric Conventions ................................................ 62
Glossary .......................................................................... 62
Errata ............................................................................... 67
Part Numbers Affected .............................................. 67
CY8C24123A Qualification Status ............................ 67
CY8C24123A Errata Summary ................................. 67
Document History Page ................................................. 68
Sales, Solutions, and Legal Information ...................... 71
Worldwide Sales and Design Support ....................... 71
Products .................................................................... 71
PSoC® Solutions ...................................................... 71
Cypress Developer Community ................................. 71
Technical Support ..................................................... 71
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PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with a low-cost single-chip programmable device.
PSoC devices include configurable blocks of analog and digital
logic, and programmable interconnects. This architecture makes
it possible for you to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts and packages.
The PSoC architecture, shown in Figure 2, consists of four main
areas: PSoC core, digital system, analog system, and system
resources. Configurable global busing allows combining all the
device resources into a complete custom system. The PSoC
CY8C24x23A family can have up to three I/O ports that connect
to the global digital and analog interconnects, providing access
to four digital blocks and six analog blocks.
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
The M8C CPU core is a powerful processor with speeds up to
24 Hz, providing a four-MIPS 8-bit Harvard-architecture
microprocessor. The CPU uses an interrupt controller with
11 vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included sleep and watchdog timers (WDT).
Memory encompasses 4 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±2.5% to ±5% over temperature and voltage[1]. The 24 MHz IMO
can also be doubled to 48 MHz for use by the digital system. A
low power 32 kHz internal low speed oscillator (ILO) is provided
for the sleep timer and WDT. If crystal accuracy is required, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can generate a system interrupt on high
level, low level, and change from last read.
Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that may be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user module references.
Figure 2. Digital System Block Diagram
Digital peripheral configurations are:
■PWMs (8- and 16-bit)
■PWMs with dead band (8- and 16-bit)
■Counters (8- to 32-bit)
■Timers (8- to 32-bit)
■UART 8-bit with selectable parity
■SPI master and slave
■I2C slave and multi-master (one is available as a system
resource)
■CRC generator (8- to 32-bit)
■IrDA
■PRS generators (8- to 32-bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This gives a choice of
system resources for your application. Family resources are
shown in Table 1 on page 6.
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2
Port 1
Port 0
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0°C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 67.
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Analog System
The analog system consists of six configurable blocks, each
consisting of an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and SAR)
■Filters (two and four pole band-pass, low-pass, and notch)
■Amplifiers (up to two, with selectable gain to 48x)
■Instrumentation amplifiers (one with selectable gain to 93x)
■Comparators (up to two, with 16 selectable thresholds)
■DACs (up to two, with 6 to 9-bit resolution)
■Multiplying DACs (up to two, with 6 to 9-bit resolution)
■High current output drivers (two with 30 mA drive as a PSoC
Core resource)
■1.3 V reference (as a system resource)
■DTMF dialer
■Modulators
■Correlators
■Peak detectors
■Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 3
Figure 3. Analog System Block Diagram
ACB00 ACB01
Block Array
Array Input Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
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Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
switch-mode pump, low-voltage detection, and power-on-reset
(POR). Statements describing the merits of each system
resource follow:
■Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks may
be generated using digital PSoC blocks as clock dividers.
■A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■The I2C module provides 100- and 400-kHz communication
over two wires. slave, master, and multi-master are supported.
■Low-voltage detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR circuit
eliminates the need for a system supervisor.
■An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■An integrated switch-mode pump generates normal operating
voltages from a single 1.2 V battery cell, providing a low cost
boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted in this table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66 up to 64 4 16 up to 12 4 4 12 2 K 32 K
CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to
12 + 4[2] 1 K 16 K
CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K
CY8C24x94 up to 56 1 4 up to 48 2 2 6 1 K 16 K
CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4 K
CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8 K
CY8C22x45 up to 38 2 8 up to 38 0 4 6[2] 1 K 16 K
CY8C21x45 up to 24 1 4 up to 24 0 4 6[2] 512 8 K
CY8C21x34 up to 28 1 4 up to 28 0 2 4[2] 512 8 K
CY8C21x23 up to 16 1 4 up to 8 0 2 4[2] 256 4 K
CY8C20x34 up to 28 0 0 up to 28 0 0 3[2,3] 512 8 K
CY8C20xx6 up to 36 0 0 up to 36 0 0 3[2,3] up to
2 K
up to
32 K
Notes
2. Limited analog functionality.
3. Two analog blocks and one CapSense®.
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Getting Started
For in depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable knowledge base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
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Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■Extensive user module catalog
■Integrated source-code editor (C and assembly)
■Free C compiler with no size restrictions or time limits
■Built-in debugger
■In-circuit emulation
■Built-in support for communication interfaces:
❐Hardware and software I2C slaves and masters
❐Full-speed USB 2.0
❐Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
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Pinouts
This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled
with a “P”) is capable of digital I/O. However, VSS, VDD, SMP, and XRES are not capable of digital I/O.
8-Pin Part Pinout
Table 2. 8-Pin PDIP and SOIC
Pin
No.
Type Pin
Name Description
Digital Analog
1I/O I/O P0[5] Analog column mux input and column
output
Figure 4. CY8C24123A 8-Pin PSoC Device
2I/O I/O P0[3] Analog column mux input and column
output
3I/O P1[1] Crystal input (XTALin), I2C serial clock
(SCL), ISSP-SCLK[4]
4Power VSS Ground connection
5I/O P1[0] Crystal output (XTALout), I2C serial
data (SDA), ISSP-SDATA[4]
6I/O IP0[2] Analog column mux input
7I/O IP0[4] Analog column mux input
8Power VDD Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
PDIP
SOIC
1
2
3
4
8
7
6
5
VDD
P0[4], A, I
P0[2], A, I
P1[0], XTALout, I2C SDA
A, IO, P0[5]
A, IO, P0[3]
I2C SCL, XTALin, P1[1]
VSS
Note
4. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 11 of 71
20-Pin Part Pinout
Table 3. 20-Pin PDIP, SSOP, and SOIC
Pin
No.
Type Pin
Name Description
Digital Analog
1I/O I P0[7] Analog column mux input Figure 5. CY8C24223A 20-Pin PSoC Device
2I/O I/O P0[5] Analog column mux input and column output
3I/O I/O P0[3] Analog column mux input and column output
4I/O I P0[1] Analog column mux input
5Power SMP SMP connection to external components
required
6I/O P1[7] I2C SCL
7I/O P1[5] I2C SDA
8I/O P1[3]
9I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[5]
10 Power VSS Ground connection.
11 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[5]
12 I/O P1[2]
13 I/O P1[4] Optional external clock input (EXTCLK)
14 I/O P1[6]
15 Input XRES Active high external reset with internal
pull-down
16 I/O I P0[0] Analog column mux input
17 I/O I P0[2] Analog column mux input
18 I/O I P0[4] Analog column mux input
19 I/O I P0[6] Analog column mux input
20 Power VDD Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
PDIP
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VDD
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout,
I2C SDA
Note
5. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 12 of 71
28-Pin Part Pinout
Table 4. 28-Pin PDIP, SSOP, and SOIC
Pin
No.
Type Pin
Name Description
Digital Analog
1I/O I P0[7] Analog column mux input Figure 6. CY8C24423A 28-Pin PSoC Device
2I/O I/O P0[5] Analog column mux input and column output
3I/O I/O P0[3] Analog column mux input and column output
4I/O I P0[1] Analog column mux input
5I/O P2[7]
6I/O P2[5]
7I/O I P2[3] Direct switched capacitor block input
8I/O I P2[1] Direct switched capacitor block input
9Power SMP SMP connection to external components
required
10 I/O P1[7] I2C SCL
11 I/O P1[5] I2C SDA
12 I/O P1[3]
13 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[6]
14 Power VSS Ground connection.
15 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[6]
16 I/O P1[2]
17 I/O P1[4] Optional EXTCLK
18 I/O P1[6]
19 Input XRES Active high external reset with internal
pull-down
20 I/O I P2[0] Direct switched capacitor block input
21 I/O I P2[2] Direct switched capacitor block input
22 I/O P2[4] External analog ground (AGND)
23 I/O P2[6] External voltage reference (VREF)
24 I/O I P0[0] Analog column mux input
25 I/O I P0[2] Analog column mux input
26 I/O I P0[4] Analog column mux input
27 I/O I P0[6] Analog column mux input
28 Power VDD Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2CSCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
VDD
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Note
6. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
Not for Production
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 13 of 71
32-Pin Part Pinout
Table 5. 32-Pin QFN[7]
Pin No. Type Pin
Name Description
Digital Analog
1I/O P2[7] Figure 7. CY8C24423A 32-Pin PSoC Device
2I/O P2[5]
3I/O I P2[3] Direct switched capacitor block input
4I/O I P2[1] Direct switched capacitor block input
5Power VSS Ground connection
6Power SMP SMP connection to external components
required
7I/O P1[7] I2C SCL
8I/O P1[5] I2C SDA
9NC No connection. Pin must be left floating
10 I/O P1[3]
11 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[8]
12 Power VSS Ground Connection
13 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[8]
14 I/O P1[2]
15 I/O P1[4] Optional EXTCLK
16 NC No connection. Pin must be left floating
17 I/O P1[6]
18 Input XRES Active high external reset with internal
pull-down
19 I/O I P2[0] Direct switched capacitor block input
20 I/O I P2[2] Direct switched capacitor block input
21 I/O P2[4] External AGND
22 I/O P2[6] External VREF
23 I/O I P0[0] Analog column mux input
24 I/O I P0[2] Analog column mux input
25 NC No connection. Pin must be left floating
26 I/O I P0[4] Analog column mux input
27 I/O I P0[6] Analog column mux input
28 Power VDD Supply voltage
29 I/O I P0[7] Analog column mux input
30 I/O I/O P0[5] Analog column mux input and column
output
31 I/O I/O P0[3] Analog column mux input and column
output
32 I/O I P0[1] Analog column mux input
LEGEND: A = Analog, I = Input, and O = Output.
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
VSS
SMP
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
VDD
P0[6], A, I
P0[4], A, I
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
P0[2], A, I
P0[0], A, I
XRES
P1[6]
NC
P1[3]
I2C SCL, XTALin, P1[1]
VSS
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
NC
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
Notes
7. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
8. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 14 of 71
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 6. 56-Pin SSOP OCD
Pin No. Type Pin
Name Description
Digital Analog
1NC No connection. Pin must be left floating Figure 8. CY8C24000A 56-Pin PSoC Device
2I/O I P0[7] Analog column mux input
3I/O I P0[5] Analog column mux input and column output
4I/O I P0[3] Analog column mux input and column output
5I/O I P0[1] Analog column mux input
6I/O P2[7]
7I/O P2[5]
8I/O I P2[3] Direct switched capacitor block input
9I/O I P2[1] Direct switched capacitor block input
10 NC No connection. Pin must be left floating
11 NC No connection. Pin must be left floating
12 NC No connection. Pin must be left floating
13 NC No connection. Pin must be left floating
14 OCD OCDE OCD even data I/O
15 OCD OCDO OCD odd data output
16 Power SMP SMP connection to required external compo-
nents
17 NC No connection. Pin must be left floating
18 NC No connection. Pin must be left floating
19 NC No connection. Pin must be left floating
20 NC No connection. Pin must be left floating
21 NC No connection. Pin must be left floating
22 NC No connection. Pin must be left floating
23 I/O P1[7] I2C SCL
24 I/O P1[5] I2C SDA
25 NC No connection. Pin must be left floating
26 I/O P1[3]
27 I/O P1[1] XTALin, I2C SCL, ISSP-SCLK[9]
28 Power VDD Supply voltage
29 NC No connection. Pin must be left floating
30 NC No connection. Pin must be left floating
31 I/O P1[0] XTALout, I2C SDA, ISSP-SDATA[9]
32 I/O P1[2]
33 I/O P1[4] Optional EXTCLK
34 I/O P1[6]
35 NC No connection. Pin must be left floating
36 NC No connection. Pin must be left floating
37 NC No connection. Pin must be left floating
38 NC No connection. Pin must be left floating
39 NC No connection. Pin must be left floating
40 NC No connection. Pin must be left floating
41 Input XRES Active high external reset with internal pull-down.
42 OCD HCLK OCD high speed clock output.
43 OCD CCLK OCD CPU clock output.
44 NC No connection. Pin must be left floating
45 NC No connection. Pin must be left floating
46 NC No connection. Pin must be left floating
47 NC No connection. Pin must be left floating
48 I/O I P2[0] Direct switched capacitor block input.
49 I/O I P2[2] Direct switched capacitor block input.
50 I/O P2[4] External AGND.
51 I/O P2[6] External VREF.
52 I/O I P0[0] Analog column mux input.
53 I/O I P0[2] Analog column mux input and column output.
54 I/O I P0[4] Analog column mux input and column output.
55 I/O I P0[6] Analog column mux input.
56 Power VDD Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Note
9. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
SSOP
156
255
354
453
552
651
750
849
948
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
VDD
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
NC
NC
NC
NC
CCLK
HCLK
XRES
NC
NC
NC
NC
NC
NC
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALOut, I2C SDA, SDATA
NC
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
NC
NC
NC
NC
OCDE
OCDO
SMP
NC
NC
NC
NC
NC
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
VSS
NC
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 15 of 71
Register Reference
This section lists the registers of the CY8C24x23A PSoC device. For detailed register information, see the PSoC Programmable
Sytem-on-Chip Reference Manual.
Register Conventions
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Register Mapping Tables
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks, Bank 0 and Bank 1. The XOI bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XOI bit is set, the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Table 7. Abbreviations
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 16 of 71
Table 8. Register Map Bank 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW D0
11 51 ASD20CR1 91 RW D1
12 52 ASD20CR2 92 RW D2
13 53 ASD20CR3 93 RW D3
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW I2C_CFG D6 RW
17 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL_X E8 W
DCB02DR1 29 W 69 A9 MUL_Y E9 W
DCB02DR2 2A RW 6A AA MUL_DH EA R
DCB02CR0 2B # 6B AB MUL_DL EB R
DCB03DR0 2C # 6C AC ACC_DR1 EC RW
DCB03DR1 2D W 6D AD ACC_DR0 ED RW
DCB03DR2 2E RW 6E AE ACC_DR3 EE RW
DCB03CR0 2F # 6F AF ACC_DR2 EF RW
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and must not be accessed. # Access is bit specific.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 17 of 71
Table 9. Register Map Bank 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW 40 ASC10CR0 80 RW C0
PRT0DM1 01 RW 41 ASC10CR1 81 RW C1
PRT0IC0 02 RW 42 ASC10CR2 82 RW C2
PRT0IC1 03 RW 43 ASC10CR3 83 RW C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 ASD20CR0 90 RW GDI_O_IN D0 RW
11 51 ASD20CR1 91 RW GDI_E_IN D1 RW
12 52 ASD20CR2 92 RW GDI_O_OU D2 RW
13 53 ASD20CR3 93 RW GDI_E_OU D3 RW
14 54 ASC21CR0 94 RW D4
15 55 ASC21CR1 95 RW D5
16 56 ASC21CR2 96 RW D6
17 57 ASC21CR3 97 RW D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B 6B AB ECO_TR EB W
DCB03FN 2C RW 6C AC EC
DCB03IN 2D RW 6D AD ED
DCB03OU 2E RW 6E AE EE
2F 6F AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and must not be accessed. # Access is bit specific.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 18 of 71
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications,
check if you have the most recent datasheet by visiting the website at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted.
Refer to Table 30 on page 37 for the electrical specifications for the IMO using SLIMO mode.
Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vd d Vo l ta g e
2.40
3 MHz
Valid
Operating
Region
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
IMO Frequency
Vd d Vo l ta g e
3.60
6 MHz
SLIMO Mode = 0
SLIMO
Mode=0
2.40
SLIMO
Mode=1
SLIMO
Mode=1
SLIMO
Mode=1
SLIMO
Mode=1
SLIMO
Mode=0
Table 10. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage temperature –55 25 +100 °C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrades reliability.
TBAKETEMP Bake temperature –125 See
package
label
°C
tBAKETIME Bake time See
package
label
–72 Hours
TAAmbient temperature with power applied –40 –+85 °C
VDD Supply voltage on VDD relative to VSS –0.5 –+6.0 V
VIO DC input voltage VSS – 0.5 – VDD + 0.5 V
VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin –25 –+50 mA
ESD Electrostatic discharge voltage 2000 – – V Human body model ESD.
LU Latch up current – – 200 mA
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 19 of 71
Operating Temperature
DC Electrical Characteristics
DC Chip-Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 11. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient temperature –40 –+85 °C
TJJunction temperature –40 –+100 °C The temperature rise from ambient
to junction is package specific. See
Table 49 on page 57. You must limit
the power consumption to comply
with this requirement
Table 12. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
VDD Supply voltage 2.4 –5.25 VSee DC POR and LVD specifications,
Table 27 on page 35
IDD Supply current – 5 8 mA Conditions are VDD = 5.0 V, TA = 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off
SLIMO mode = 0. IMO = 24 MHz
IDD3 Supply current –3.3 6.0 mA Conditions are VDD = 3.3 V, TA= 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz
IDD27 Supply current – 2 4 mA Conditions are VDD = 2.7 V, TA = 25 °C,
CPU = 0.75 MHz, SYSCLK doubler
disabled, VC1 = 0.375 MHz,
VC2 = 23.44 kHz, VC3 = 0.09 kHz,
analog power = off. SLIMO mode = 1.
IMO = 6 MHz
ISB Sleep (mode) current with POR, LVD, sleep timer,
and WDT.[10] – 3 6.5 µA Conditions are with internal slow speed
oscillator, VDD = 3.3 V, –40 °C TA
55 °C, analog power = off
ISBH Sleep (mode) current with POR, LVD, sleep timer,
and WDT at high temperature.[10] – 4 25 µA Conditions are with internal slow speed
oscillator, VDD = 3.3 V, 55 °C < TA
85 °C, analog power = off
ISBXTL Sleep (mode) current with POR, LVD, sleep timer,
WDT, and external crystal.[10] – 4 7.5 µA Conditions are with properly loaded,
1 µW max, 32.768 kHz crystal.
VDD = 3.3 V, –40 °C TA 55 °C, analog
power = off
ISBXTLH Sleep (Mode) current with POR, LVD, sleep timer,
WDT, and external crystal at high temperature.[10] – 5 26 µA Conditions are with properly loaded, 1µW
max, 32.768 kHz crystal.
VDD = 3.3 V, 55 °C < TA 85 °C, analog
power = off
VREF Reference voltage (Bandgap) 1.28 1.30 1.32 VTrimmed for appropriate VDD.
VDD > 3.0 V
VREF27 Reference voltage (Bandgap) 1.16 1.30 1.32 VTrimmed for appropriate VDD.
VDD = 2.4 V to 3.0 V
Note
10. Standby current includes all functions (POR, LVD, WDT, sleep time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
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DC GPIO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 13. 5 V and 3.3 V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 1.0 – – V IOH = 10 mA, VDD = 4.75 to 5.25 V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]), maximum
40 mA on odd port pins (for example,
P0[3], P1[5])). 80 mA maximum
combined IOH budget.
VOL Low output level – – 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V
(maximum 100 mA on even port pins
(for example, P0[2], P1[4]), maximum
100 mA on odd port pins (for example,
P0[3], P1[5])). 150 mA maximum
combined IOL budget.
IOH High level source current 10 – – mA VOH = VDD – 1.0 V, see the limitations
of the total current in the note for VOH
IOL Low level sink current 25 – – mA VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL Input low level – – 0.8 V VDD = 3.0 to 5.25
VIH Input high level 2.1 – V VDD = 3.0 to 5.25
VHInput hysterisis –60 –mV
IIL Input leakage (absolute value) –1–nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent.
Tem p = 2 5 ° C
COUT Capacitive load on pins as output –3.5 10 pF Package and pin dependent.
Tem p = 2 5 °C
Table 14. 2.7 V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 0.4 – – V IOH = 2 mA (6.25 Typ), VDD = 2.4 to
3.0 V (16 mA maximum, 50 mA Typ
combined IOH budget).
VOL Low output level – – 0.75 V IOL = 11.25 mA, VDD = 2.4 to 3.0 V (90
mA maximum combined IOL budget).
IOH High level source current 2 – – mA VOH = VDD – 0.4, see the limitations of
total current in note for VOH.
VIL Input low level – – 0.75 V VDD = 2.4 to 3.0
VIH Input high level 2.0 – – V VDD = 2.4 to 3.0
VHInput hysteresis – 90 – mV
IOL Low level sink current 11.25 – – mA VOL = .75, see the limitations of total
current in note for VOL.
IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent.
Tem p = 2 5 ° C
COUT Capacitive load on pins as output – 3.5 10 pF Package and pin dependent.
Tem p = 2 5 ° C
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DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
The operational amplifier is a component of both the analog continuous time PSoC blocks and the Analog Switched Cap PSoC blocks.
The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters are measured at 5 V at
25 °C and are for design guidance only.
Table 15. 5 V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–1.6
1.3
1.2
10
8
7.5
mV
mV
mV
–
–
TCVOSOA Average input offset voltage drift – 7.0 35.0 µV/°C
IEBOA Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 µA
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 2 5 °C
VCMOA Common mode voltage range
Common mode voltage range (high power or high
Opamp bias)
0.0 – VDD
VDD – 0.5
V The common mode input voltage
range is measured through an
analog output buffer. The
specification includes the limitations
imposed by the characteristics of
the analog output buffer.
0.5 –
GOLOA Open loop gain
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
60
60
80
–
–
–
–
–
–
dB
dB
dB
Specification is applicable at high
Opamp bias. For low Opamp bias
mode, minimum is 60 dB.
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
ISOA Supply current (including associated AGND buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply voltage rejection ratio 64 80 – dB VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
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Table 16. 3.3 V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
TCVOSOA Average input offset voltage drift – 7.0 35.0 µV/°C
IEBOA Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 A
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0.2 – VDD – 0.2 V The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the limitations
imposed by the characteristics of the
analog output buffer.
GOLOA Open loop gain
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
Specification is applicable at low
Opamp bias. For high Opamp bias
mode (except high power, high
Opamp bias), minimum is 60 dB.
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
VOLOWOA Low output voltage swing (internal signals)
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
ISOA Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
A
A
A
A
A
A
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
PSRROA Supply voltage rejection ratio 64 80 – dB VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
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DC Low Power Comparator Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V at 25 °C and are for design guidance only.
Table 17. 2.7 V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
Power = high, Opamp bias = high
setting is not allowed for 2.7 V VDD
operation.
TCVOSOA Average input offset voltage drift – 7.0 35.0 V/°C
IEBOA Input leakage current (port 0 analog pins) – 20 – pA Gross tested to 1 A
CINOA Input capacitance (port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Tem p = 2 5 °C
VCMOA Common mode voltage range 0.2 – VDD – 0.2 V The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by
the characteristics of the analog
output buffer.
GOLOA Open loop gain
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
Specification is applicable at low
Opamp bias. For high Opamp bias
mode, (except high power, high
Opamp bias), minimum is 60 dB.
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
Power = high, Opamp bias = high
setting is not allowed for 2.7 V VDD
operation.
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = high, Opamp bias = high
setting is not allowed for 2.7 V VDD
operation.
ISOA Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
A
A
A
A
A
A
Power = high, Opamp bias = high
setting is not allowed for 2.7 V VDD
operation.
PSRROA Supply voltage rejection ratio 64 80 – dB VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
Table 18. DC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
VREFLPC Low power comparator (LPC) reference voltage
range
0.2 – VDD – 1 V
ISLPC LPC supply current – 10 40 µA
VOSLPC LPC voltage offset – 2.5 30 mV
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DC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 19. 5 V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
CLLoad Capacitance – – 200 pF This specification applies to the
external circuit that is being driven
by the analog output buffer.
VOSOB Input offset voltage (absolute value) – 3 12 mV
TCVOSOB Average input offset voltage drift –+6 –V/°C
VCMOB Common mode input voltage range 0.5 – VDD – 1.0 V
ROUTOB Output resistance
Power = low
Power = high
–
–
1
1
–
–
W
W
VOHIGHOB High output voltage swing
(Load = 32 ohms to VDD/2)
Power = low
Power = high
0.5 × VDD + 1.1
0.5 × VDD + 1.1
–
–
–
–
V
V
VOLOWOB Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = low
Power = high
–
–
–
–
.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
ISOB Supply current including Opamp bias
cell
(No Load)
Power = low
Power = high
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRROB Supply voltage rejection ratio 52 64 –dB VOUT > (VDD – 1.25)
Table 20. 3.3 V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
CLLoad Capacitance – – 200 pF This specification applies to the
external circuit that is being driven
by the analog output buffer.
VOSOB Input offset voltage (absolute value) – 3 12 mV
TCVOSOB Average input offset voltage drift –+6 –V/°C
VCMOB Common mode input voltage range 0.5 – VDD – 1.0 V
ROUTOB Output resistance
Power = low
Power = high
–
–
1
1
–
–
VOHIGHOB High output voltage swing (Load = 1 K
ohms to VDD/2)
Power = low
Power = high
0.5 × VDD + 1.0
0.5 × VDD + 1.0
–
–
–
–
V
V
VOLOWOB Low output voltage swing (Load = 1 K
ohms to VDD/2)
Power = low
Power = high
–
–
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
ISOB Supply current including Opamp bias
cell
(no load)
Power = low
Power = high
–
–
0.8
2.0
2.0
4.3
mA
mA
PSRROB Supply voltage rejection ratio 52 64 –dB VOUT > (VDD – 1.25)
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Table 21. 2.7 V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
CLLoad Capacitance – – 200 pF This specification applies to the
external circuit that is being driven by
the analog output buffer.
VOSOB Input offset voltage (absolute value) – 3 12 mV
TCVOSOB Average input offset voltage drift –+6 –V/°C
VCMOB Common mode input voltage range 0.5 – VDD – 1.0 V
ROUTOB Output resistance
Power = low
Power = high
–
–
1
1
–
–
VOHIGHOB High output voltage swing (Load = 1
K ohms to VDD/2)
Power = low
Power = high
0.5 × VDD + 0.2
0.5 × VDD + 0.2
–
–
–
–
V
V
VOLOWOB Low output voltage swing (Load = 1
K ohms to VDD/2)
Power = low
Power = high
–
–
–
–
0.5 × VDD – 0.7
0.5 × VDD – 0.7
V
V
ISOB Supply current including Opamp
bias cell (No Load)
Power = low
Power = high
–
0.8
2.0
2.0
4.3
mA
mA
PSRROB Supply voltage rejection ratio 52 64 –dB VOUT > (VDD – 1.25).
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DC Switch Mode Pump Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 22. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP 5 V 5 V output voltage from pump 4.75 5.0 5.25 V Configuration listed in footnote.[11]
Average, neglecting ripple. SMP trip
voltage is set to 5.0 V.
VPUMP 3 V 3.3 V output voltage from pump 3.00 3.25 3.60 V Configuration listed in footnote.[11]
Average, neglecting ripple. SMP trip
voltage is set to
3.25 V.
VPUMP 2 V 2.6 V output voltage from pump 2.45 2.55 2.80 V Configuration listed in footnote.[11]
Average, neglecting ripple. SMP trip
voltage is set to
2.55 V.
IPUMP Available output current
VBAT = 1.8 V, VPUMP = 5.0 V
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configuration listed in footnote.[11]
SMP trip voltage is set to 5.0 V.
SMP trip voltage is set to 3.25 V.
SMP trip voltage is set to 2.55 V.
VBAT5 V Input voltage range from battery 1.8 – 5.0 V Configuration listed in footnote.[11]
SMP trip voltage is set to 5.0 V.
VBAT3 V Input voltage range from battery 1.0 – 3.3 V Configuration listed in footnote.[11]
SMP trip voltage is set to 3.25 V.
VBAT2 V Input voltage range from battery 1.0 – 3.0 V Configuration listed in footnote.[11]
SMP trip voltage is set to 2.55 V.
VBATSTART Minimum input voltage from
battery to start pump
1.2 – – V Configuration listed in footnote.[11]
0 °C TA 100. 1.25 V at TA = –40 °C
VPUMP_Line Line regulation (over VBAT
range)
–5 –%V
O Configuration listed in footnote.[11] VO
is the VDD Value for PUMP Trip”
specified by the VM[2:0] setting in the
DC POR and LVD Specification, Table
27 on page 35.
VPUMP_Load Load regulation – 5 – %VO Configuration listed in footnote.[11] VO
is the “VDD value for PUMP Trip”
specified by the VM[2:0] setting in the
DC POR and LVD Specification, Table
27 on page 35.
VPUMP_Ripple Output voltage ripple (depends
on capacitor/load)
– 100 – mVpp Configuration listed in footnote.[11]
Load is 5 mA.
E3Efficiency 35 50 – % Configuration listed in footnote.[11]
Load is 5 mA. SMP trip voltage is set
to 3.25 V.
E2Efficiency – – –
FPUMP Switching frequency – 1.3 – MHz
DCPUMP Switching duty cycle – 50 – %
Note
11. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 11
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Figure 11. Basic Switch Mode Pump Circuit
Battery C1
D1
+PSoC
Vdd
Vss
SMP
VBAT
L1
VPUMP
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DC Analog Reference Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
The guaranteed specifications for RefHI and RefLo are measured through the Analog Continuous Time PSoC blocks. The power
levels for RefHi and RefLo refer to the Analog Reference Control register. AGND is measured at P2[4] in AGND bypass mode. Each
Analog Continuous Time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the
local AGND buffer. Reference control power can be set to medium or high unless otherwise noted.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of
the digital signal may appear on the AGND.
Table 23. 5 V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
0b000 RefPower = high
Opamp bias = high
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409 V
VAGND AGND VDD/2 VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154 V
RefPower = high
Opamp bias = low
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358 V
VAGND AGND VDD/2 VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218 V
RefPower = medium
Opamp bias = high
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357 V
VAGND AGND VDD/2 VDD/2 – 0.055 VDD/2 VDD/2 + 0.052 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224 V
RefPower = medium
Opamp bias = low
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353 V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225 V
0b001 RefPower = high
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] –
0.076
P2[4] + P2[6] –
0.021
P2[4] + P2[6] +
0.041
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] –
0.025
P2[4] – P2[6] +
0.011
P2[4] – P2[6] +
0.085
V
RefPower = high
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] –
0.069
P2[4] + P2[6] –
0.014
P2[4] + P2[6] +
0.043
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] –
0.029
P2[4] – P2[6] +
0.005
P2[4] – P2[6] +
0.052
V
RefPower = medium
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] –
0.072
P2[4] + P2[6] –
0.011
P2[4] + P2[6] +
0.048
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] –
0.031
P2[4] – P2[6] +
0.002
P2[4] – P2[6] +
0.057
V
RefPower = medium
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.009
P2[4] + P2[6] +
0.047
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] –
0.033
P2[4] – P2[6] +
0.001
P2[4] – P2[6] +
0.039
V
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 29 of 71
0b010 RefPower = high
Opamp bias = high
VREFHI Ref High VDD VDD – 0.121 VDD – 0.003 VDD V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 VDD/2 + 0.034 V
VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.019 V
RefPower = high
Opamp bias = low
VREFHI Ref High VDD VDD – 0.083 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033 V
VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.016 V
RefPower = medium
Opamp bias = high
VREFHI Ref High VDD VDD – 0.075 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.015 V
RefPower = medium
Opamp bias = low
VREFHI Ref High VDD VDD – 0.074 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.014 V
0b011 RefPower = high
Opamp bias = high
VREFHI Ref High 3 × Bandgap 3.753 3.874 3.979 V
VAGND AGND 2 × Bandgap 2.511 2.590 2.657 V
VREFLO Ref Low Bandgap 1.243 1.297 1.333 V
RefPower = high
Opamp bias = low
VREFHI Ref High 3 × Bandgap 3.767 3.881 3.974 V
VAGND AGND 2 × Bandgap 2.518 2.592 2.652 V
VREFLO Ref Low Bandgap 1.241 1.295 1.330 V
RefPower = medium
Opamp bias = high
VREFHI Ref High 3 × Bandgap 2.771 3.885 3.979 V
VAGND AGND 2 × Bandgap 2.521 2.593 2.649 V
VREFLO Ref Low Bandgap 1.240 1.295 1.331 V
RefPower = medium
Opamp bias = low
VREFHI Ref High 3 × Bandgap 3.771 3.887 3.977 V
VAGND AGND 2 × Bandgap 2.522 2.594 2.648 V
VREFLO Ref Low Bandgap 1.239 1.295 1.332 V
0b100 RefPower = high
Opamp bias = high
VREFHI Ref High 2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.481 + P2[6] 2.569 + P2[6] 2.639 + P2[6] V
VAGND AGND 2 × Bandgap 2.511 2.590 2.658 V
VREFLO Ref Low 2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.515 – P2[6] 2.602 – P2[6] 2.654 – P2[6] V
RefPower = high
Opamp bias = low
VREFHI Ref High 2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.498 + P2[6] 2.579 + P2[6] 2.642 + P2[6] V
VAGND AGND 2 × Bandgap 2.518 2.592 2.652 V
VREFLO Ref Low 2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6] 2.598 – P2[6] 2.650 – P2[6] V
RefPower = medium
Opamp bias = high
VREFHI Ref High 2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.504 + P2[6] 2.583 + P2[6] 2.646 + P2[6] V
VAGND AGND 2 × Bandgap 2.521 2.592 2.650 V
VREFLO Ref Low 2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6] 2.596 – P2[6] 2.649 – P2[6] V
RefPower = medium
Opamp bias = low
VREFHI Ref High 2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.505 + P2[6] 2.586 + P2[6] 2.648 + P2[6] V
VAGND AGND 2 × Bandgap 2.521 2.594 2.648 V
VREFLO Ref Low 2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6] 2.595 – P2[6] 2.648 – P2[6] V
Table 23. 5 V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 30 of 71
0b101 RefPower = high
Opamp bias = high
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.228 P2[4] + 1.284 P2[4] + 1.332 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.358 P2[4] – 1.293 P2[4] – 1.226 V
RefPower = high
Opamp bias = low
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.236 P2[4] + 1.289 P2[4] + 1.332 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.357 P2[4] – 1.297 P2[4] – 1.229 V
RefPower = medium
Opamp bias = high
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.237 P2[4] + 1.291 P2[4] + 1.337 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.356 P2[4] – 1.299 P2[4] – 1.232 V
RefPower = medium
Opamp bias = low
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.237 P2[4] + 1.292 P2[4] + 1.337 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.357 P2[4] – 1.300 P2[4] – 1.233 V
0b110 RefPower = high
Opamp bias = high
VREFHI Ref High 2 × Bandgap 2.512 2.594 2.654 V
VAGND AGND Bandgap 1.250 1.303 1.346 V
VREFLO Ref Low VSS VSS VSS + 0.011 VSS + 0.027 V
RefPower = high
Opamp bias = low
VREFHI Ref High 2 × Bandgap 2.515 2.592 2.654 V
VAGND AGND Bandgap 1.253 1.301 1.340 V
VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.02 V
RefPower = medium
Opamp bias = high
VREFHI Ref High 2 × Bandgap 2.518 2.593 2.651 V
VAGND AGND Bandgap 1.254 1.301 1.338 V
VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.017 V
RefPower = medium
Opamp bias = low
VREFHI Ref High 2 × Bandgap 2.517 2.594 2.650 V
VAGND AGND Bandgap 1.255 1.300 1.337 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.015 V
0b111 RefPower = high
Opamp bias = high
VREFHI Ref High 3.2 × Bandgap 4.011 4.143 4.203 V
VAGND AGND 1.6 × Bandgap 2.020 2.075 2.118 V
VREFLO Ref Low VSS VSS VSS + 0.011 VSS + 0.026 V
RefPower = high
Opamp bias = low
VREFHI Ref High 3.2 × Bandgap 4.022 4.138 4.203 V
VAGND AGND 1.6 × Bandgap 2.023 2.075 2.114 V
VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.017 V
RefPower = medium
Opamp bias = high
VREFHI Ref High 3.2 × Bandgap 4.026 4.141 4.207 V
VAGND AGND 1.6 × Bandgap 2.024 2.075 2.114 V
VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.015 V
RefPower = medium
Opamp bias = low
VREFHI Ref High 3.2 × Bandgap 4.030 4.143 4.206 V
VAGND AGND 1.6 × Bandgap 2.024 2.076 2.112 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.013 V
Table 23. 5 V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 31 of 71
Table 24. 3.3 V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
0b000 RefPower = high
Opamp bias = high
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.170 VDD/2 + 1.288 VDD/2 + 1.376 V
VAGND AGND VDD/2 VDD/2 – 0.098 VDD/2 + 0.003 VDD/2 + 0.097 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.386 VDD/2 – 1.287 VDD/2 – 1.169 V
RefPower = high
Opamp bias = low
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.210 VDD/2 + 1.290 VDD/2 + 1.355 V
VAGND AGND VDD/2 VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.054 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.359 VDD/2 – 1.292 VDD/2 – 1.214 V
RefPower = medium
Opamp bias = high
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.198 VDD/2 + 1.292 VDD/2 + 1.368 V
VAGND AGND VDD/2 VDD/2 – 0.041 VDD/2 VDD/2 + 0.04 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.362 VDD/2 – 1.295 VDD/2 – 1.220 V
RefPower = medium
Opamp bias = low
VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.202 VDD/2 + 1.292 VDD/2 + 1.364 V
VAGND AGND VDD/2 VDD/2 – 0.033 VDD/2 VDD/2 + 0.030 V
VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.364 VDD/2 – 1.297 VDD/2 – 1.222 V
0b001 RefPower = high
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.072
P2[4] + P2[6] –
0.017
P2[4] + P2[6] +
0.041
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.029
P2[4] – P2[6] +
0.010
P2[4] – P2[6] +
0.048
V
RefPower = high
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.066
P2[4] + P2[6] –
0.010
P2[4] + P2[6] +
0.043
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.024
P2[4] – P2[6] +
0.004
P2[4] – P2[6] +
0.034
V
RefPower = medium
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.073
P2[4] + P2[6] –
0.007
P2[4] + P2[6] +
0.053
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.028
P2[4] – P2[6] +
0.002
P2[4] – P2[6] +
0.033
V
RefPower = medium
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.073
P2[4] + P2[6] –
0.006
P2[4] + P2[6] +
0.056
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.030
P2[4] – P2[6] P2[4] – P2[6] +
0.032
V
0b010 RefPower = high
Opamp bias = high
VREFHI Ref High VDD VDD – 0.102 VDD – 0.003 VDD V
VAGND AGND VDD/2 VDD/2 – 0.040 VDD/2 + 0.001 VDD/2 + 0.039 V
VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.020 V
RefPower = high
Opamp bias = low
VREFHI Ref High VDD VDD – 0.082 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.031 VDD/2 VDD/2 + 0.028 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.015 V
RefPower = medium
Opamp bias = high
VREFHI Ref High VDD VDD – 0.083 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.032 VDD/2 – 0.001 VDD/2 + 0.029 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.014 V
RefPower = medium
Opamp bias = low
VREFHI Ref High VDD VDD – 0.081 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.033 VDD/2 – 0.001 VDD/2 + 0.029 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.013 V
0b011 All power settings
Not allowed at 3.3 V
––– – – ––
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 32 of 71
0b100 All power settings
Not allowed at 3.3 V
––– – – ––
0b101 RefPower = high
Opamp bias = high
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.211 P2[4] + 1.285 P2[4] + 1.348 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.354 P2[4] – 1.290 P2[4] – 1.197 V
RefPower = high
Opamp bias = low
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.209 P2[4] + 1.289 P2[4] + 1.353 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.352 P2[4] – 1.294 P2[4] – 1.222 V
RefPower = medium
Opamp bias = high
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.351 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.351 P2[4] – 1.296 P2[4] – 1.224 V
RefPower = medium
Opamp bias = low
VREFHI Ref High P2[4] + Bandgap (P2[4]
= VDD/2)
P2[4] + 1.215 P2[4] + 1.292 P2[4] + 1.354 V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4] – Bandgap (P2[4]
= VDD/2)
P2[4] – 1.352 P2[4] – 1.297 P2[4] – 1.227 V
0b110 RefPower = high
Opamp bias = high
VREFHI Ref High 2 × Bandgap 2.460 2.594 2.695 V
VAGND AGND Bandgap 1.257 1.302 1.335 V
VREFLO Ref Low VSS VSS VSS + 0.01 VSS + 0.029 V
RefPower = high
Opamp bias = low
VREFHI Ref High 2 × Bandgap 2.462 2.592 2.692 V
VAGND AGND Bandgap 1.256 1.301 1.332 V
VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.017 V
RefPower = medium
Opamp bias = high
VREFHI Ref High 2 × Bandgap 2.473 2.593 2.682 V
VAGND AGND Bandgap 1.257 1.301 1.330 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.014 V
RefPower = medium
Opamp bias = low
VREFHI Ref High 2 × Bandgap 2.470 2.594 2.685 V
VAGND AGND Bandgap 1.256 1.300 1.332 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.012 V
0b111 All power settings
Not allowed at 3.3 V
––– – – ––
Table 24. 3.3 V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 33 of 71
Table 25. 2.7 V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
0b000 All power settings
Not allowed at 2.7 V
––– – – ––
0b001 RefPower = medium
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.739
P2[4] + P2[6] –
0.016
P2[4] + P2[6] +
0.759
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
1.675
P2[4] – P2[6] +
0.013
P2[4] – P2[6] +
1.825
V
RefPower = medium
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.098
P2[4] + P2[6] –
0.011
P2[4] + P2[6] +
0.067
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.308
P2[4] – P2[6] +
0.004
P2[4] – P2[6] +
0.362
V
RefPower = low
Opamp bias = high
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.042
P2[4] + P2[6] –
0.005
P2[4] + P2[6] +
0.035
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.030
P2[4] – P2[6] P2[4] – P2[6] +
0.030
V
RefPower = low
Opamp bias = low
VREFHI Ref High P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.367
P2[4] + P2[6] –
0.005
P2[4] + P2[6] +
0.308
V
VAGND AGND P2[4] P2[4] P2[4] P2[4] –
VREFLO Ref Low P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.345
P2[4] – P2[6] P2[4] – P2[6] +
0.301
V
0b010 RefPower = high
Opamp bias = high
VREFHI Ref High VDD VDD – 0.100 VDD – 0.003 VDD V
VAGND AGND VDD/2 VDD/2 – 0.038 VDD/2 VDD/2 + 0.036 V
VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.016 V
RefPower = high
Opamp bias = low
VREFHI Ref High VDD VDD – 0.065 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.025 VDD/2 VDD/2 + 0.023 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.012 V
RefPower = medium
Opamp bias = high
VREFHI Ref High VDD VDD – 0.054 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.024 VDD/2 – 0.001 VDD/2 + 0.020 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.012 V
RefPower = medium
Opamp bias = low
VREFHI Ref High VDD VDD – 0.042 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.027 VDD/2 – 0.001 VDD/2 + 0.022 V
VREFLO Ref Low VSS VSS VSS + 0.001 VSS + 0.010 V
RefPower = low
Opamp bias = high
VREFHI Ref High VDD VDD – 0.042 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.028 VDD/2 – 0.001 VDD/2 + 0.023 V
VREFLO Ref Low VSS VSS VSS + 0.001 VSS + 0.010 V
RefPower = low
Opamp bias = low
VREFHI Ref High VDD VDD – 0.036 VDD – 0.002 VDD V
VAGND AGND VDD/2 VDD/2 – 0.184 VDD/2 – 0.001 VDD/2 + 0.159 V
VREFLO Ref Low VSS VSS VSS + 0.001 VSS + 0.009 V
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DC Analog PSoC Block Specifications
Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
0b011 All power settings
Not allowed at 2.7 V
––– – – ––
0b100 All power settings
Not allowed at 2.7 V
––– – – ––
0b101 All power settings
Not allowed at 2.7 V
––– – – ––
0b110 RefPower = high
Opamp bias = high
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.160 1.302 1.340 V
VREFLO Ref Low VSS VSS VSS + 0.007 VSS + 0.025 V
RefPower = high
Opamp bias = low
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.160 1.301 1.338 V
VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.017 V
RefPower = medium
Opamp bias = high
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.160 1.301 1.338 V
VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.013 V
RefPower = medium
Opamp bias = low
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.160 1.300 1.337 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.011 V
RefPower = low
Opamp bias = high
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.252 1.300 1.339 V
VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.011 V
RefPower = low
Opamp bias = low
VREFHI Ref High 2 × Bandgap Not allowed Not allowed Not allowed V
VAGND AGND Bandgap 1.252 1.300 1.339 V
VREFLO Ref Low VSS VSS VSS + 0.001 VSS + 0.01 V
0b111 All power settings
Not allowed at 2.7 V
––– – – ––
Table 25. 2.7 V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings Symbol Reference Description Min Typ Max Units
Table 26. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
RCT Resistor unit value (continuous time) –12.2 – k
CSC Capacitor unit value (switched capacitor) –80 –fF
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DC POR, SMP, and LVD Specifications
Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip
Technical Reference Manual for more information on the VLT_CR register.
Table 27. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD must be greater than or
equal to 2.5 V during startup,
reset from the XRES pin, or
reset from watchdog.
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[12]
2.99[13]
3.09
3.20
4.55
4.75
4.83
4.95
V0
V0
V0
V0
V0
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD value for SMP trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.500
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.550
3.02
3.10
3.250
4.64
4.73
4.82
5.00
2.62[14]
3.09
3.16
3.32[15]
4.74
4.83
4.92
5.12
V
V0
V0
V0
V0
V
V
V
Notes
12. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
13. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
14. Always greater than 50 mV above VLVD0.
15. Always greater than 50 mV above VLVD3.
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DC Programming Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
DC I2C Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 28. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
VDDP VDD for programming and erase 4.5 55.5 VThis specification applies
to the functional require-
ments of external
programmer tools
VDDLV Low VDD for verify 2.4 2.5 2.6 VThis specification applies
to the functional require-
ments of external
programmer tools
VDDHV High VDD for verify 5.1 5.2 5.3 VThis specification applies
to the functional require-
ments of external
programmer tools
VDDIWRITE Supply voltage for flash write operation 2.7 5.25 VThis specification applies
to this device when it is
executing internal flash
writes
IDDP Supply current during programming or verify – 5 25 mA
VILP Input low voltage during programming or verify – – 0.8 V
VIHP Input high voltage during programming or verify 2.1 – – V
IILP Input current when applying VILP to P1[0] or P1[1]
during programming or verify
– – 0.2 mA Driving internal pull-down
resistor
IIHP Input current when applying VIHP to P1[0] or P1[1]
during programming or verify
– – 1.5 mA Driving internal pull-down
resistor
VOLV Output low voltage during programming or verify – – VSS + 0.75 V
VOHV Output high voltage during programming or verify VDD – 1.0 – VDD V
FlashENPB Flash endurance (per block) 50,000[16] – – – Erase/write cycles per
block
FlashENT Flash endurance (total)[17] 1,800,000 – – – Erase/write cycles
FlashDR Flash data retention 10 – – Years
Table 29. DC I2C Specifications[18]
Symbol Description Min Typ Max Units Notes
VILI2C Input low level – – 0.3 × VDD V 2.4 V VDD 3.6 V
– – 0.25 × VDD V4.75 V VDD 5.25 V
VIHI2C Input high level 0.7 × VDD – – V 2.4 V VDD 5.25 V
Notes
16. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to
3.6 V, and 4.75 V to 5.25 V.
17. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
18. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
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AC Electrical Characteristics
AC Chip-Level Specifications
These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 30. 5 V and 3.3 V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO24[19] Internal main oscillator (IMO) frequency for
24 MHz
22.8 24 25.2[20,21] MHz Trimmed for 5 V or 3.3 V operation
using factory trim values.
See Figure 10 on page 18.
SLIMO mode = 0.
FIMO6 IMO frequency for 6 MHz 5.5 66.5[20,21] MHz Trimmed for 5 V or 3.3 V operation
using factory trim values.
See Figure 10 on page 18.
SLIMO mode = 1.
FCPU1 CPU frequency (5 V nominal) 0.937 24 24.6[20] MHz SLIMO mode = 0.
FCPU2 CPU frequency (3.3 V nominal) 0.937 12 12.3[21] MHz SLIMO mode = 0.
F48M Digital PSoC block frequency 048 49.2[20,22] MHz Refer to the AC Digital Block
Specifications.
F24M Digital PSoC block frequency 024 24.6[22] MHz
F32K1 ILO frequency 15 32 64 kHz
F32K2 External crystal oscillator –32.768 –kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F32K_U ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C
starts to run, the ILO is not trimmed.
See the System Resets section of
the PSoC Technical Reference
Manual for details on timing this
FPLL PLL frequency –23.986 –MHz Is a multiple (x732) of crystal
frequency.
TPLLSLEW PLL lock time 0.5 –10 ms
TPLLSLEWSLOW PLL lock time for low gain setting 0.5 –50 ms
TOS External crystal oscillator startup to 1% –1700 2620 ms
TOSACC External crystal oscillator startup to
100 ppm
–2800 3800 ms The crystal oscillator frequency is
within 100 ppm of its final value by
the end of the Tosacc period. Correct
operation assumes a properly
loaded 1 µW maximum drive level
32.768 kHz crystal.
3.0 V VDD 5.5 V,
–40 °C TA 85 °C.
tXRST External reset pulse width 10 – – s
Notes
19. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0°C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 67.
20. 4.75 V < VDD < 5.25 V.
21. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
22. See the individual user module datasheets for information on maximum frequencies for user modules.
23. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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DC24M 24 MHz duty cycle 40 50 60 %
DCILO ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 46.8 48.0 49.2[24, 25] MHz Trimmed. Using factory trim values.
FMAX Maximum frequency of signal on row input
or row output.
– – 12.3 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during power-up.
tPOWERUP Time from end of POR to CPU executing
code
–16 100 ms Power-up from 0 V. See the System
Resets section of the PSoC
Technical Reference Manual.
tjit_IMO [26] 24 MHz IMO cycle-to-cycle jitter (RMS) –200 700 ps N = 32
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–300 900 ps
24 MHz IMO period jitter (RMS) –100 400 ps
tjit_PLL [26] 24 MHz IMO cycle-to-cycle jitter (RMS) –200 800 ps N = 32
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–300 1200
24 MHz IMO period jitter (RMS) –100 700
Table 30. 5 V and 3.3 V AC Chip-Level Specifications (continued)
Symbol Description Min Typ Max Units Notes
Notes
24. 4.75 V < VDD < 5.25 V.
25. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
26. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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Table 31. 2.7 V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO12 IMO frequency for 12 MHz 11.5 12 12.7[27, 28] MHz Trimmed for 2.7 V operation using
factory trim values.
See Figure 10 on page 18.
SLIMO mode = 1.
FIMO6 IMO frequency for 6 MHz 5.5 66.5[27, 28] MHz Trimmed for 2.7 V operation using
factory trim values.
See Figure 10 on page 18.
SLIMO mode = 1.
FCPU1 CPU frequency (2.7 V nominal)00.9370303.15[27] MHz0SLIMO mode = 0.
FBLK27 Digital PSoC block frequency
(2.7 V nominal)
012 12.7[27, 28] MHz0Refer to the AC Digital Block
Specifications.
F32K1 ILO frequency 832 96 kHz
F32K_U ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C
starts to run, the ILO is not trimmed.
See the System Resets section of
the PSoC Technical Reference
Manual for details on timing this
tXRST External reset pulse width 10 – – µs
DC12M 12 MHz duty cycle 40 50 60 %
DCILO ILO duty cycle 20 50 80 %
FMAX Maximum frequency of signal on row input
or row output.
– – 12.7 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during power-up.
tPOWERUP Time from end of POR to CPU executing
code
–16 100 ms Power-up from 0 V. See the System
Resets section of the PSoC
Technical Reference Manual.
tjit_IMO[29] 12 MHz IMO cycle-to-cycle jitter (RMS) –400 1000 ps N = 32
12 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–600 1300 ps
12 MHz IMO period jitter (RMS) –100 500 ps
tjit_PLL[29] 12 MHz IMO cycle-to-cycle jitter (RMS) –400 1000 ps N = 32
12 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–700 1300
12 MHz IMO period jitter (RMS) –300 500
Notes
27. 2.4 V < VDD < 3.0 V.
28. Refer to application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
29. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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Figure 12. PLL Lock Timing Diagram
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
Figure 14. External Crystal Oscillator Startup Timing Diagram
24 MHz
FPLL
PLL
Enable
TPLLSLEW
PLL
Gain 0
24 MHz
FPLL
PLL
Enable
TPLLSLEWLOW
PLL
Gain 1
32 kHz
F32K2
32K
Select
TOS
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AC GPIO Specifications
These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Figure 15. GPIO Timing Diagram
Table 32. 5 V and 3.3 V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 12 MHz Normal Strong Mode
tRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns VDD = 4.5 to 5.25 V, 10% to 90%
tFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns VDD = 4.5 to 5.25 V, 10% to 90%
tRiseS Rise time, slow strong mode, Cload = 50 pF 10 27 –ns VDD = 3 to 5.25 V, 10% to 90%
tFallS Fall time, slow strong mode, Cload = 50 pF 10 22 –ns VDD = 3 to 5.25 V, 10% to 90%
Table 33. 2.7 V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 3 MHz Normal strong mode
tRiseF Rise time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 to 3.0 V, 10% to 90%
tFallF Fall time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 to 3.0 V, 10% to 90%
tRiseS Rise time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 to 3.0 V, 10% to 90%
tFallS Fall time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 to 3.0 V, 10% to 90%
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
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AC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Power = high and Opamp bias = high is not supported at 3.3 V and 2.7 V.
Table 34. 5 V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
tROA Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
3.9
0.72
0.62
µs
µs
µs
tSOA Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
5.9
0.92
0.72
µs
µs
µs
SRROA Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.15
1.7
6.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
SRFOA Falling slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.01
0.5
4.0
–
–
–
–
–
–
V/µs
V/µs
V/µs
BWOA Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
ENOA Noise at 1 kHz (Power = medium, Opamp bias = high) –100 –nV/rt-Hz
Table 35. 3.3 V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
tROA Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
3.92
0.72
µs
µs
tSOA Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
5.41
0.72
µs
µs
SRROA Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.31
2.7
–
–
–
–
V/µs
V/µs
SRFOA Falling slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.24
1.8
–
–
–
–
V/µs
V/µs
BWOA Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.67
2.8
–
–
–
–
MHz
MHz
ENOA Noise at 1 kHz (Power = medium, Opamp bias = high) –100 –nV/rt-Hz
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor.
Figure 16. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry.
At high frequencies, increased power level reduces the noise spectrum level.
Table 36. 2.7 V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
tROA Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
3.92
0.72
µs
µs
tSOA Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
–
–
–
–
5.41
0.72
µs
µs
SRROA Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.31
2.7
–
–
–
–
V/µs
V/µs
SRFOA Falling slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.24
1.8
–
–
–
–
V/µs
V/µs
BWOA Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
0.67
2.8
–
–
–
–
MHz
MHz
ENOA Noise at 1 kHz (Power = medium, Opamp bias = high) –100 –nV/rt-Hz
100
1000
10000
0.001 0.01 0.1 1 10 100Fr eq ( kHz)
nV/rtHz
0
0.01
0.1
1.0
10
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Figure 17. Typical Opamp Noise
AC Low Power Comparator Specifications
Table 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V at 25 °C and are for design guidance only.
10
100
1000
10000
0.001 0.01 0.1 1 10 100
Freq (kHz)
nV/rtHz
PH_ BH
PH_ BL
PM_BL
PL_ BL
Table 37. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
tRLPC LPC response time – – 50 µs 50 mV overdrive comparator
reference set within VREFLPC
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AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 38. 5 V and 3.3 V AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
All functions Block input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
Timer Input clock frequency
No capture, VDD 4.75 V – – 50.4 MHz
No capture, VDD < 4.75 V – – 25.2 MHz
With capture – – 25.2 MHz
Capture pulse width 50[30] – – ns
Counter Input clock frequency
No enable input, VDD 4.75 V – – 50.4 MHz
No enable input, VDD < 4.75 V – – 25.2 MHz
With enable input – – 25.2 MHz
Enable input pulse width 50[30] – – ns
Dead Band Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50[30] – – ns
Disable mode 50[30] – – ns
Input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
CRCPRS
(PRS Mode)
Input clock frequency
VDD 4.75 V – – 50.4 MHz
VDD < 4.75 V – – 25.2 MHz
CRCPRS
(CRC Mode)
Input clock frequency – – 25.2 MHz
SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions
50[30] – – ns
Transmitter Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 50.4 MHz
VDD 4.75 V, 1 stop bit – – 25.2 MHz
VDD < 4.75 V – – 25.2 MHz
Receiver Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 50.4 MHz
VDD 4.75 V, 1 stop bit – – 25.2 MHz
VDD < 4.75 V – – 25.2 MHz
Note
30. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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Table 39. 2.7 V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions
Block input clock frequency – – 12.7 MHz 2.4 V < VDD < 3.0 V
Timer Capture pulse width 100[31] – – ns
Input clock frequency, with or without capture – – 12.7 MHz
Counter Enable Input Pulse Width 100[31] – – ns
Input clock frequency, no enable input – – 12.7 MHz
Input clock frequency, enable input – – 12.7 MHz
Dead Band Kill pulse width:
Asynchronous restart mode 20 – – ns
Synchronous restart mode 100[31] – – ns
Disable mode0100[31] – – ns
Input clock frequency – – 12.7 MHz
CRCPRS
(PRS Mode)
Input clock frequency – – 12.7 MHz
CRCPRS
(CRC Mode)
Input clock frequency – – 12.7 MHz
SPIM Input clock frequency – – 6.35 MHz The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS Input clock frequency – – 4.23 MHz
Width of SS_ Negated between transmissions 100[31] – – ns
Transmitter Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Receiver Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Note
31. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
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AC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 40. 5 V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units
tROB Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.5
2.5
µs
µs
tSOB Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.2
2.2
µs
µs
SRROB Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/µs
V/µs
SRFOB Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/µs
V/µs
BWOB Small signal bandwidth, 20mVpp, 3dB BW, 100 pF load
Power = low
Power = high
0.8
0.8
–
–
–
–
MHz
MHz
BWOB Large signal bandwidth, 1Vpp, 3dB BW, 100 pF load
Power = low
Power = high
300
300
–
–
–
–
kHz
kHz
Table 41. 3.3 V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units
tROB Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
3.8
3.8
µs
µs
tSOB Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.6
2.6
µs
µs
SRROB Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/µs
V/µs
SRFOB Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/µs
V/µs
BWOB Small signal bandwidth, 20mVpp, 3dB BW, 100 pF load
Power = low
Power = high
0.7
0.7
–
–
–
–
MHz
MHz
BWOB Large signal bandwidth, 1Vpp, 3dB BW, 100 pF load
Power = low
Power = high
200
200
–
–
–
–
kHz
kHz
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AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 42. 2.7 V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units
tROB Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
4
4
µs
µs
tSOB Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
3
3
µs
µs
SRROB Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
0.4
0.4
–
–
–
–
V/µs
V/µs
SRFOB Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
0.4
0.4
–
–
–
–
V/µs
V/µs
BWOB Small signal bandwidth, 20 mVpp, 3dB BW, 100 pF load
Power = low
Power = high
0.6
0.6
–
–
–
–
MHz
MHz
BWOB Large signal bandwidth, 1 Vpp, 3dB BW, 100 pF load
Power = low
Power = high
180
180
–
–
–
–
kHz
kHz
Table 43. 5 V AC External Clock Specifications
Symbol Description Min Typ Max Units
FOSCEXT Frequency 0.093 –24.6 MHz
–High period 20.6 –5300 ns
–Low period 20.6 – – ns
–Power-up IMO to switch 150 – – s
Table 44. 3.3 V AC External Clock Specifications
Symbol Description Min Typ Max Units
FOSCEXT Frequency with CPU clock divide by 1[32] 0.093 –12.3 MHz
FOSCEXT Frequency with CPU clock divide by 2 or greater[33] 0.186 –24.6 MHz
–High period with CPU clock divide by 1 41.7 –5300 ns
–Low period with CPU clock divide by 1 41.7 – – ns
–Power-up IMO to switch 150 – – s
Notes
32. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
33. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
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AC Programming Specifications
Table 46 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 45. 2.7 V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU clock divide by 1[34] 0.093 –12.3 MHz
FOSCEXT Frequency with CPU clock divide by 2 or greater[35] 0.186 –12.3 MHz
–High period with CPU clock divide by 1 41.7 –5300 ns
–Low period with CPU clock divide by 1 41.7 – – ns
–Power-up IMO to switch 150 – – µs
Table 46. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
tRSCLK Rise time of SCLK 1 – 20 ns
tFSCLK Fall time of SCLK 1 – 20 ns
tSSCLK Data setup time to falling edge of SCLK 40 – – ns
tHSCLK Data hold time from falling edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
tERASEB Flash erase time (block) –20 –ms
tWRITE Flash block write time –80 –ms
tDSCLK Data out delay from falling edge of SCLK – – 45 ns VDD 3.6
tDSCLK3 Data out delay from falling edge of SCLK – – 50 ns 3.0 VDD 3.6
tDSCLK2 Data out delay from falling edge of SCLK – – 70 ns 2.4 VDD 3.0
tERASEALL Flash erase time (Bulk) –20 –ms Erase all blocks and
protection fields at once
tPROGRAM_HOT Flash block erase + flash block write time – – 200[36] ms 0 °C Tj 100 °C
tPROGRAM_COLD Flash block erase + flash block write time – – 400[36] ms –40 °C Tj 0 °C
Notes
34. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
35. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
36. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
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AC I2C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Figure 18. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
Table 47. AC Characteristics of the I2C SDA and SCL Pins for VDD > 3.0 V
Symbol Description Standard-Mode Fast-Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0100 0400 kHz
tHDSTAI2C Hold time (repeated) start condition. After this period, the first clock
pulse is generated
4.0 –0.6 –µs
tLOWI2C Low period of the SCL clock 4.7 –1.3 –µs
tHIGHI2C High period of the SCL clock 4.0 –0.6 –µs
tSUSTAI2C Setup time for a repeated start condition 4.7 –0.6 –µs
tHDDATI2C Data hold time 0 – 0 – µs
tSUDATI2C Data setup time 250 –100[37] –ns
tSUSTOI2C Setup time for stop condition 4.0 –0.6 –µs
tBUFI2C Bus free time between a stop and start condition 4.7 –1.3 –µs
tSPI2C Pulse width of spikes are suppressed by the input filter – – 0 50 ns
Table 48. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V (Fast Mode Not Supported)
Symbol Description Standard-Mode Fast-Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0100 – – kHz
tHDSTAI2C Hold time (repeated) start condition. After this period, the first clock
pulse is generated
4.0 – – – µs
tLOWI2C Low period of the SCL clock 4.7 – – – µs
tHIGHI2C High period of the SCL clock 4.0 – – – µs
tSUSTAI2C Setup time for a repeated start condition 4.7 – – – µs
tHDDATI2C Data hold time 0 – – – µs
tSUDATI2C Data setup time 250 – – – ns
tSUSTOI2C Setup time for stop condition 4.0 – – – µs
tBUFI2C Bus free time between a stop and start condition 4.7 – – – µs
tSPI2C Pulse width of spikes are suppressed by the input filter – – – – ns
I2C_SDA
I2C_SCL
SSr SP
TBUFI2C
TSPI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
START Condition Repeated START Condition STOP Condition
Note
37. A fast-mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Packaging Information
This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, see the emulator pod drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 19. 8-Pin PDIP (300 Mils)
51-85075 *D
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Figure 20. 8-Pin SOIC (150 Mils)
Figure 21. 20-Pin Molded DIP (300 Mils)
51-85066 *H
51-85011 *D
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Figure 22. 20-Pin SSOP (210 Mils)
Figure 23. 20-Pin Molded SOIC (300 Mils)
51-85077 *F
51-85024 *F
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Figure 24. 28-Pin Molded DIP (300 Mils)
Figure 25. 28-Pin SSOP (210 Mils)
51-85014 *G
51-85079 *F
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Figure 26. 28-Pin SOIC (300 Mils)
51-85026 *H
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Figure 27. 32-Pin QFN (Sawn) Package
Important Note For information on the preferred dimensions for mounting QFN packages, see the application note, Application Notes
for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
Figure 28. 56-Pin SSOP (300 Mils)
001-30999 *D
51-85062 *F
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Thermal Impedances Capacitance on Crystal Pins
Solder Reflow Specifications
Table 51 shows the solder reflow temperature limits that must not be exceeded.
Table 49. Thermal Impedances per Package
Package Typical JA[38]
8-pin PDIP 123 °C/W
8-pin SOIC 185 °C/W
20-pin PDIP 109 °C/W
20-pin SSOP 117 °C/W
20-pin SOIC 81 °C/W
28-pin PDIP 69 °C/W
28-pin SSOP 101 °C/W
28-pin SOIC 74 °C/W
32-pin QFN[39] 22 °C/W
Table 50. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
8-pin PDIP 2.8 pF
8-pin SOIC 2.0 pF
20-pin PDIP 3.0 pF
20-pin SSOP 2.6 pF
20-pin SOIC 2.5 pF
28-pin PDIP 3.5 pF
28-pin SSOP 2.8 pF
28-pin SOIC 2.7 pF
32-pin QFN 2.0 pF
Table 51. Solder Reflow Specifications
Package Maximum Peak Temperature (TC)Maximum Time above TC – 5 °C
8-pin PDIP 260 °C 30 seconds
8-pin SOIC 260 °C 30 seconds
20-pin PDIP 260 °C 30 seconds
20-pin SSOP 260 °C 30 seconds
20-pin SOIC 260 °C 30 seconds
28-pin PDIP 260 °C 30 seconds
28-pin SSOP 260 °C 30 seconds
28-pin SOIC 260 °C 30 seconds
32-pin QFN 260 °C 30 seconds
Notes
38. TJ = TA + Power × JA
39. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages
available at www.amkor.com.
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Development Tool Selection
This section presents the development tools available for all
current PSoC device families including the CY8C24x23A family.
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer, used to generate PSoC firmware applications.
PSoC Designer is available free of charge at
http://www.cypress.com and includes a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free ofcharge at
http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with
PSoC Designer. This kit supports in-circuit emulation and the
software interface lets you to run, halt, and single step the
processor and view the content of specific memory locations.
Advance emulation features also supported through PSoC
Designer. The kit includes:
■PSoC Designer software CD
■ICE-Cube in-circuit emulator
■ICE Flex-Pod for CY8C29x66 family
■Cat-5 adapter
■Mini-Eval programming board
■110 ~ 240 V power supply, Euro-Plug adapter
■iMAGEcraft C compiler (registration required)
■ISSP cable
■USB 2.0 cable and Blue Cat-5 cable
■2 CY8C29466-24PXI 28-PDIP chip samples
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit lets you to program PSoC devices
through the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
through a provided USB 2.0 cable. The kit includes:
■MiniProg programming unit
■MiniEval socket programming and evaluation board
■28-pin CY8C29466-24PXI PDIP PSoC device sample
■28-pin CY8C27443-24PXI PDIP PSoC device sample
■PSoC Designer software CD
■Getting Started guide
■USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■Evaluation board with LCD module
■MiniProg programming unit
■28-pin CY8C29466-24PXI PDIP PSoC device sample (2)
■PSoC Designer software CD
■Getting Started guide
■USB 2.0 cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■PSoCEvalUSB board
■LCD module
■MIniProg programming unit
■Mini USB cable
■PSoC Designer and Example Projects CD
■Getting Started guide
■Wire pack
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Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■Modular programmer base
■Three programming module cards
■MiniProg programming unit
■PSoC Designer software CD
■Getting Started guide
■USB 2.0 cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■CY3207 programmer unit
■PSoC ISSP software CD
■110 ~ 240 V power supply, Euro-Plug adapter
■USB 2.0 cable
Accessories (Emulation and Programming)
Table 52. Emulation and Programming Accessories
Part Number Pin Package Flex-Pod Kit[40] Foot Kit[41] Adapter[42]
All non-QFN All non-QFN CY3250-24X23A CY3250-8DIP-FK,
CY3250-8SOIC-FK,
CY3250-20DIP-FK,
CY3250-20SOIC-FK,
CY3250-20SSOP-FK,
CY3250-28DIP-FK,
CY3250-28SOIC-FK,
CY3250-28SSOP-FK
Adapters can be found at
http://www.emulation.com.
Notes
40. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
41. Foot kit includes surface mount feet that can be soldered to the target PCB.
42. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
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Ordering Information
The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes.
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
Table 53. CY8C24x23A PSoC Device Key Features and Ordering Information
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital Blocks
Analog Blocks
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
8-pin (300-mil) DIP CY8C24123A-24PXI 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No
8-pin (150-mil) SOIC CY8C24123A-24SXI 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No
8-pin (150-mil) SOIC
(Tape and Reel)
CY8C24123A-24SXIT 4K 256 No –40 °C to +85 °C 4 6 6 4 2 No
20-pin (300-mil) DIP CY8C24223A-24PXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes
20-pin (210-mil) SSOP CY8C24223A-24PVXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes
20-pin (210-mil) SSOP
(Tape and Reel)
CY8C24223A-24PVXIT 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes
20-pin (300-mil) SOIC CY8C24223A-24SXI 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes
20-pin (300-mil) SOIC
(Tape and Reel)
CY8C24223A-24SXIT 4K 256 Yes –40 °C to +85 °C 4 6 16 8 2 Yes
28-pin (210-mil) SSOP CY8C24423A-24PVXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
28-pin (210-mil) SSOP
(Tape and Reel)
CY8C24423A-24PVXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
28-pin (300-mil) SOIC CY8C24423A-24SXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
28-pin (300-mil) SOIC
(Tape and Reel)
CY8C24423A-24SXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
32-pin (5 × 5 mm 1.00 max)
Sawn QFN
CY8C24423A-24LTXI 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
32-pin (5 × 5 mm 1.00 max)
Sawn QFN (Tape and Reel)
CY8C24423A-24LTXIT 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
56-pin OCD SSOP CY8C24000A-24PVXI[43] 4K 256 Yes –40 °C to +85 °C 4 6 24 10 2Yes
CY 8 C 24 xxx-SPxx
Package Type: Thermal Rating:
PX = PDIP Pb-free C = Commercial
SX = SOIC Pb-free I = Industrial
PVX = SSOP Pb-free E = Extended
LFX/LKX = QFN Pb-free
AX = TQFP Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
43. This part may be used for in-circuit debugging. It is NOT available for production.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 61 of 71
Acronyms
Acronyms Used
Table 54 lists the acronyms that are used in this document.
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Table 54. Acronyms Used in this Datasheet
Acronym Description Acronym Description
AC alternating current MIPS million instructions per second
ADC analog-to-digital converter OCD on-chip debug
API application programming interface PCB printed circuit board
CMOS complementary metal oxide semiconductor PDIP plastic dual-in-line package
CPU central processing unit PGA programmable gain amplifier
CRC cyclic redundancy check PLL phase-locked loop
CT continuous time POR power on reset
DAC digital-to-analog converter PPOR precision power on reset
DC direct current PRS pseudo-random sequence
DTMF dual-tone multi-frequency PSoC® Programmable System-on-Chip
ECO external crystal oscillator PWM pulse width modulator
EEPROM electrically erasable programmable read-only memory QFN quad flat no leads
GPIO general purpose I/O RTC real time clock
ICE in-circuit emulator SAR successive approximation
IDE integrated development environment SC switched capacitor
ILO internal low speed oscillator SLIMO slow IMO
IMO internal main oscillator SMP switch mode pump
I/O input/output SOIC small-outline integrated circuit
IrDA infrared data association SPITM serial peripheral interface
ISSP in-system serial programming SRAM static random access memory
LCD liquid crystal display SROM supervisory read only memory
LED light-emitting diode SSOP shrink small-outline package
LPC low power comparator UART universal asynchronous receiver / transmitter
LVD low voltage detect USB universal serial bus
MAC multiply-accumulate WDT watchdog timer
MCU microcontroller unit XRES external reset
CY8C24123A
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CY8C24423A
Document Number: 38-12028 Rev. *W Page 62 of 71
Document Conventions
Units of Measure
Table 55 lists the units of measures.
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Table 55. Units of Measure
Symbol Units of Measure Symbol Units of Measure
kB 1024 bytes µs microsecond
dB decibels ms millisecond
°C degree Celsius ns nanosecond
fF femto farad ps picosecond
pF picofarad µV microvolts
kHz kilohertz mV millivolts
MHz megahertz mVpp millivolts peak-to-peak
rt-Hz root hertz nV nanovolts
kkilohm V volts
ohm µW microwatts
µA microampere W watt
mA milliampere mm millimeter
nA nanoampere ppm parts per million
pA pikoampere % percent
mH millihenry
Glossary
active high 5. A logic signal having its asserted state as the logic 1 state.
6. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
API (Application
Programming
Interface)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth 1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
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Document Number: 38-12028 Rev. *W Page 63 of 71
bias 1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block 1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy
check (CRC)
A calculation used to detect errors in data communications, typically performed using a linear feedback shift
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger A hardware and software system that allows the user to analyze the operation of the system under development.
A debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band A period of time when neither of two or more signals are in their active state or in transition.
digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
Glossary (continued)
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duty cycle The relationship of a clock period high time to its low time, expressed as a percent.
emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash An electrically programmable and erasable, non-volatile technology that provides users with the programmability
and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power
is off.
Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency The number of cycles or events per unit of time, for a periodic function.
gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect
(LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Glossary (continued)
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CY8C24423A
Document Number: 38-12028 Rev. *W Page 65 of 71
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal The reference to a circuit containing both analog and digital techniques and components.
modulator A device that imposes a signal on a carrier.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port A group of pins, usually eight.
power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of
hardware reset.
PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM)
An output in the form of duty cycle which varies as a function of the applied measurand.
RAM An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register A storage device with a specific capacity, such as a bit or byte.
reset A means of bringing a system back to a know state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Glossary (continued)
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shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a
high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains
unchanged until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V.
VSS A name for a power net meaning “voltage source.” The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Glossary (continued)
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Document Number: 38-12028 Rev. *W Page 67 of 71
Errata
This section describes the errata for the CY8C24xxxA device family. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
CY8C24123A Qualification Status
Product Status: Production
CY8C24123A Errata Summary
The following table defines the errata applicability to available CY8C24123A family devices.
1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes
■Problem Definition
Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product
usage between 0 and 70 °C.
■Parameters Affected
The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70 °C and within the upper and
lower datasheet temperature range is ±5%.
■Trigger Condition(S)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ±2.5% when
operated beyond the temperature range of 0 to +70 °C.
■Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■Fix Status
Silicon fix is not planned. The workaround mentioned above should be used.
Part Number Ordering Information
CY8C24123A CY8C24123A-24PXI
CY8C24123A-24SXI
CY8C24123A-24SXIT
CY8C24223A-24PXI
CY8C24223A-24PVXI
CY8C24223A-24PVXIT
CY8C24223A-24SXI
CY8C24223A-24SXIT
CY8C24423A-24PVXI
CY8C24423A-24PVXIT
CY8C24423A-24SXI
CY8C24423A-24SXIT
CY8C24423A-24LFXI
CY8C24423A-24LTXI
CY8C24423A-24LTXIT
CY8C24000A-24PVXI
Items Part Number Silicon Revision Fix Status
[1.]. Internal Main Oscillator (IMO) Tolerance Deviation at
Temperature Extremes
CY8C24123A *A No silicon fix planned.
Workaround is
required.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 68 of 71
Document History Page
Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip
Document Number: 38-12028
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 236409 SFV See ECN New silicon and new document – Preliminary datasheet.
*A 247589 SFV See ECN Changed the title to read “Final” datasheet. Updated Electrical Specifications
chapter.
*B 261711 HMT See ECN Input all SFV memo changes. Updated Electrical Specifications chapter.
*C 279731 HMT See ECN Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add
Solder Reflow Peak Temperature table. Clean up pinouts and fine tune wording
and format throughout.
*D 352614 HMT See ECN Add new color and CY logo. Add URL to preferred dimensions for mounting
MLF packages. Update Transmitter and Receiver AC Digital Block Electrical
Specifications. Re-add ISSP pinout identifier. Delete Electrical Specification
sentence re: devices running at greater than 12 MHz. Update Solder Reflow
Peak Temperature table. Fix CY.com URLs. Update CY copyright.
*E 424036 HMT See ECN Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN
E-Pad dimensions and rev. *A. Add ISSP note to pinout tables. Update typical
and recommended Storage Temperature per industrial specs. Add OCD
non-production pinout and package diagram. Update CY branding and QFN
convention. Update package diagram revisions.
*F 521439 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new
Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table.
*G 2256806 UVS /
PYRS
See ECN Added Sawn pin information.
*H 2425586 DSO /
AESA
See ECN Corrected Ordering Information to include CY8C24423A-24LTXI and
CY8C24423A-24LTXIT
*I 2619935 OGNE /
AESA
12/11/2008 Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC®
Programmable System-on-Chip™”
Updated package diagram 001-30999 to *A.
Added note on digital signaling in DC Analog Reference Specifications on page
28.
Added Die Sales information note to Ordering Information on page 60.
*J 2692871 DPT /
PYRS
04/16/2009 Updated Max package thickness for 32-pin QFN package
Formatted Notes
Updated “Getting Started” on page 7
Updated “Development Tools” on page 8 and “Designing with PSoC Designer”
on page 9
*K 2762168 JVY /
AESA
06/25/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified FIMO6 and TWRITE specifications.
Replaced TRAMP (time) specification with SRPOWER_UP (slew rate) specifi-
cation.
Added note [9] to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP
, TERASEALL, TPROGRAM_HOT
, and
TPROGRAM_COLD specifications.
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 69 of 71
*L 2897881 MAXK /
NJF
03/23/2010 Add “More Information” on page 2. Update unit in Table 10-28 and Table 39 of
SPIS Maximum Input Clock Frequency from ns to MHz. Update revision of
package diagrams for 8 PDIP, 8 SOIC, 20 PDIP, 20 SSOP, 20 SOIC, 28 PDIP,
28 SSOP, 28 SOIC, 32 QFN. Updated Cypress website links. Removed
reference to PSoC Designer 4.4. Updated 56-Pin SSOP definitions and
diagram. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum
Ratings. Updated 5 V DC Analog Reference Specifications table. Updated
Note in Packaging Information. Added Note 29. Updated Solder Reflow
Specifications table. Removed Third Party Tools and Build a PSoC Emulator
into your Board. Removed inactive parts from Ordering Information. Update
trademark info. and Sales, Solutions, and Legal Information.
*M 2942375 VMAD 06/02/2010 Updated content to match current style guide and datasheet template.
No technical updates.
*N 3032514 NJF 09/17/10 Added PSoC Device Characteristics table.
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Analog reference tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*O 3098766 YJI 12/01/2010 No technical updates.
Completing Sunset Review.
*P 3351721 YJI 08/31/2011 Full annual review of document. No changes are required.
*Q 3367463 BTK / GIR 09/22/2011 Updated text under DC Analog Reference Specifications on page 28.
Removed package diagram spec 51-85188 as there is no active MPN using
this outline drawing.
The text “Pin must be left floating” is included under Description of NC pin in
Table 5 on page 13 and Table 6 on page 14.
Updated Table 51 on page 57 to give more clarity.
Removed Footnote #35.
*R 3598291 LURE /
XZNG
04/24/2012 Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
*S 3991993 PMAD 05/08/2013 Updated Packaging Information:
spec 51-85066 – Changed revision from *E to *F.
spec 51-85014 – Changed revision from *F to *G.
spec 51-85026 – Changed revision from *F to *G.
spec 001-30999 – Changed revision from *C to *D.
spec 51-85062 – Changed revision from *E to *F.
Updated Reference Documents (Removed 001-17397 spec, 001-14503 spec
related information).
Added Errata.
Document History Page (continued)
Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip
Document Number: 38-12028
Revision ECN Orig. of
Change
Submission
Date Description of Change
CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *W Page 70 of 71
*T 4066332 PMAD 07/17/2013 Added Errata Footnotes (Note 1, 19).
Updated PSoC Functional Overview:
Updated PSoC Core:
Added Note 1 and referred the same note in 4th paragraph in PSoC Core.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Chip-Level Specifications:
Added Note 19 and referred the same note in FIMO24 parameter.
Updated minimum and maximum values of FIMO24 parameter.
Updated AC Digital Block Specifications:
Replaced all instances of maximum value “49.2” with “50.4” and “24.6” with
“25.2” in Table 38.
Updated to new template.
*U 4479672 RJVB 08/20/2014 Updated Packaging Information:
Updated Packaging Dimensions:
spec 51-85011 – Changed revision from *C to *D.
spec 51-85024 – Changed revision from *E to *F.
spec 51-85026 – Changed revision from *G to *H.
Updated Errata:
Updated CY8C24123A Errata Summary:
Updated details in “Fix Status” column in the table.
Updated details in “Fix Status” bulleted point below the table.
Completing Sunset Review.
*V 4622083 RKRM 01/13/2015 Added More Information.
*W 5688158 XKJ 05/03/2017 Updated Packaging Information:
Updated Packaging Dimensions:
spec 51-85066 – Changed revision from *G to *H.
Updated Ordering Information:
Updated part numbers.
Updated Errata:
Updated Part Numbers Affected:
Updated part numbers.
Updated to new template.
Document History Page (continued)
Document Title: CY8C24123A/CY8C24223A/CY8C24423A, PSoC® Programmable System-on-Chip
Document Number: 38-12028
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document Number: 38-12028 Rev. *W Revised May 3, 2017 Page 71 of 71
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
CY8C24123A
CY8C24223A
CY8C24423A
© Cypress Semiconductor Corporation, 2004–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
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