Product Brief
April 2000
Features
■The
StarPro
2000 (see Figure 1), based on three
SuperCore
™ quad-MAC DSP cores, provides the
following:
— 3600 MMACs (million multiply and accumulates)
per second at 300 MHz.
— Processes 64 full-duplex speech channels
(encode and decode) with associated echo can-
cellation and DTMF processing without external
memory—any cellular vocoders of the GSM,
CDMA, and TDMA standards.
— Processes 64 data channels (V.90 and V.17
encode and decode) with ECDC and the associ-
ated fallbacks.
— A unique flexible solution for communications
infrastructure.
— The most effective cost-per-channel solution.
■Each
SuperCore
macrocell (see Figure 2), based on
the
StarCore
* SC140 quad-MAC DSP core, pro vides
the following:
— 1200 MMACS/3000 RISC MIPS at
300 MHz.
— Four MACs per cycle.
— 8 Kbytes instruction cache, 8 Kbytes data cache.
— 16 Kbytes local data memory.
— Cache management unit.
— Programmable interrupt controller (PIC) with
32 levels of priority.
— Debug port with instruction trace.
■768 Kbytes shared SRAM:
— A unified memory space.
— Provides system memory for instruction and data
storage.
■Proprietary
Daytona
† bus for system interconnec-
tion:
— 32-bit address, 128-bit split-transaction data bus
that operates at the DSP core’s frequency.
— Connects three
SuperCore
macr ocells to system
memory.
— Designed for high speed with low latency.
— User-programmable arbitration.
— Includes system debug capability.
■Three serial I/O units (SIU):
— Compatible with TDM highways such as E1/T1
and ST-bus.
— Function as hardware support for µ-law and A-law
companding.
— Support buff ering of TDM data.
— Each SIU is supported by two DMA channels.
■One parallel interface unit (PIU):
— Provides the interface to off-chip peripherals or
host micr oproc es s or.
— A glueless interface to the
Motorola
‡ Power-
QUICC II 60x or local bus.
— Synchronous burst transfers supported for maxi-
mum throughput.
— A 32-bit address bus, 32-bit data bus, passive
parallel port with flexible addressing modes.
— Buffered to minimize external device overhead.
■Two 32-bit external memory interface units (MIU):
— Provide the interface to off-chip peripherals and
memory.
— Compatible with synchronous or asynchronous
memories.
— A 28-bit address bus, 32-bit data bus, active par-
allel port.
■Eight memory-to-memory DMA channels (MMT):
— Allow block memory transfers anywhere in the
memory space.
— Can be utili zed by an y DSP core.
*
StarCore
is a trademark of Motorola, Inc.
†
Daytona
is a trademark of AT&T.
‡
Motorola
is a registered trademark of Motorola, Inc.
StarPro
™
2000
Product Brief
April 2000
StarPro
2000
2
Features (continued)
■Six timers:
— Six 32-bit timers are clocked by the PLL.
— One-shot operation or auto-repeat.
— Provide an interrupt source to any DSP core.
■General-purpose bit I/O unit (BIU):
— 16 general-purpose pins, user-programmable as
inputs or outputs.
— Acce ssible by any DSP core.
■Power diss ipa tio n:
— 1.5 W internal at full speed and 1.5 V.
— I/O operating voltage of 3.3 V or 2.5 V nominal.
■Phase-lock loop (PLL) to allow full-speed operation
from a slower external clock:
— All three cores operate at the same frequency.
■System-on-chip de velopment tools support under
Lucent’s
LUxWORKS
™ debugging environment:
—
Complete software generation system featuring
the
StarCore
C-compiler; assembler and linker;
SC140 simulator; and a comprehensive set of C-
call able library functions.
— Integrated system-lev el development tools for both
algorithm development and hardware/software co-
verification.
—
Hardware development platforms and on-chip , in-
circuit emulation capabilities through Lucent’s Tar-
getServe JTAG communication system featuring
DART for real-time data collection.
■Packaging options:
— 516 PBGAM1T (31 mm x 31 mm, 1.00 mm ball
pitch).
Description
The
StarPro
2000 is a 16-bit digital signal processor
(DSP) developed as a flexible solution for multichannel
processing in any communications infrastructure sys-
tem: wireless, wireline, and packet based networks.
This is the first Lucent product based on
StarCore
SC140 DSP core, and the first product of the
StarPro
portfolio.
The
StarPro
2000 is optimized for infrastructure appli-
cati ons such as wirel ine VoIP gate w ays , remote a ccess
servers, wireless mobile switching centers, and radio
network controllers. The three SIUs provide high band-
width TDM access and make it easy f or the device to fit
switch applications. The MIUs provide access to e xter-
nal memory, peripherals, and coprocessors. The PIU is
a passive interface allowing the entire DSP memory
space to be acce ssed b y a host proc es sor (e . g., Powe r-
QUICC). The PIU I/O is buffered with FIFOs to allow
higher bandwidth when performing block transfers.
Because the
StarCore
SC140 DSP core has demon-
strated excellent contr ol-c ode effic ie ncy, the
StarPro
2000 offers the ability to execute a mix of control and
DSP functions on the same device. Without changing
the hardware architecture of the device, tasks can be
dynamically allocated across the three cores of the
device. For example, in a data application, two of the
DSP cores can process multichannel FAX/data modem
pump tasks while, the third core can process multi-
channel data-link (AT, V.42, V.42bis) tasks. In a voice-
only application, all three cores process multichannel
speech and ec ho cance ll ati on.
An industry-v erified RTOS offered through ENEA can
be used to coordinate the tasks between the cores.
Because all three SC140 cores share memory and I/O
(see Figure 1), the user has flexibility in system parti-
tioning, which can change on-the-fly. To summarize,
the
StarPro
2000 is a flexib le platform which can pro-
cess TDM and packet data flow with no DSP bottle-
necks, and offers high-channel density with low power
consumption.
For wireless base stations, Lucent provides a low risk
migration path from discrete ASICs, coprocessors, and
StarPro
2000 DSPs to an integrated system-on-a-chip
solution.
StarPro
2000 allows equipment manufactur-
ers to rapidly implement a system-on-a-chip solution
that increases system performance (lower latency and
lower power) and provides optimal cost savings. The
PIU (see Figure 1) is a passive interface allowing the
entire
StarPro
2000 memory space to be accessed by
an ASIC. A user can start with a separate DSP/ASIC
architecture, and then combine these in a simple way
by leaving the original I/O interf aces intact, or in a more
advanced way by bridging the ASIC onto the
Daytona
bus directly. The latter is one of the key advantages of
the
Daytona
system bus, which provides high-band-
width, scalability, and heterogeneous device support.
The
StarPro
2000 offers several system-on-a-chip
implementations at different stages of an architecture
definition.
Product Brief
April 2000
StarPro
2000
3
Block Diagram
Figure 1.
StarPro
2000 Conceptual Block Diagram
BIU0
THREE
TIMERS
MIU0
DAYTONA
BUS
ARBITRATOR
DAYTONA
BUS
ANALYSIS
DAYTONA
BUS†
StarPro2000
ADDRESS
DATA
CONTROL
IOBITS
128
TO
TDM
HIGHWAY
OR
OTHER
DSPs
TO
COPROCESSOR
ASICs
OR
HOST
TO
EXTERNAL
MEMORY
AND
PERIPHERALS
ADDRESS
DATA
CONTROL
32
32
18
26
32
19
8
4 KB
SIU0
CLOCK
SYNC
DATA
3
2
2
CLOCK
SYNC
DATA
3
2
2
4
SWT DMA
6-CHANNEL
SIU1
SIU2
PIU
4-CHANNEL
MMT DMA
INT
BOOT
ROM
SYSTEM
CONTROL
† The
Daytona
bus includes a 128-bit data bu s and a 32-bit address bus.
CKI
RSTN
BOOT
TRAP
DAYTONA
BUS INTERFACE
DAYTONA
BUS INTERFACE
MIM0
PIM
BIU1
THREE
TIMERS
MIU1
IOBITS
ADDRESS
DATA
CONTROL
26
32
19
8
4-CHANNEL
MMT DM A
DAYTONA
BUS INTERFACE
MIM1
CLOCK
SYNC
DATA
3
2
2
JTAG/
EoNCE
2
24
8CONTROL
UNIT
768 KB
PROGRAM
AND DATA
SYSTEM
MEMORY
DAYTONA
BUS
INTERFACE
PEGASUS
SUPERCORE
2
4 MAC
PEGASUS
SUPERCORE
1
4 MAC
PEGASUS
SUPERCORE
0
4 MAC
PROCESSOR
Product Brief
April 2000
StarPro
2000
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
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1-800-372-2447, FAX 610-712-41 06 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
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Tel. (65) 778 8833, FAX (65) 777 7495
CHIN A: Microelectron ic s Gr oup, Lu c ent Techno logies (Chi na) C o., Ltd., A-F2, 23/F, Zao Fong Uni verse Building, 1800 Zhong Shan Xi Road , S hanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Mu ni ch), UNITED KIN G DOM: (44) 1344 865 900 (Ascot),
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ITALY : (39) 02 6608131 (Milan), SPAIN: ( 34) 1 807 1441 (Madrid)
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
April 2000
PB00-010WTEC (Replaces PN00-055WTEC)
Lucent Technologies Inc. reser ves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a re sult of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
StarPro, SuperCore,
and
LUxWORKS
are trademarks of Lucent Technologies.
Block Diagram (continued)
Figure 2. The Lucent
SuperCore
Macrocell Block Diagram
5-9434 (F)
JTAG-EONCETRACE BUFF ER CLOCK CONFIG I/F PIC
STARCORE
SC140S
DCACHE
WRITE BUFF ER ICACHE CACHE MGR BRIDGE
DAYTONA
SUPERBUS INTERFACE
LPB
AND
LOCAL MEMORY
DAYTONA
SUPER BUS 32-bit ADDRESS, 128-bit DATA
XA—32-bit ADDRESS, 64-bit DATA
P—32-bit ADDRESS,
128-bit DATA
SUPERCORE
INTERFACE
XB—32-bit ADDRESS, 64-bit DATA
