1
Data sheet acquired from Harris Semiconductor
SCHS141H
Features
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Pinout
CD54HC112, CD54HCT112 (CERDIP)
CD74HC112 (PDIP, SOIC, SOP, TSSOP)
CD74HCT112 (PDIP)
TOP VIEW
Description
The ’HC112 and ’HCT112 utilize silicon-gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.
The HCT logic family is functionally as well as pin-
compatible with the standard LS logic family.
.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1CP
1K
1J
1S
1Q
1Q
GND
2Q
VCC
2R
2CP
2K
2J
2S
2Q
1R
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC112F3A -55 to 125 16 Ld CERDIP
CD54HCT112F3A -55 to 125 16 Ld CERDIP
CD74HC112E -55 to 125 16 Ld PDIP
CD74HC112MT -55 to 125 16 Ld SOIC
CD74HC112M96 -55 to 125 16 Ld SOIC
CD74HC112NSR -55 to 125 16 Ld SOP
CD74HC112PW -55 to 125 16 Ld TSSOP
CD74HC112PWR -55 to 125 16 Ld TSSOP
CD74HC112PWT -55 to 125 16 Ld TSSOP
CD74HCT112E -55 to 125 16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC112, CD74HC112,
CD54HCT112, CD74HCT112
Dual J-K Flip-Flop with Set and Reset
Negative-Edge Trigger
[
/Title
(
CD74
H
C112
,
C
D74
H
CT11
2
)
/
Sub-
j
ect
(
Dual
J
-K
F
lip-
F
lop
w
ith
S
etand
R
eset
N
ega-
March 1998 - Revised October 2003
2
Functional Diagram
TRUTH TABLE
INPUTS OUTPUTS
S R CP J K Q Q
LHXXXHL
HLXXXLH
LLX X X H (Note 1) H (Note 1)
HH↓L L No Change
HH↓HLHL
HH↓LHLH
HH↓H H Toggle
H H H X X No Change
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care
↓= High-to-Low Transition
NOTE:
1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.
1S
2S
2R
4
10
5
61Q
1Q
14
15
1R
2K 12
13
9
72Q
2Q
2CP
F/F 1
F/F 2
GND = 8
VCC = 16
2J 11
1K 2
1
1CP
1J 3
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time, tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
Package Thermal Impedance, θJA (see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W
D (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature (Hermetic Package or Die) . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
---------V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
---------V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 4 - 40 - 80 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage CMOS Loads VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC
and
GND
- 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 4 - 40 - 80 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 3) VCC
- 2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
1S, 2S 0.5
1K, 2K 0.6
1R, 2R 0.65
1J, 2J, 1CP, 2CP 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Pulse Width CP tW- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
5
Pulse Width R, St
W- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Setup Time J, K, to CP tSU - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Hold Time J, K, to CP tH-20--0-0-ns
4.5 0 - - 0 - 0 - ns
60--0-0-ns
Removal Time R to CP, S to CP tREM - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
CP Frequency fMAX - 2 6 - - 5 - 4 - MHz
4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz
HCT TYPES
Pulse Width CP tSU - 4.5 16 - - 20 - 24 - ns
Pulse Width R, St
W- 4.5 18 - - 23 - 27 - ns
Setup Time J, K, to CP tH- 4.5 16 - - 20 - 24 - ns
Hold Time J, K, to CP tREM - 4.5 3 - - 3 - 3 - ns
Removal Time R to CP, S to CP tW- 4.5 20 - - 25 - 30 - ns
CP Frequency fMAX - 4.5 30 - - 25 - 20 - MHz
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,
CP to Q, Q tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns
CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 30 - 37 - 45 ns
Propagation Delay,
S to Q, QtPLH, tPHL CL= 50pF 2 - - 155 - 195 - 235 ns
CL= 50pF 4.5 - - 31 - 39 - 47 ns
CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 26 - 33 - 40 ns
Propagation Delay,
R to Q, QtPLH, tPHL CL= 50pF 2 - - 180 - 225 - 270 ns
CL= 50pF 4.5 - - 36 - 45 - 54 ns
CL= 15pF 5 - 15 - ----ns
CL= 50pF 6 - - 31 - 38 - 46 ns
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
6
Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF 6 - - 13 - 16 - 19 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
CP Frequency fMAX CL = 15pF 5 - 60 - ----MHz
Power Dissipation Capacitance
(Notes 4, 5) CPD - 5-12-----pF
HCT TYPES
Propagation Delay,
CP to Q, Q tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - ----ns
Propagation Delay,
S to Q, QtPLH, tPHL CL= 50pF 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - ----ns
Propagation Delay,
R to Q, QtPLH, tPHL CL= 50pF 4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 14 - ----ns
Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
CP Frequency fMAX CL = 15pF 5 - 60 - ----MHz
Power Dissipation Capacitance
(Notes 4, 5) CPD - 5-20-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD = CPD VCC2 fi + ΣCLfowhere fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
7
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms (Continued)
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8970201EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
CD54HC112F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT112F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC112E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC112EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC112M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HC112PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC112PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT112E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT112EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC112, CD54HCT112, CD74HC112, CD74HCT112 :
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC112M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC112NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC112PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC112PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC112M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC112NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC112PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC112PWT TSSOP PW 16 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
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