6-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT
1
FEATURES APPLICATIONS
NOMINAL SIZE = 0.87 i x 0.5 i
(22,1 mm x 12,57 mm)
DESCRIPTION
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007www.ti.com
ADJUST POWER MODULE
•Telecom, Industrial, and General-Purpose2
•Up to 6-A Output Current
Circuits•12-V Input Voltage•Wide-Output Voltage Adjust(1.2 V to 5.5 V)/(0.8 V to 1.8 V)•Efficiencies up to 93%•200 W/in
3
Power Density•On/Off Inhibit•Undervoltage Lockout•Operating Temperature: – 40 °C to 85 °C•Auto-Track™ Sequencing•Output Overcurrent Protection(Nonlatching, Auto-Reset)•Safety Agency Approvals:UL/IEC/CSA-22.2 60950-1•Point-of-Load Alliance ( POLA™) Compatible
The PTH12050 series is the smallest non-isolated power modules that features Auto-Track™ Sequencing.Auto-Track simplifies the sequencing of supply voltages in power systems by enabling modules to track eachother, or any other external voltage, during power up and power down.
Although small in size (0.87 inches ×0.5 inches), these modules are rated for up to 6 A of output current, andare an ideal choice in applications where space, performance, and a power-up sequencing capability areimportant attributes.
The series operates from an input voltage of 12-V to provide step-down conversion to a wide range of outputvoltages. The output voltage of the W-suffix device may set to any voltage over the adjust range, 1.2 V to 5.5 V.The L-suffix device has an adjustment range of 0.8 V to 1.8 V. The output voltage is set within the adjustmentrange using a single external resistor.
Other operating features include an on/off inhibit, output voltage adjust (trim), and output overcurrent protection.For high efficiency, these parts employ a synchronous rectifier output stage.
Target applications include telecom, industrial, and general purpose circuits, including low-power dual-voltagesystems that use the TMS320™ DSP family, microprocessor, ASIC, or FPGA.
For start-up into a non-prebiased output, review page 14 in the Application Information section.
For start-up into a prebiased output, review page 18 in the Application Information section.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Auto-Track, POLA, TMS320 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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VI
Inhibit
GND GND
VO
Track
C1
100 F
(Required)
mR ,1%
(Required)
SET
C2
10 F
Ceramic
m
C3
100 F
(Optional)
m
PTH12050
(TopView)
1
5
2
3
4
6
ABSOLUTE MAXIMUM RATINGS
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
STANDARD APPLICATION
A. R
SET
= Required to set the output voltage higher than the minimum value. See the Application Information section forvalues.
B. C2 = 10 µF ceramic capacitor. Required for output voltages 3.3 V or higher.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or seethe TI website at www.ti.com.
Over operating free-air temperatur range unless otherwise notedAll voltages are with respect to GND
UNIT
V
I
Track input voltage – 0.3 V to V
I
+0.3 VT
A
Operating temperature Over V
I
range – 40 °C to 85 °Crange
Surface temperature of module body or pins PTH12050WAH 260 °C
(1)T
wave
Wave solder temperature
(5 ＝seconds)
PTH12050WAS 235 °C
(1)T
reflow
Solder reflow temperature Surface temperature of module body or pins
PTH12050WAZ 260 °C
(1)
T
stg
Storage temperature – 55 °C to 125 °C
(2)
Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 msec, ＝Sine, mounted 500 GMechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20 GWeight 2.9 gramsFlammability Meets UL 94V-O
(1) During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the statedmaximum.
(2) The shipping tray or tape and reel cannot be used to bake parts at temperatures higher than 65 °C.
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ELECTRICAL CHARACTERISTICS
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
T
A
= 25 °C; V
I
= 12 V; V
O
= 3.3 V; C1 = 100 µF, C2 = 10 µF, C3 = 0 µF, and I
O
= I
O(max)
(unless otherwise stated)
PARAMETER TEST CONDITIONS PTH12050W UNIT
MIN TYP MAX
85 °C, 400 LFM airflow 0 6
(1)
AI
O
Output current Over ΔV
adj
range
60 °C, natural convection 6
(1)
A
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
o tol
Set-point voltage tolerance ± 2
(2)
%V
o
ΔReg
temp
Temperature variation – 40 °C <T
A
< 85 °C ± 0.5 %V
o
ΔReg
line
Line regulation Over V
I
range ± 5 mV
ΔReg
load
Load regulation Over I
O
range ± 5 mV
ΔReg
tot
Total output variation Includes set-point, line, load, – 40 °C≤T
A
≤85 °C ± 3
(2)
%V
o
ΔV
adj
Output voltage adjust range Over V
I
range 1.2 5.5
(1)
V
R
SET
= 280 Ω, V
O
= 5 V
(1)
93%
R
SET
= 2 k Ω, V
O
= 3.3 V
(1)
91%
R
SET
= 4.32 k Ω, V
O
= 2.5 V 89%
ηEfficiency I
O
= 5 A R
SET
= 8.06 k Ω, V
O
= 2 V 88%
R
SET
= 11.5 k Ω, V
O
= 1.8 V 87%
R
SET
= 24.3 k Ω, V
O
= 1.5 V 86%
R
SET
= open circuit, V
O
= 1.2 V 84%
V
O
≤2.5 V 25 mVppV
r
V
O
ripple (peak-to-peak) 20-MHz bandwidth
V
O
> 2.5 V 1 %V
o
I
o
trip Overcurrent threshold Reset, followed by auto-recovery 14 A
t
tr
1 A/µs load step, Recovery time 70 µsTransient response 50 to 100% I
O
max,ΔV
tr
V
O
over/undershoot 100 mVC3 = 100 µF
I
IL
track Track input current (pin 2) Pin to GND – 0.13
(3)
mA
dV
track
/dt Track slew rate capability C
O
≤C
O
(max) 1 V/ms
V
I
increasing 9.5 10.4UVLO Under-voltage lockout VV
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(3)
VV
IL
Inhibit Control (pin 4) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 4 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 4) to GND, Track (pin 2) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 260 320 380 kHz
External input capacitance, C1 100
(4)
µF
Nonceramic 0 100
(5)
3300
(6)
Capacitance value µFExternal output capacitance, C3 Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(7)
5.9MTBF Reliability Per Bellcore TR-332 50% stress, T
A
= 40 °C, ground benign
10
6
Hr
(1) See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating.(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has atolerance of 1% with 100 ppm/ °C or better temperature stability.(3) This control pin has an internal pull-up to the input voltage V
I
(7.5 V for pin 2). If it is left open-circuit, the module operates when inputpower is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Donot place an external pull-up on this pin. For further information, see the related application note.(4) A 100 µF electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mArms of ripple current. An additional 10 µF ceramic capacitor is required for output voltages 3.3 V and higher. For further information, seethe related application information on capacitor selection.(5) An external output capacitor is not required for basic operation. Adding 100 µF of distributed capacitance at the load improves thetransient response.(6) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using avoltage supervisor, C
O(max)
is reduced to 2200 μF. See the application notes for further guidance.(7) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ωas the minimum when using max-ESR valuesto calculate.
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ELECTRICAL CHARACTERISTICS
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
T
A
= 25 °C; V
I
= 12 V; V
O
= 1.8 V; C1 = 100 µF, C2 = 10 µF, C3 = 0 µF, and I
O
= I
O(max)
(unless otherwise stated)
PARAMETER TEST CONDITIONS PTH12050L UNIT
MIN TYP MAX
85 °C, 400 LFM airflow 0 6
(1)
AI
O
Output current Over ΔV
adj
range
60 °C, natural convection 6
(1)
A
V
I
Input voltage range Over I
O
range 10.8 13.2 V
V
Otol
Set-point voltage tolerance ± 2
(2)
%V
o
ΔReg
temp
Temperature variation – 40 °C <T
A
< 85 °C ± 0.5 %V
o
ΔReg
line
Line regulation Over V
I
range ± 5 mV
ΔReg
load
Load regulation Over I
O
range ± 5 mV
ΔReg
tot
Total output variation Includes set-point, line, load, – 40 °C≤T
A
≤85 °C ± 3
(2)
%V
o
ΔReg
adj
Output voltage adjust range Over V
I
range 0.8 1.8 V
R
SET
= 130 Ω, V
O
= 1.8 V 88%
R
SET
= 3.57 k Ω, V
O
= 1.5 V 87%
ηEfficiency I
O
= 5 A R
SET
= 12.1 k Ω, V
O
= 1.2 V 85%
R
SET
= 32.4 k Ω, V
O
= 1 V 83%
R
SET
= open circuit, V
O
= 0.8 V 81%
V
O
> 1 V 30V
r
V
o
ripple (peak-to-peak) 20-MHz bandwidth mVppV
O
≤1 V 20
I
o
trip Overcurrent threshold Reset, followed by auto-recovery 14 A
t
tr
1 A/µs load step, Recovery time 70 µsTransient response 50 to 100% I
O(max)
,ΔV
tr
V
O
over/undershoot 100 mVC
3
= 100 µF
I
IL
track Track input current (pin 2) Pin to GND – 0.13
(3)
mA
dV
track
/dt Track slew rate capability C
O
≤C
O(max)
1 V/ms
V
I
increasing 9.5 10.4UVLO Undervoltage lockout VV
I
decreasing 8.8 9
V
IH
Input high voltage, Referenced to GND Open
(3)
VV
IL
Inhibit control (pin 4) Input low voltage, Referenced to GND – 0.2 0.5
I
IL
Input low current, Pin 4 to GND 0.24 mA
I
I
Input standby current Inhibit (pin 4) to GND, Track (pin 2) open 10 mA
f
s
Switching frequency Over V
I
and I
O
ranges 200 250 300 kHz
External input capacitance, C1 100
(4)
µF
Nonceramic 0 100
(5)
3300
(6)
Capacitance value µFExternal output capacitance, C3 Ceramic 0 300
Equivalent series resistance (nonceramic) 4
(7)
5.9MTBF Reliability Per Bellcore TR-332 50% stress, T
A
= 40 °C, ground benign
10
6
Hr
(1) See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating.(2) The set-point voltage tolerance is affected by the tolerance and stability of R
SET
. The stated limit is unconditionally met if R
SET
has atolerance of 1% with 100 ppm/ °C or better temperature stability.(3) This control pin has an internal pull-up to the input voltage V
I
(7.5 V for pin 2). If it is left open-circuit, the module operates when inputpower is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Donot place an external pull-up on this pin. For further information, see the related application note.(4) A 100 µF electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mArms of ripple current. An additional 10 µF ceramic capacitor is required for output voltages 3.3 V and higher. For further information, seethe related application information on capacitor selection.(5) An external output capacitor is not required for basic operation. Adding 100 µF of distributed capacitance at the load improves thetransient response.(6) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using avoltage supervisor, C
O
(max) is reduced to 2200 μF. See the application notes for further guidance.(7) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m Ωas the minimum when using max-ESR valuesto calculate.
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DEVICE INFORMATION
PTHXX050
(Top View)
1
5
2
3
4
6
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Terminal Functions
TERMINAL
DESCRIPTIONNAME NO.
V
I
3 The positive input voltage power node to the module, which is referenced to common GND.V
O
6 The regulated positive power output with respect to the GND node.This is the common ground connection for the V
I
and V
O
power connections. It is also the 0-V
DC
reference for theGND 1
control inputs.A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of the moduleto a value higher than its lowest value. The temperature stability of the resistor should be 100 ppm/ °C (or better).V
O
Adjust 5 The set-point range is 1.2 V to 5.5 V for W-suffix devices, and 0.8 V to 1.8 V for L-suffix devices. The resistor valuerequired for a given output voltage may be calculated using a formula. If left open circuit, the output voltage defaultsto its lowest value. For further information on output voltage adjustment, see the related application note.The specification table gives the preferred resistor values for a number of standard output voltages.The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level groundsignal to this input disables the module ’ s output and turns off the output voltage. When the Inhibit control is active,the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the moduleInhibit 4
produces an output whenever a valid input source is applied. Do not place an external pull-up on this pin. Forpower-up into a non-prebiased output, it is recommended that AutoTrack be utilized for On/Off control. See theApplication Information for additional details.This is an analog control input that enables the output voltage to follow an external voltage. This pin becomesactive typically 20 ms after the input voltage has been applied, and allows direct control of the output voltage from0 V up to the nominal set-point voltage. Within this range, the output follows the voltage at the Track pin on aTrack 2
volt-for-volt basis. When the control voltage is raised above this range, the module regulates at its set-point voltage.The feature allows the output voltage to rise simultaneously with other modules powered from the same input bus.If unused, the input should be connected to V
I
.Note: Due to the under-voltage lockout feature, the output of the module cannot follow its own input voltage duringpower up. For more information, see the related application note.
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PTH12050W TYPICAL CHARACTERISTICS (V
I
= 12 V)
(1) (2)
Efficiency − %
IO − Output Current − A
0 1 2 3 4 5 6
50
60
70
80
90
100
VO = 5 V
VO = 3.3 V
VO = 2.5 V
VO = 2 V
VO = 1.8 V
VO = 1.5 V
VO = 1.2 V
0
20
40
60
80
Output Ripple − mV
VOUT = 5 V
VOUT = 3.3 V
VOUT = 2.5 V
VOUT = 2 V
VOUT = 1.8 V VOUT = 1.5 V
VOUT = 1.2 V
IO − Output Current − A
0 1 2 3 4 5 6
0
1
2
3
4
VOUT = 5 V
− Power Dissipation − W
PD
VOUT = 3.3 V
VOUT = 2.5 V
VOUT = 2 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
IO − Output Current − A
0 1 2 3 4 5 6
0
30
20
60
40
70
90
80
50
400
200
100
LFM
Natural Convection
200
100
Natural
Convection
VO= 3.3 V
1 2 3 4 5 6
400
IO- Output Current - A
TA- Ambient Temperature - °C
0
30
20
1 2 3 4
60
40
70
90
80
50
5 6
400
LFM
Natural Convection
400
200
100 VO= 5 V
200
100
Natural
Convection
IO- Output Current - A
TA- Ambient Temperature - °C
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
EFFICIENCY OUTPUT RIPPLE POWER DISSIPATIONvs vs vsLOAD CURRENT LOAD CURRENT LOAD CURRENT
Figure 1. Figure 2. Figure 3.
TEMPERATURE DERATING TEMPERATURE DERATINGvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 4. Figure 5.
(1) Characteristic data has been developed from actual products tested at 25 °C. This data is considered typical data for the converter.Applies to Figure 1 ,Figure 2 , and Figure 3 .(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operatingtemperatures. Derating limits apply to modules soldered directly to a 4 inches ×4 inches double-sided PCB with 1-oz. copper. Forsurface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the powerpins. Please refer to the mechanical specification for more information. Applies to Figure 4 .
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PTH12050L TYPICAL CHARACTERISTICS (V
I
= 12 V)
(1) (2)
50
60
70
80
90
100
Efficiency-%
VO=0.8V
VO=1.8V
VO=1.5V
VO=1.2V
VO=1V
IO-OutputCurrent- A
0 1 2 3 4 5 6
− Power Dissipation − W
PD
0
0.3
0.6
0.9
1.2
1.5
1.8
IO − Output Current − A
0 1 2 3 4 5 6
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1 V
VOUT = 0.8 V
Output Ripple − mV
VOUT = 1 V
VOUT = 1.8 V
VOUT = 0.8 V
VOUT = 1.5 V
VOUT = 1.2 V
0
10
20
30
40
50
IO − Output Current − A
0 1 2 3 4 5 6
TA− Ambient Temperature −
5C
20
30
40
50
60
70
80
90
100 LFM
Nat Conv
VO = ≤1.8 V
IO − Output Current − A
0 1 2 3 4 5 6
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
EFFICIENCY OUTPUT RIPPLE POWER DISSIPATIONvs vs vsLOAD CURRENT LOAD CURRENT LOAD CURRENT
Figure 6. Figure 7. Figure 8.
TEMPERATURE DERATING
vsOUTPUT CURRENT
Figure 9.(1) Characteristic data has been developed from actual products tested at 25 °C. This data is considered typical data for the converter.Applies to Figure 6 ,Figure 7 , and Figure 8 .(2) SOA graphs represent the conditions at which internal components are at or below the manufacturer's maximum operatingtemperatures. Derating limits apply to modules soldered directly to a 4 inches ×4 inches double-sided PCB with 1-oz. copper. Forsurface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the powerpins. Please refer to the mechanical specification for more information. Applies to Figure 9 .
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APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
VIVO
GND
PTH12050
1
63
4
2
Track
VIVO
GNDInhibit Adjust
*Requiredwithoutputvoltages 3.3V>
5
C1
100 F
(Required)
m
C2*
10 F
Ceramic
m
R ,
1%
SET C3
100 F
(Optional)
m
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
The V
O
Adjust control (pin 5) sets the output voltage of the PTH12050 product. The adjustment range is from1.2 V to 5.5 V for the W-suffix modules and 0.8 V to 1.8 V for L-suffix modules. The adjustment method requiresthe addition of a single external resistor, R
SET
, that must be connected directly between the V
O
Adjust and GNDpins. Table 1 gives the standard value of the external resistor for a number of standard voltages, along with theactual output voltage that this resistance value provides. For other output voltages, the value of the requiredresistor can either be calculated using Equation 1 , or simply selected from the range of values given inTable 3 .Figure 10 shows the placement of the required resistor.
Table 1. Standard Values of R
SET
for Standard Output Voltages
PTH12050W PTH12050L
V
O
V
O
V
OR
SET
(k Ω) R
SET
(k Ω)(Required) (V) (Actual) (V) (Actual) (V)
5 0.280 5.009 N/A N/A3.3 2.0 3.294 N/A N/A2.5 4.32 2.503 N/A N/A2 8.06 2.010 N/A N/A1.8 11.5 1.801 0.130 1.8001.5 24.3 1.506 3.57 1.4991.2 Open 1.200 12.1 1.2011.1 N/A N/A 18.7 1.1011.0 N/A N/A 32.4 0.9990.9 N/A N/A 71.5 0.9010.8 N/A N/A Open 0.800
(1) A 0.05-W rated resistor can be used. The tolerance should be 1%, with a temperature stability of 100 ppm/ °C orbetter. Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 5 and 1using dedicated PCB traces.(2) Never connect capacitors from V
O
Adjust to either GND or V
O
. Any capacitance added to the V
O
Adjust pin affects thestability of the regulator.
Figure 10. V
O
Adjust Resistor Placement
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Equation 1. Output Voltage Adjust
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Use Equation 1 to calculate the adjust resistor value. See Table 2 for parameters, R
s
and V
min
.
Table 2. Adjust Formula Parameters
OUTPUT VOLTAGE ADJUST EQUATION Parameter PTH12050W PTH12050L
V
(MIN)
1.2 V 0.8 VV
(MAX)
5.5 V 1.8 VR
S
1.82 k Ω7.87 k Ω(1)
Table 3. Output Voltage Set-Point Resistor Values
PTH12050W PTH12050L
V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω) V
O
(V) R
SET
(k Ω)
1.200 Open 2.7 3.51 0.8 Open1.225 318 2.75 3.34 0.825 3121.250 158 2.8 3.18 0.85 1521.275 105 2.85 3.03 0.875 98.81.300 78.2 2.9 2.89 0.9 72.11.325 62.2 2.95 2.75 0.925 56.11.350 51.1 3.0 2.62 0.95 45.51.375 43.9 3.05 2.49 0.975 37.81.400 38.2 3.1 2.39 1.0 32.11.425 33.7 3.15 2.27 1.025 27.71.450 30.2 3.2 2.18 1.05 24.11.475 27.3 3.25 2.08 1.075 21.21.50 24.8 3.3 1.99 1.1 18.81.55 21 3.35 1.91 1.125 16.71.60 18.2 3.4 1.82 1.15 151.65 16 3.5 1.66 1.175 13.51.70 14.2 3.6 1.51 1.2 12.11.75 12.7 3.7 1.38 1.225 111.80 11.5 3.8 1.26 1.25 9.911.85 10.5 3.9 1.14 1.275 8.971.90 9.61 4.0 1.04 1.3 8.131.95 8.85 4.1 0.939 1.325 7.372.00 8.18 4.2 0.847 1.35 6.682.05 7.59 4.3 0.761 1.375 6.042.10 7.07 4.4 0.680 1.4 5.462.15 6.6 4.5 0.604 1.425 4.932.20 6.18 4.6 0.533 1.45 4.442.25 5.8 4.7 0.466 1.475 3.982.30 5.45 4.8 0.402 1.5 3.562.35 5.14 4.9 0.342 1.55 2.82.40 4.85 5.0 0.285 1.6 2.132.45 4.58 5.1 0.231 1.65 1.542.50 4.33 5.2 0.180 1.7 1.022.55 4.11 5.3 0.131 1.75 0.5512.60 3.89 5.4 0.085 1.8 0.1302.65 3.7 5.5 0.041
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CAPACITOR RECOMMENDATIONS FOR THE PTH12050 SERIES OF POWER MODULES
Input Capacitor
Output Capacitors (Optional)
Ceramic Capacitors
Tantalum Capacitors
Capacitor Table
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
The recommended input capacitor(s) is determined by the 100 µF minimum capacitance and 750 mArmsminimum ripple current rating. A 10-µF X5R/X7R ceramic capacitor may also be added to reduce the reflectedinput ripple current. This is recommended for output voltage set points of 3.3 V and higher.
Ripple current, less than 100 m Ωequivalent series resistance (ESR) and temperature are major considerationswhen selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have arecommended minimum voltage rating of 2 ×(maximum dc voltage + ac ripple). This is standard practice toensure reliability. Only a few tantalum capacitors have sufficient voltage rating to meet this requirement. Attemperatures below 0 °C, the ESR of aluminum electrolytic capacitors increases. For these applications, Os-Contypes , polymer-tantalum, and polymer-aluminum types should be considered.
For applications with load transients (sudden changes in load current), regulator response benefits from externaloutput capacitance. The value of 100 µF is used to define the transient response specification. For mostapplications, a high quality computer-grade aluminum electrolytic capacitor is adequate. These capacitorsprovide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient temperaturesabove 0 °C. Below 0 °C, tantalum, ceramic or Os-Con type capacitors are recommended. When using one ormore nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 m Ω(7 m Ωusing themanufacturer'fs maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified inTable 4 .
In addition to electrolytic capacitance, adding a 10-µF X5R/X7R ceramic capacitor to the output reduces theoutput ripple voltage and improve the regulator's transient response. The measurement of both the output rippleand transient response is also best achieved across a 10-µF ceramic capacitor.
Above 150 kHz the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramiccapacitors have very low ESR and a resonant frequency higher than the bandwidth of the regulator. They can beused to reduce the reflected ripple current at the input as well as improve the transient response of the output.When used on the output their combined ESR is not critical as long as the total value of ceramic capacitancedoes not exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than five identicalceramic capacitors in parallel with values of 10 µF or greater.
Tantalum type capacitors are most suited for use on the output bus, and are recommended for applicationswhere the ambient operating temperature can be less than 0 °C. The AVX TPS, Sprague 593D/594/595 andKemet T495/ T510 capacitor series are suggested over other tantalum types due to their higher rated surge,power dissipation, and ripple current capability. As a caution many general purpose tantalum capacitors haveconsiderably higher ESR, reduced power dissipation and lower ripple current capability. These capacitors arealso less reliable as they have no surge current rating. Tantalum capacitors that do not have a stated ESR orsurge current rating are not recommended for power applications.
When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit are encounteredwell before the maximum capacitance value is reached.
Table 1 identifies the characteristics of capacitors from number of vendors with acceptable ESR and ripplecurrent (rms) ratings. The recommended number of capacitors required at both the input and output buses isidentified for each capacitor type.
This is not an extensive capacitor list. Capacitors from other vendors are available with comparablespecifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are criticalparameters necessary to insure both optimum regulator performance and long capacitor life.
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PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Table 4. Input/Output Capacitors
(1)
Capacitor Characteristics Quantity
Max ESR Max RippleCapacitor Vendor,
Working
Vendor NumberValue at Current at Physical Size Input OutputType/Series (Style)
Voltage
(µF) 100 kHz 85 °C (Irms) (mm) Bus Bus(V)
(Ω) (mA)
Panasonic, Aluminum 25 330 0.090 775 10 ×12,5 1 1 EEUFC1E331
FC (Radial) 35 180 0.090 775 10 ×12,5 1 1 EEUFC1V181
FK (SMD) 25 470 0.080 850 10 ×10,2 1 1 EEVFK1E471P
United Chemi-Con
PXA-Poly-Aluminum (SMD) 16 150 0.026 3430 10 ×7,7 1 ≤4 PXA16VC151MJ80TP
PS (Radial) 20 100 0.024 3300 8 ×11,5 1 ≤4 20PS100MH11
LXZ, Aluminum (Radial) 35 220 0.090 760 10 ×12,5 1 1 LXZ35VB221M10X12LL
Nichicon Aluminum
HD (Radial) 25 220 0.072 760 8 ×11,5 1 1 UHD1E221MPR
PM (Radial) 35 220 0.090 770 10 ×15 1 1 UPM1V221MHH6
Panasonic, Poly-Aluminum
S/SE (SMD) 6.3
(2)
180 0.005 4000 7,3 ×4,3 ×4,2 N/R
(3)
≤1 EEFSE0J181R (V
O
≤5.1 V)
Sanyo
SVP, Os-con (SMD) 20 100 0.024 >3300 8 ×12 1 ≤4 20SVP100M
SEQP, Os-con (Radial) 20 100 0.024 >3300 8 ×12 1 ≤4 20SEQP100M
TPE, Pos-Cap (SMD) 10 220 0.025 >2400 7,3 ×5,7 N/R
(3)
≤4 10TPE220ML
AVX, Tantalum 10 100 0.100 >1090 7,3 ×4,3 ×4,1 N/R
(3)
≤5 TPSD107M010R0100
TPS (SMD) 10 220 0.100 >1414 7,3 ×4,3 ×4,1 N/R
(3)
≤5 TPSV227M010R0100
25 68 0.095 >1451 7,3 ×4,3 ×4,1 2 ≤5 TPSV686M025R0080
Kemet
T520, Poy-Tant (SMD) 10 100 0.080 1200 7,3x5,7x4 N/R
(3)
≤5 T520D107M010AS
T495, Tantalum (SMD) 10 100 0.100 >1100 7,3x5,7x4 N/R
(3)
≤5 T495X107M010AS
Vishay-Sprague 10 150 0.090 1100 7,3 ×6×4,1 N/R
(3)
≤5 594D157X0010C2T
594D, Tantalum (SMD) 25 68 0.095 1600 7,3 ×6×4,1 2 ≤5 594D686X0025R2T
94SP, Organic (Radial) 16 100 0.070 2890 10 ×10,5 1 ≤5 94SP107X0016FBP
94SVP, Organic (SMD) 20 100 0.025 3260 8 ×12 1 ≤4 94SVP107X0020E12
Kemet, Ceramic X5R (SMD) 16 10 0.002 – 1210 case 1
(4)
≤5 C1210C106M4PAC
6.3 47 0.002 3225 mm N/R
(3)
≤5 C1210C476K9PAC
Murata, Ceramic X5R (SMD) 6.3 100 0.002 – 1210 case N/R
(3)
≤3 GRM32ER60J107M
6.3 47 3225 mm N/R
(3)
≤5 GRM32ER60J476M
16 22 1
(4)
≤5 GRM32ER61C226L
16 10 1
(4)
≤5 GRM32DR61C106K
TDK, Ceramic X5R (SMD) 6.3 100 0.002 – 1210 case N/R
(3)
≤3 C3225X5ROJ107MT
6.3 47 3225 mm N/R
(3)
≤5 C3225X5ROJ476MT
16 22 1
(4)
≤5 C3225X5R1C226MT
16 10 1
(4)
≤5 C3225X5R1C106MT
(1) Capacitor Supplier VerificationPlease verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because oflimited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-termconsideration for obsolescence.RoHS, Lead-free and Material DetailsPlease consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing processrequirements. Component designators or part number deviations can occur when material composition or soldering requirements areupdated.
(2) The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V.(3) N/R – Not recommended. The capacitor voltage rating does not meet the minimum operating limits.(4) Ceramic capacitors are required to complement electrolytic types at the input and to reduce high-frequency ripple current.
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Designing for Very Fast Load Transients
Features of the PTH Family of Non-Isolated Wide Output Adjust Power Modules
Introduction
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using theoptional value of output capacitance. As the di/dt of a transient is increased, the response of a converter'sregulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation withany dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target applicationspecifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional outputcapacitor decoupling. In these cases special attention must be paid to the type, value and ESR of the capacitorsselected.
If the transient performance requirements exceed that specified in the data sheet, or the total amount of loadcapacitance is above 3,000 µF, the selection of output capacitors becomes more important.
The PTH/PTV family of non-isolated, wide-output adjustable power modules are optimized for applications thatrequire a flexible, high performance module that is small in size. Each of these products are POLA™ compatible.POLA-compatible products are produced by a number of manufacturers, and offer customers advanced,nonisolated modules with the same footprint and form factor. POLA parts are also ensured to be interoperable,thereby, providing customers with second-source availability.
From the basic, Just Plug It In functionality of the 6-A modules, to the 30-A rated feature-rich PTHxx030, theseproducts were designed to be very flexible, yet simple to use. The features vary with each product. Table 5provides a quick reference to the features by product series and input bus voltage.
Table 5. Operating Features by Series and Input Bus Voltage
Series Input Bus (V) I
O
(A) Adjust On/Off Over- Prebias Auto- Margin Output Thermal(Trim) Inhibit Current Startup Track™ Up/Down Sense Shutdown
3.3 6 • • • • •PTHxx050 5 6 • • • • •12 6 • • • • •3.3 / 5 10 • • • • • • •PTHxx060
12 10 • • • • • • •3.3 / 5 15 • • • • • • •PTHxx010
12 12 • • • • • • •5 8 • • • • •PTVxx010
12 8 • • • • •3.3 / 5 22 • • • • • • • •PTHxx020
12 18 • • • • • • • •5 18 • • • • • • •PTVxx020
12 16 • • • • • • •3.3 / 5 30 • • • • • • • •PTHxx030
12 26 • • • • • • • •
For simple point-of-use applications, the PTH12050 (6 A) provides operating features such as an on/off inhibit,output voltage trim, prebias start-up and overcurrent protection. The PTH12060 (10 A), and PTH12010 (12 A)include an output voltage sense, and margin up/down controls. Then the higher output current, PTH12020 (18 A)and PTH12030 (26 A) products incorporate overtemperature shutdown protection.
The PTV12010 and PTV12020 are similar parts offered in a vertical, single in-line pin (SIP) profile, at slightlylower current ratings.
All of the products referenced in Table 5 include Auto-Track™. This feature was specifically designed to simplifythe task of sequencing the supply voltages in a power system. This and other features are described in thefollowing sections.
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POWER-UP INTO A NON-PREBIASED OUTPUT — AUTO-TRACK™ FUNCTION
UDG−06074
RSET
2 kΩ
0.1 W
1 %
CO
330 µF
CI
560 µF
2
8 1 7
3910
PTH12060W
4
6
+
GND
L
O
A
D
Q1
BSS138
1=Turn−Off
+
Margin
Down
Margin
Up Inhibit
Track GND GND VoAdj
5
VO
VO
VOSense
VI
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
The Auto-Track function is unique to the PTH/PTV family, and is available with all POLA products. Auto-Trackwas designed to simplify the amount of circuitry required to make the output voltage from each module power upand power down in sequence. The sequencing of two or more supply voltages during power up is a commonrequirement for complex mixed-signal applications that use dual-voltage VLSI ICs such as the TMS320™ DSPfamily, microprocessors, and ASICs.
Basic Power-Up Using Auto-Track™
For applications requiring output voltage on/off control, each series of the PTH family incorporates the trackcontrol pin. The Auto-Track feature should be used instead of the inhibit feature wherever there is a requirementfor the output voltage from the regulator to be turned on/off.
Figure 11 shows the typical application for basic start-up. Note the discrete transistor (Q1). The track input hasits own internal pull-up to a potential of 5 V to 13.2 V The input is not compatible with TTL logic devices. Anopen-collector (or open-drain) discrete transistor or supply voltage supervisor (TPS3808 or TPS7712) isrecommended for control.
Figure 11. Basic Start-up Control Circuit
Turning on Q1 applies a low voltage to the track control pin and disables the output of the module. If Q1 is thenturned off, the output ramps immediately to the regulated output voltage. A regulated output voltage is producedwithin 35 ms. With the initial application of the input source voltage, the track pin must be held low (Q1 turnedON) for at least 40 ms. Figure 12 shows the typical rise in both the output voltage and input current, following theturn off of Q1. The turn off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms weremeasured with a 10-A constant current load.
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Q1VDS (2 V/div)
VO (2 V/div)
II (2 A/div)
t − Time − 40 ms/div
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Figure 12. Power-Up from Track Control
NOTE:
If a prebias condition is not present, it is highly recommended that the Track controlpin be used for controlled power-up and power-down. If Track control is not used, theoutput voltage starts up and overshoots by as much as 10%, before settling at theoutput voltage setpoint.
How Auto-Track™ Works
Auto-Track works by forcing the module output voltage to follow a voltage presented at the Track control pin
(1)
.This control range is limited to between 0 V and the module set-point voltage. Once the track-pin voltage israised above the set-point voltage, the module output remains at its set-point
(2)
. As an example, if the Track pinof a 2.5-V regulator is at 1 V, the regulated output is 1 V. If the voltage at the Track pin rises to 3 V, the regulatedoutput does not go higher than 2.5 V.
When under Auto-Track control, the regulated output from the module follows the voltage at its Track pin on avolt-for-volt basis. By connecting the Track pin of a number of these modules together, the output voltages followa common signal during power up and power down. The control signal can be an externally generated masterramp waveform, or the output voltage from another power supply circuit
(3)
. For convenience, the Track inputincorporates an internal RC-charge circuit. This operates off the module input voltage to produce a suitable risingwaveform at power up.
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PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Typical Auto-Track Application
The basic implementation of Auto-Track allows for simultaneous voltage sequencing of a number of Auto-Trackcompliant modules. Connecting the Track inputs of two or more modules forces their track input to follow thesame collective RC-ramp waveform, and allows their power-up sequence to be coordinated from a commonTrack control signal. This can be an open-collector (or open-drain) device, such as a power-up reset voltagesupervisor IC. See U3 in Figure 13 .
To coordinate a power-up sequence, the Track control must first be pulled to ground potential through R
TRK
asdefined in Figure 13 . This should be done at or before input power is applied to the modules. The ground signalshould be maintained for at least 40 ms after input power has been applied. This brief period gives the modulestime to complete their internal soft-start initialization
(4)
, enabling them to produce an output voltage. A low-costsupply voltage supervisor IC, that includes a built-in time delay, is an ideal component for automaticallycontrolling the Track inputs at power up.
Figure 13 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequencedpower up of two 12-V input Auto-Track modules. The output of the TL7712A supervisor becomes active abovean input voltage of 3.6 V, enabling it to assert a ground signal to the common track control well before the inputvoltage has reached the module's undervoltage lockout threshold. The ground signal is maintained untilapproximately 43 ms after the input voltage has risen above U3's voltage threshold, which is 10.95 V. The 43-mstime period is controlled by the capacitor C3. The value of 3.3 µF provides sufficient time delay for the modulesto complete their internal soft-start initialization. The output voltage of each module remains at zero until the trackcontrol voltage is allowed to rise. When U3 removes the ground signal, the track control voltage automaticallyrises. This causes the output voltage of each module to rise simultaneously with the other modules, until eachreaches its respective set-point voltage.
Figure 14 shows the output voltage waveforms from the circuit of Figure 13 after input voltage is applied to thecircuit. The waveforms, V
O
1 and V
O
2, represent the output voltages from the two power modules, U1 (3.3 V) andU2 (1.8 V), respectively. V
TRK
, V
O
1, and V
O
2 are shown rising together to produce the desired simultaneouspower-up characteristic.
The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltagethreshold, the ground signal is re-applied to the common track control. This pulls the track inputs to zero volts,forcing the output of each module to follow, as shown in Figure 15 . In order for a simultaneous power-down tooccur, the track inputs must be pulled low before the input voltage has fallen below the modules' undervoltagelockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longerpresent, their outputs can no longer follow the voltage applied at their track input. During a power-downsequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and theAuto-Track slew rate. If the Track pin is pulled low at a slew rate greater than 1 V/ms, the discharge of the outputcapacitors will induce large currents which could exceed the peak current rating of the module. This will result ina reduction in the maximum allowable output capacitance as listed in the Electrical Characteristics table. Whencontrolling the Track pin of the PTH12060W using a voltage supervisor IC, the slew rate is increased, thereforeC
O
max is reduced to 2200 μF.
Notes on Use of Auto-Track™1. The Track pin voltage must be allowed to rise above the module set-point voltage before the moduleregulates at its adjusted set-point voltage.2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with rampspeeds of up to 1 V/ms.3. The absolute maximum voltage that may be applied to the Track pin is the input voltage V
I
.4. The module cannot follow a voltage at its track control input until it has completed its soft-start initialization.This takes about 40 ms from the time that a valid voltage has been applied to its input. During this period, itis recommended that the Track pin be held at ground potential.5. The Auto-Track function is disabled by connecting the Track pin to the input voltage (V
I
). When Auto-Track isdisabled, the output voltage rises at a quicker and more linear rate after input power has been applied.
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N = Number of Track pins connected together
10 kΩ
# RTRK = 100 Ω / N
VI = 12 V Vo1 = 3.3 V
RSET1
CO1
+
C
+
PTH12050W
5
63
4
2
Track
VIVO
GND
Inhibit 1Adjust
TL7712A
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
CT
CREF RRST
Vo2 = 1.8 V
CO2
+
C
+
PTH12060W
7
10
4
5
62
3
9 8
Track
VIVO
GNDInhibit 1
Up Dn Sense
Adjust
SET2
U1
U2
U3
RTRK #
2.0 kΩ
11.5 kΩ
I2
0.1 µF3.3 µF
50 Ω
I1
R
t − Time − 20 ms/div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
t − Time − 400 µs/div
VTRK (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Figure 13. Sequenced Power Up and Power Down Using Auto-Track
Figure 14. Simultaneous Power Up With Auto-Track Figure 15. Simultaneous Power Down with Auto-TrackControl Control
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POWER-UP INTO A PREBIASED OUTPUT — START-UP USING INHIBIT CONTROL
t − Time − 10 ms/div
VO1 (1 V/div)
VO2 (1 V/div)
IO2 (5 V/div)
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series ofpower modules. (Note that this is a feature enhancement for the many of the W-suffix products)
[1]
.
A prebias startup condition occurs as a result of an external voltage being present at the output of a powermodule prior to its output becoming active. This often occurs in complex digital systems when current fromanother power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Anotherpath might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. Aprebias can cause problems with power modules that incorporate synchronous rectifiers. This is because undermost operating conditions, such modules can sink as well as source output current. The 12-V input PTH modulesall incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit pin is heldlow.
Conditions for Prebias Holdoff
In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions mustbe maintained. The module holds off a prebias voltage when the Inhibit pin is held low, and whenever the outputis allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of theground signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Trackdisabled
[2]
. To further ensure that the regulator doesn ’ t sink output current, (even with a ground signal applied toits Inhibit), the input voltage must always be greater than the applied prebias source. This condition must existthroughout the power-up sequence
[3]
.
The soft-start period is complete when the output begins rising above the prebias voltage. Once it is completethe module functions as normal, and sinks current if a voltage higher than the nominal regulation value is appliedto its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risento either the set-point voltage, or the voltage applied at the module's Track control pin, whichever is lowest.to its output.
Prebias Demonstration Circuit
Figure 16 shows the startup waveforms for the demonstration circuit shown in Figure 17 . The initial rise in V
O
2 isthe prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that theoutput current from the PTH12010L module (I
O
2) is negligible until its output voltage rises above the appliedprebias.
Figure 16. Prebias Startup Waveforms
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Up Dn Sense
V =12V
I
ASIC
VCORE VC CI O
I 2
O
PTH12010L
1
10
4
5
62
3
9
Tra ck
GND
Inhibit
7
Vadj
Sense
+
V 1=3.3V
O
V 2=1.8V
O
R1
2kW
R5
10k0
R4
100kW
R3
11k0
R1
130 W
C2
330 Fm
C4
330 Fm
C6
0.68 Fm
C5
0.1 Fm
C3
330 Fm
C1
330 Fm
+
+
PTH12020W
7
10
4
5
62
3
9
Tra ck
VI
VI
VO
VO
GND
Inhibit
1
Adjust
+
TL7702B
VCC
GND
SENSE
RESIN
REF
CT
RESET
RESET
8
7
2
1
3
5
6
4
+
8
8
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
Figure 17. Application Circuit Demonstrating Prebias Startup
Notes:
1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now beenincorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with aproduction lot date code of 0423 or later.2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by thevoltage applied to the Track control pin, the output sinks current during the period that the track controlvoltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track bedisabled when not being used. This is accomplished by connecting the Track pin to the input voltage, V
I
. Thisraises the Track pin voltage well above the set-point voltage prior to the module ’ s start up, thereby, defeatingthe Auto-Track feature.3. To further ensure that the regulator's output does not sink current when power is first applied (even with aground signal applied to the Inhibit control pin), the input voltage must always be greater than the appliedprebias source. This condition must exist throughout the power-up sequence of the power system.
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Overcurrent Protection
Overtemperature Protection (OTP)
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
For protection against load faults, all modules incorporate output overcurrent protection. Applying a load thatexceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, amodule periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode ofoperation, whereby, the module continues in a cycle of successive shutdown and power up until the load fault isremoved. During this period, the average current flowing into the fault is significantly reduced. Once the fault isremoved, the module automatically recovers and returns to normal operation.
The PTH12020, PTV12020, and PTH12030 products have overtemperature protection. These products have anon-board temperature sensor that protects the module's internal circuitry against excessively high temperatures.A rise in the internal temperature may be the result of a drop in airflow, or a high ambient temperature. If theinternal temperature exceeds the OTP threshold, the module's Inhibit control is internally pulled low. This turnsthe output off. The output voltage drops as the external output capacitors are discharged by the load circuit. Therecovery is automatic, and begins with a soft-start power up. It occurs when the sensed temperature decreasesby about 10 °C below the trip point.Note: The overtemperature protection is a last resort mechanism to prevent thermal stress to the regulator.Operation at or close to the thermal shutdown temperature is not recommended and will reduce thelong-term reliability of the module. Always operate the regulator within the specified Safe Operating Area(SOA) limits for the worst-case conditions of ambient temperature and airflow.
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TAPE AND REEL SPECIFICATION
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
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TRAY SPECIFICATION
PTH12050W/L
SLTS214H – MAY 2003 – REVISED OCTOBER 2007
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
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PTH12050LAH ACTIVE Through-
Hole Module EUU 6 56 Pb-Free (RoHS) SN N / A for Pkg Type Request Free Samples
PTH12050LAS ACTIVE Surface
Mount Module EUV 6 56 TBD SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS Request Free Samples
PTH12050LAST ACTIVE Surface
Mount Module EUV 6 250 TBD SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS Purchase Samples
PTH12050LAZ ACTIVE Surface
Mount Module EUV 6 56 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Request Free Samples
PTH12050LAZT ACTIVE Surface
Mount Module EUV 6 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Purchase Samples
PTH12050WAD ACTIVE Through-
Hole Module EUU 6 56 Pb-Free (RoHS) SN Level-1-235C-UNLIM/
Level-3-260C-168HRS Purchase Samples
PTH12050WAH ACTIVE Through-
Hole Module EUU 6 56 Pb-Free (RoHS) SN Level-1-235C-UNLIM/
Level-3-260C-168HRS Request Free Samples
PTH12050WAS ACTIVE Surface
Mount Module EUV 6 56 TBD SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS Request Free Samples
PTH12050WAST ACTIVE Surface
Mount Module EUV 6 250 TBD SNPB Level-1-235C-UNLIM/
Level-3-260C-168HRS Purchase Samples
PTH12050WAZ ACTIVE Surface
Mount Module EUV 6 56 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Request Free Samples
PTH12050WAZT ACTIVE Surface
Mount Module EUV 6 250 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2010
Addendum-Page 2
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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