Preliminary
This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.0 http://www.ramtron.com
Mar. 2007 Page 1 of 15
FM22L16
4Mbit FRAM Memory
Features
4Mbit Ferroelectric Nonvolatile RAM
• Organized as 256Kx16
• Configurable as 512Kx8 Using /UB, /LB
• 10
14
Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Pro cess
SRAM Compatible
• JEDEC 256Kx16 SRAM Pinout
• 55 ns Access Time, 110 ns Cycle Time
Advanced Features
• Low V
DD
Monitor Protects Memory against
Inadvertent Wr ites
• Software Programmable Block Write Protect
Superior to B a ttery-backed SRAM Modules
• No Battery Concerns
• Monolithic Reliability
• True Surface Mount Solution, No Rework Steps
• Superior for Moisture, Shock, and Vibration
Low Power Operation
• 2.7V – 3.6V Power Supply
• Low Current Mode ( 5µA) using ZZ pin
• 18 mA Active Current
Industry Sta ndard Configuratio n
• Industrial Temperature -40° C to +85° C
• 44-pin “Green”/RoHS TSOP-II package
Description
The FM22L16 is a 256Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and unlimited write endurance make
FRAM superior to other types of memory.
In-system operation of the FM22L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM22L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM22L16 includes a low voltage monitor that
blocks access to the memory array when V
DD
drops
below a critical threshold. The memory is protected
against an inadvertent access and data corruption
under this condition. The device also features
software-controlled write protection. The memory
array is divided into 8 uniform blocks, each of which
can be individually write protected.
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
A13
A14
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
WE
VDD
A15
A16
A17
CE
A12
/ZZ
OE
A7
A6
A5
VSS
DQ12
DQ11
DQ8
DQ9
DQ10
LB
A8
A9
A10
A11
VDD
UB
DQ13
DQ14
DQ15
Ordering Information
FM22L16-55-TG 55 ns access, 44-pin
“Green”/RoHS TSOP-II
FM22L16
Rev. 1.0
Mar. 2007 Page 2 of 15
Address Latch & Write Protec t
Block & Row Decoder
. . .
Figure 1. Block Diagram
Pin Description
Pin Name Type Pin Description
A(17:0) Input Address inputs: The 18 address lines select one of 262,144 words in the FRAM array.
The lowest two address lines A(1:0) may be used for page mode read and write
operations.
/CE Input Chip Enable input: The device is selected and a new memory access begins when /CE is
low and /ZZ is high. The entire address is latched internally o n the falling ed ge of /CE.
Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE
is low.
/WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM22L16 to write the data on the DQ bus to the FRAM arr ay. The falling edge of /WE
latches a new column address for fast page mode write cycles.
/OE Input Output Enable: When /OE is low, the FM22L16 drives the data bus when valid read
data is available. De-asserting /OE high tri-states the DQ pins.
/ZZ Input Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for
normal read/write operation.
DQ(15:0) I/O Data: 16-bit bi-directional data bus for accessing the FRAM array.
/UB Input Upper Byte Select: Enables DQ(15:8) pins during reads and writes. T hese pins are hi-Z
if /UB is high.
/LB Input Lower B yte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
VDD Supply Supply Voltage: 3.3V
VSS Supply Ground
FM22L16
Rev. 1.0
Mar. 2007 Page 3 of 15
Functional Trut h Table
1,2
/CE /WE A(17:2) A(1:0) /ZZ Operation
X X X X L Sleep Mode
H X X X H Standby/Idle
↓ H V V H Read
L H No Change Change H Page Mode Read
L H Change V H Random Read
↓ L V V H /CE-Controlled Write
L ↓ V V H /WE-Controlled Write
2
L ↓ No Change V H Page Mode Write
3
↑ X X X H Starts Precharge
Notes:
1) H=Logic High , L=Logic Low, V = Vali d Data, X=Don’t Care.
2) /WE-cont rolled write cycle begins as a Read cycle.
3) Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.
4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
Byte Select Trut h Table
/OE /LB /UB Operation
H X X
X H H
Read; Outputs Disabled
H L Read; DQ(7:0) Hi-Z
L H Read; DQ(15:8) Hi-Z
L
L L Read
H L Write; Mask DQ(7:0)
L H Write; Mask DQ(15:8)
X
L L Write
Simplified Sleep/Standby State Dia gram
FM22L16
Rev. 1.0
Mar. 2007 Page 4 of 15
Overview
The FM22L16 is a wordwide FRAM memory
logically organized as 262,144 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(17:2) changes.
Memory Operation
Users access 262,144 memory locations, each with 16
data bits through a parallel interface. The FRAM
array is organized as 8 blocks each having 8192 rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is de-
asserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to FRAM called NoDelay
TM
writes.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random locatio n (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM22L16’s /CE-initiated access time is faster than
the address cycle time.
The FM22L16 will drive the data bus when /OE and
at least one of the byte enables (/UB, /LB) is asserted
low. The upper data byte is driven when /UB is low,
and the lower data byte is driven when /LB is low. If
/OE is asserted after the memory access time has been
satisfied, the data bus will be driven with valid data.
If /OE is asserted prior to completion of the memory
access, the da ta bus will no t be driven until valid data
is available. This feature minimizes supply current in
the system b y eliminating transients caused by invalid
data being driven onto the bus. When /OE is
deasserted high, the data bus will remain in a high-Z
state.
Write Operation
Writes occur in the FM22L16 in the same time
interval as reads. The FM22L16 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address A(17:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the de vice begins the
memory cycle as a write. The FM22L16 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is de-asserted high. In a /WE-controlled write,
the memory cycle begins on the falling edge of /CE.
The /WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to de-asserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessa ry.
Page Mode Operation
The FRAM array is organized as 8 blocks each
having 8192 rows. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A (1:0) may
be changed to a new value. A new data byte is then
driven to the DQ p ins no later than t
AAP
, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
along with a new column address provides a page
mode write access.
FM22L16
Rev. 1.0
Mar. 2007 Page 5 of 15
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared fo r a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time t
PC
.
Software Write Protection
The 256Kx16 address space is divided into 8 sectors
(blocks) of 32Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including r ead a ddr esses in the wrong o rd er, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The d ata byte contains the write-protect settings. T his
value will not be written to the memory array, so the
address is a d on’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six add resses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. T he
data byte must be driven to the lower 8-bits of the
data bus, DQ (7:0). Setting a bit to 1 write protects
the corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 32K x16 blocks
Sector 7 3FFFFh – 38000h
Sector 6 37FFFh – 30000h
Sector 5 2FFFFh – 28000h
Sector 4 27FFFh – 20000h
Sector 3 1FFFFh – 18000h
Sector 2 17FFFh – 10000h
Sector 1 0FFFFh – 08000h
Sector 0 07FFFh – 00000h
The write-p rotect read address sequence follows:
1. 24555h *
2. 3AAAAh
3. 02333h
4. 1CCCCh
5. 000FFh
6. 3EF00h
7. 3AAAAh
8. 1CCCCh
9. 0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 24555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 10
32
chance of randomly accessing
exactly the 1
st
six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write pr otect operation is sho wn in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unp r otected.
FM22L16
Rev. 1.0
Mar. 2007 Page 6 of 15
Figure 2. Write-Protect State Machine
For example, the following sequence write-protects addresses from 18000h to 27FFFh (sectors 3 & 4):
Address Data
Read 24555h -
Read 3AAAAh -
Read 02333h -
Read 1CCCCh -
Read 000FFh -
Read 3EF00h -
Write 3AAAAh 18h ; bits 3 & 4 = 1
Write 1CCCCh E7h ; complement of 18h
Write 0FF00h - ; Data is don’t care
Read 00000h - ; return to Normal Operation
FM22L16
Rev. 1.0
Mar. 2007 Page 7 of 15
Software Write Protect Timing
SRAM Drop-In Replacement
The FM22L16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may rema in low indefinitely. While /CE
is low, the device automatically detects address
changes and a new access is begun. This functionality
allows /CE to be grounded as you might with an
SRAM. It also allows page mode operation at speeds
up to 40MHz. Note that if /CE is tied to ground,
the user must be sure /WE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur.
For applications that require the lowest power
consumption, the /CE signal should be active only
during memory accesses. The FM22L16 draws I
DD
supply current while /CE is low, even if addresses and
control signals are static. While /CE is high, the
device draws no more than the maximum standby
current I
SB
.
The FM22L16 is backward compatible with the
1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM22L16 with /CE toggling
low on every address is perfectly acceptable.
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 512Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(18) may be
available from the system processor.
Figure 3. FM22L16 Wired as 512Kx8
FM22L16
Rev. 1.0
Mar. 2007 Page 8 of 15
Electrical Specifications
A bsolute Maximum R atings
Symbol Description Ratings
V
DD
Power Supply Voltage with respect to V
SS
-1.0V to +4.5V
V
IN
Voltage on any signal pin with respect to V
SS
-1.0V to +4.5V and
V
IN
< V
DD
+1V
T
STG
Storage Temperature -55°C to +125°C
T
LEAD
Lead Temperatur e (Soldering, 10 seconds) 300° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these or any other conditions above those listed in the
operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended
periods may affect device reliabili ty.
DC Operating Conditions
(T
A
= -40° C to + 8 5 ° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
V
DD
Power Supply 2.7 3.3 3.6 V
I
DD1
V
DD
Supply Current 18 mA 1
I
DD2
V
DD
Supply Current – CMOS - 1.5 mA 2
I
SB2
Standby Current – CMOS - 150 µA 3
I
ZZ
Sleep Mode Current - 5 µA 4
I
LI
Input Leakage Current ±1 µA
I
LO
Output Leakage Current ±1 µA
V
IH
Input High Voltage 2.2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0 .3 0.6 V
V
OH1
Output High Voltage (
I
OH
= -1.0 mA)
2.4 V
V
OH2
Output High Voltage (
I
OH
= -100 µA)
V
DD
-0.2 V
V
OL1
Output Low Voltage (
I
OL
= 2.1 mA)
0.4 V
V
OL2
Output Low Voltage (
I
OL
= 100 µA)
0.2 V
Notes
1.
V
DD
= 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or V
DD
-0.2V), all DQ pins unloaded.
2.
V
DD
= 3.6V, /CE at V
SS
, All other pins are static and at CMOS levels (0.2V or V
DD
-0.2V), /ZZ is high.
3.
V
DD
= 3.6V, /CE at V
DD
, All other pins are static and at CMOS levels (0.2V or V
DD
-0.2V), /ZZ is high.
4.
V
DD
= 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or V
DD
-0.2V).
FM22L16
Rev. 1.0
Mar. 2007 Page 9 of 15
Read Cycle AC Parameters (T
A
= -40° C to + 85 ° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
-55
Symbol Parameter Min Max Units Notes
t
RC
Read Cycle Time 110 - ns
t
CE
Chip Enable Access Time - 55 ns
t
AA
Address Access Time - 110 ns
t
OH
Output Hold Time 20 - ns
t
AAP
Page Mode Address Access Time - 35 ns
t
OHP
Page Mode Output Hold Time 5 - ns
t
CA
Chip Enable Active Time 55 - ns
t
PC
Precharge Time 55 - ns
t
BA
/UB, /LB Access Time - 30 ns
t
AS
Address Setup Time (to /CE low) 0 - ns
t
AH
Address Hold Time (/CE-controlled) 55 - ns
t
OE
Output Enable Access Time - 10 ns
t
HZ
Chip Enable to Output High-Z - 10 ns 1
t
OHZ
Output Ena ble High to Output High-Z - 10 ns 1
t
BHZ
/UB, /LB High to Output High-Z - 10 ns 1
Write Cycle AC Parameters (T
A
= -40° C to + 85 ° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
-55
Symbol Parameter Min Max Units Notes
t
WC
Write Cycle Time 110 - ns
t
CA
Chip Enable Active Time 55 - ns
t
CW
Chip Enable to Write Enable High 55 - ns
t
PC
Precharge Time 55 - ns
t
BHZ
/UB, /LB High to Output High-Z 5 ns
t
PWC
Page Mode Write Enable Cycle Time 35 - ns
t
WP
Write Enable P ulse W idth 16 - ns
t
AS
Address Setup Time (to /CE low) 0 - ns
t
ASP
Page Mode Address Setup Time (to /WE low) 8 - ns
t
AHP
Page Mode Address Hold Time (to /WE low) 15 - ns
t
WLC
Write Enable Low to /CE High 25 - ns
t
WLA
Write Enable Low to A(17:2) Change 25 - ns
t
AWH
A(17:2) Change to Write Enable High 110 - ns
t
DS
Data Input Setup Time 14 - ns
t
DH
Data Input Hold Time 0 - ns
t
WZ
Write Enable Low to Output High Z - 10 ns 1
t
WX
Write Enable High to Output Dr iven 10 - ns 1
t
WS
Write Enab le to /CE Low Setup Time 0 - ns 2
t
WH
Write Enable to /CE High Hold Time 0 - ns 2
Notes
1 This parameter is characterized but not 100% tested.
2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters t
WS
and t
WH
are not t est ed.
Capacitance
(T
A
= 25° C , f=1 MHz, V
DD
= 3.3V)
Symbol Parameter Max Units Notes
C
I/O
Input/Output Capacitance (DQ) 8 pF
C
IN
Input Capacitance 6 pF
C
ZZ
Input Capacitance of /ZZ pin 8 pF
FM22L16
Rev. 1.0
Mar. 2007 Page 10 of 15
Power Cycle Timing (T
A
= -40° C to + 85 ° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
PU
Power-Up to First Access T ime (after V
DD
min) 450 -
µs
t
PD
Power-Down to Last Access Time (prior to V
TP
) 0
µs
t
VR
V
DD
Rise Time 50 - µs/V 1,2
t
VF
V
DD
Fall Time 100 - µs/V 1,2
t
ZZEN
Sleep Mode Enter Time ( /ZZ low to /CE don’t care) - 0 µs
t
ZZEX
Sleep Mode E xit Time (/ZZ high to 1
st
access after wakeup) 450 - µs
Notes
1 Slope measured at any point on V
DD
waveform.
2 Ramtron cannot test or characterize all V
DD
power ramp profiles. The behavior of the internal circuits is difficult to predict
whe n V
DD
is below the level of a tran sistor threshold voltage. Ramtron strongly recommends that V
DD
power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention
(V
DD
= 2.7V to 3.6V)
Parameter Min Units Notes
Data Retention 10 Years
AC Test Conditions
Input Pulse Levels 0 to 3V
Input rise and fall times 3 ns
Input and outp ut timing levels 1 . 5V
Output Load Capacitance 30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
FM22L16
Rev. 1.0
Mar. 2007 Page 11 of 15
Page Mode Read Cycle Timing
* Although sequential column a ddressing is shown, it is not r e quired.
Write Cycle Timing 1 (/WE-Controlled, /OE lo w)
Write Cycle Timing 2 (/CE-Controlled)
FM22L16
Rev. 1.0
Mar. 2007 Page 12 of 15
Write Cycle Timing 3 (/CE low)
Page Mode Write Cycle Timing
* Although sequential column a ddressing is shown, it is not r e quired.
Sleep Mode Enter/Exit Timing
FM22L16
Rev. 1.0
Mar. 2007 Page 13 of 15
Power Cycle Timing
FM22L16
Rev. 1.0
Mar. 2007 Page 14 of 15
Mechanical Drawing
44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC)
Pin 1
E1 E
D
A1
A
b
e0.10 mm
α
LC
A2
Symbol Min. Nom. Max.
A - - 1.20
A1 0.05 - 0.15
A2 0.95 1.00 1.05
b 0.30 - 0.45
C 0.12 - 0.20
D 18.41 BASIC
E 11.56 11.76 11.96
E1 - 10.16 -
e 0.80 BSC
L 0.40 0.50 0.60
α
0° - 8°
Note: All dimensions in millimeters.
FM22L16
Rev. 1.0
Mar. 2007 Page 15 of 15
Revision History
Revision
Date
Summary
1.0 3/9/07 Initial release.
