SA57AHU-FH - Cirrus Logic - Product.Network

SA57A

SA57U 1

SA57A

DESCRIPTION

The SA57A is a fully integrated switching amplier de-

signed primarily to drive DC brush motors. Two inde-

pendent half bridges provide over 15 amperes peak

output current under microcontroller or DSC control.

Thermal and short circuit monitoring is provided, which

generates fault signals for the microcontroller to take

appropriate action. A block diagram is provided in Fig-

ure 1.

Additionally, cycle-by-cycle current limit offers user

programmable hardware protection independent of

the microcontroller. Output current is measured using

an innovative low loss technique. The SA57A is built

using a multi-technology process allowing CMOS logic

control and complementary DMOS output power de-

vices on the same IC. Use of P-channel high side FETs

enables 60V operation without bootstrap or charge

pump circuitry.

The HSOP surface mount package balances excellent

thermal performance with the advantages of a low pro-

le surface mount package.

FEATURES

♦ Low cost intelligent switching amplier

♦ Directly connects to most embedded Micro-

controllers and Digital Signal Controllers

♦ Integrated gate driver logic with dead-time

generation and shoot-through prevention

♦ Wide power supply range (8.5V to 60V)

♦ Over 15A peak output current per phase

♦ Independent current sensing for each output

♦ User programmable cycle-by-cycle current

limit protection

♦ Over-current and over-temperature warning

signals

APPLICATIONS

♦ Bidirectional DC brush motors

♦ 2 unidirectional DC brush motors

♦ 2 independent solenoid actuators

♦ Stepper motors

FIGURE 1. BLOCK DIAGRAM

SA57A Switching Amplifier

P G N D 1

Gate

Control

PWM

Signals

O ut 1

O ut 2

P G N D 2

T E M P

GND

LIM

/D IS 1

S C

D IS 2

S G N D

P hase 1

P hase 2

Control

Logic

I1' I2'

I1'

I2'

Fault

Logic

Switching Amplifier

SA57A

www.apexanalog.com OCT 2012

SA57U REVF

SA57A

2 SA57U

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

SUPPLY VOLTAGE VS60 V

SUPPLY VOLTAGE VDD 5.5 V

LOGIC INPUT VOLTAGE (-0.5) (VDD+0.5) V

OUTPUT CURRENT, peak, 10ms (Note 2) IOUT 17 A

POWER DISSIPATION, avg, 25ºC (Note 2) PD100 W

TEMPERATURE, junction (Note 3) TJ150 °C

TEMPERATURE RANGE, storage TSTG −65 125 °C

OPERATING TEMPERATURE, case TA−40 125 °C

Parameter Test Conditions2Min Typ Max Units

LOGIC

INPUT LOW 1 V

INPUT HIGH 1.8 V

OUTPUT LOW 0.3 V

OUTPUT HIGH 3.7 V

OUTPUT CURRENT

(SC, Temp, ILIM/DIS1) 50 mA

POWER SUPPLY

VSUVLO 50 60 V

VS UNDERVOLTAGE LOCKOUT,

(UVLO) 9 V

VDD 4.5 5.5 V

SUPPLY CURRENT, VS

20 kHz (One phase switching at

50% duty cycle) , VS=50V, VDD=5V 25 30 mA

SUPPLY CURRENT, VDD

20 kHz (One phase switching at

50% duty cycle) , VS=50V, VDD=5.5V 5 6.5 mA

CURRENT LIMIT

CURRENT LIMIT THRESHOLD (Vth) 3.95 V

Vth HYSTERESIS 100 mV

OUTPUT

CURRENT, CONTINUOUS 25ºC Case Temperature 8 A

RISING DELAY, TD (RISE) See Figure 10 270 ns

FALLING DELAY, TD (FALL) See Figure 10 270 ns

DISABLE DELAY, TD (DIS) See Figure 10 200 ns

ENABLE DELAY, TD (DIS) See Figure 10 200 ns

RISE TIME, T (RISE) See Figure 11 50 ns

FALL TIME, T (FALL) See Figure 11 50 ns

ON RESISTANCE SOURCING

(P-CHANNEL) 5A Load 300 600 mΩ

ON RESISTANCE

SINKING (N-CHANNEL) 5A Load 250 600 mΩ

SPECIFICATIONS

SA57A

SA57U 3

NOTES:

1. (All Min/Max characteristics and specications are guaranteed over the Specied Operating Condi-

tions. Typical performance characteristics and specications are derived from measurements taken

at typical supply voltages and TC = 25°C).

2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power

dissipation to achieve high MTBF.

3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any

set of conditions, do not exceed the specied current rating or a junction temperature of 150°C.

Parameter Test Conditions2Min Typ Max Units

THERMAL

THERMAL WARNING 135 ºC

THERMAL WARNING

HYSTERESIS 40 ºC

RESISTANCE, junction to case Full temperature range 1.25 1.5 ºC/W

TEMPERATURE RANGE, case Meets Specications -40 +125 ºC

FIGURE 2.

44-Pin HSOP, Slug-Up, Package Style HU

SPECIFICATIONS, continued

SA57A

4 SA57U

DIODE FORWARD VOLTAGE - TOP FET

(P-Channel)

FORWARD VOLTAGE (V)

CURRENT (A)

0.5 1.51.31.10.90.7

DIODE FORWARD VOLTAGE - BOTTOM FET

(N-Channel)

FORWARD VOLTAGE (V)

CURRENT (A)

0.5 1.51.31.10.90.7

ON RESISTANCE - TOP FET

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

IOUT,(A)

RDS(on),(Ω)

VS=11

VS=13

VS=15

VS>17

100 987654321

(P-Channel)

ON RESISTANCE - BOTTOM FET

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

IOUT,(A)

RDS(on),(Ω)

VS=11

VS=13

VS=15

VS=17

VS>22

0 987654321

(N-Channel)

POWER DERATING

100

120

CASE TEMPERATURE, TC

POWER DISSIPATION, PD

-40 12080400

VDD SUPPLY CURRENT

4.5

4.6

4.7

4.8

4.9

0 50 100 150 200 250 300

FREQUENCY (kHz)

VDD SUPPLY CURRENT (mA)

ONE PHASE SWITCHING @

50% DUTY CYCLE; VS=50V

VDD SUPPLY CURRENT

4.5

5.5

6.5

7.5

10 20 30 40 50 60

VS SUPPLY VOLTAGE (V)

VDD SUPPLY CURRENT (mA)

ONE PHASE SWITCHING

FREQUENCY = 20kHz

50% DUTY CYCLE

25°C

125°C

CURRENT SENSE

0.1

0.01 0.1 1 10

SENSE CURRENT (mA)

LOAD CURRENT (A)

VS SUPPLY CURRENT

100

120

140

160

180

0 50 100 150 200 250 300

FREQUENCY (kHz)

SUPPLY CURRENT (mA)

ONE PHASE SWITCHING @

50% DUTY CYCLE; VS=50V

SUPPLY CURRENT

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

125°C

25°C

ONE PHASE SWITCHING

FREQUENCY = 20kHz

50% DUTY CYCLE

10 20 30 40 50 60

SA57A

SA57U 5

FIGURE 3. EXTERNAL CONNECTIONS - 44-Pin HSOP

TABLE 1. PIN DESCRIPTIONS - 44-Pin HSOP

Pin # Pin Name Signal Type Simplied Pin Description

25,26 VS (phase 1) Power High Voltage Supply (8.5-60V) supplies phase 1 only

38,39 OUT 2 Power Output Half Bridge 2 Power Output

41,42 PGND (phase 2) Power High Current GND Return Path for Power Output 2

8 SC Logic Output Indication of a short of an output to supply, GND or another phase

5 2b Logic Input Logic high commands 2 phase lower FET to turn on

6 2t Logic Input Logic high commands 2 phase upper FET to turn on

7 I2 Analog Output Phase 2 current sense output

10 ILIM/DIS1 Logic Input/Output

As an output, logic high indicates cycle-by-cycle current limit, and

logic low indicates normal operation. As an input, logic high places

all outputs in a high impedance state and logic low disables the

cycle-by-cycle current limit function.

11,12,13 SGND Power Analog and digital GND – internally connected to PGND

14 1b Logic Input Logic high commands 1 phase lower FET to turn on

15 1t Logic Input Logic high commands 1 phase upper FET to turn on

16 VDD Power Logic Supply (5V)

17 I1 Analog Output Phase 1 current sense output

18 DIS2 Logic Input Logic high places all outputs in a high impedance state

19 TEMP Logic Output Thermal indication of die temperature above 135ºC

35,36 VS (phase 2) Power High Voltage Supply phase 2

28,29 OUT 1 Power Output Half Bridge 1 Power Output

31,32 PGND (phase 1) Power High Current GND Return Path for Power Outputs 1 & 2

23,44 HS Mechanical Pins connected to the package heat slug

1,2,3,4,20,

21,22,24,27,

30,33,34,37,

40,43

NC -- Do Not Connect

SA57AHU

XXXXXXXXXXXX COO

22 23

PIN #1 ID’s:

CHAMFER, ESD Triangle

TOP (SLUG) VIEW

TEMP

DIS2

Vdd

SGND

Ilim/DIS1

SGND

VS1

OUT1

PGND1

VS2

OUT2

PGND2

SA57A

6 SA57U

1.2 PIN DESCRIPTIONS

VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequen-

cy characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to

the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current

peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discus-

sion regarding bypass capacitor selection. Note that VS pins 29-31 carry only the phase 1 supply current. Pins

46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase 2 Both

VS voltages (46-49) are monitored for undervoltage conditions.

OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it

is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to

each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)

PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load ows

through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1

of this datasheet for more details.

SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-

mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-

mately 200ns during switching transitions but in high current applications, short glitches may appear on the SC

pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ

series resistor.

1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-

channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low

side N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection

circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry

also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching

of the top and bottom input signals.

1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-

channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-

channel FET off.

I1, I2: Current sense pins. The SA57A supplies a positive current to these pins which is proportional to the current

owing through the top side P-channel FET for that phase. Commutating currents owing through the back-body

diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor

do currents owing through the low side N-channel FET, in either direction, register at the current sense pins. A

resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase cur-

rent that can be monitored with ADC inputs of a processor or external circuitry.

The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If

the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this

functionality are described in the applications section of this datasheet.

ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA57A. Pulling this pin to logic high places OUT

1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch

through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature.

Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.

SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry

is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it

is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.

Failure do to this may result in oscillations on the output pins during rising or falling edges.

VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the

SA57A. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-

mended) to the SGND pin.

DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state

when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected.

SA57A

SA57U 7

TEMP: This logic level output goes high when the die temperature of the SA57A reaches approximately 135ºC. This

pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.

HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-

nected to GND. Neither the heat slug nor these pins should be used to carry high current.

NC: These “no-connect” pins should be left unconnected.

2. SA57A OPERATION

The SA57A is designed primarily to drive DC brush motors. However, it can be used for any application requiring two

high current outputs. The signal set of the SA57A is designed specically to interface with a DSP or microcontroller.

A typical system block diagram is shown in the gure below. Over-temperature, Short-Circuit and Current Limit

fault signals provide important feedback to the system controller which can safely disable the output drivers in the

presence of a fault condition. High side current monitors for both phases provide performance information which

can be used to regulate or limit torque.

FIGURE 4. SYSTEM DIAGRAM

The block diagram in Figure 5 illustrates the features of the input and output structures of the SA57A. For simplicity,

a single phase is shown.

SA57A Switching Amplifier

DC BRUSH

MOTOR

PGND 1

Current

monitor

Signals

OUT 1

OUT 2

PGND 2

GND

SGND

Gate

Control

Logic

Fault

Logic

T E M P

LIM

/D IS 1

S C

PWM

Signals

D IS 2

S G N D

M icrocontroller

or DSC

SA57A

8 SA57U

FIGURE 5. INPUT AND OUTPUT STRUCTURES FOR A SINGLE PHASE

SGND

Gate

Control

OUT 1

PGND

TEMP

Logic

Temp

Sense

Ref

DIS2

LIM

/DIS1

UVLO

I1'

Lim 2

Vdd

Lim 1

Current

Sense

12k

Vth

TABLE 2. TRUTH TABLE

1t, 2t

1b, 2b

I1, I2

ILIM/DIS1

DIS2

OUT 1

OUT 2

Comments

0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.

0 1 <Vth 0 0 PGND Bottom output FET for that phase is turned on.

1 0 <Vth 0 0 VS Top output FET for that phase is turned on.

1 1 X X X High-Z Both output FETs for that phase are turned off.

X X >Vth 1 X High-Z Voltage on I1 or I2 has exceeded Vth, which causes ILIM/DIS1 to go high.

This internally disables Top and Bottom output FETs for ALL phases.

X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs.

X X X Pulled

High X High-Z Pulling the ILIM/DIS1 pin high externally acts as a second disable input,

which disables ALL output FETs.

X X X Pulled

Low 0

Determined

by PWM

inputs

Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit

function. The state of the outputs is strictly a function of the PWM inputs.

X X X X X High-Z If VS is below the UVLO threshold all output FETs will be disabled.

SA57A

SA57U 9

2.1 LAYOUT CONSIDERATIONS

Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing

ensures normal operation. Poor routing and bypassing can cause erratic and low efciency operation as well as

ringing at the outputs.

The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS

pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to pre-

vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output

current should be placed near the SA57A as well. Capacitor types rated for switching applications are the only types

that should be considered.

The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface

mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufcient.

SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way

that there is no motor current owing in the logic and signal ground traces as parasitic resistances in the small

signal routing can develop sufcient voltage drops to erroneously trigger input transitions. Alternatively, a ground

plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This

isolates noise between signal and power ground traces and prevents high currents from passing between the plane

sections.

Unused area on the top and bottom PCB planes should be lled with solid or hatched copper to minimize inductive

coupling between signals. The copper ll may be left unconnected, although a ground plane is recommended.

2.2 FAULT INDICATIONS

In the case of either an over-temperature or short cir-

cuit fault, the SA57A will take no action to disable the

outputs. Instead, the SC and TEMP signals are pro-

vided to an external controller, where a determination

can be made regarding the appropriate course of ac-

tion. In most cases, the SC pin would be connected

to a FAULT input on the processor, which would im-

mediately disable its PWM outputs. The TEMP fault

does not require such an immediate response, and

would typically be connected to a GPIO, or Keyboard

Interrupt pin of the processor. In this case, the pro-

cessor would recognize the condition as an external

interrupt, which could be processed in software via

an Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of

the disable inputs on the SA57A.

Figure 6 shows an external SR ip-op which provides a hard wired shutdown of all outputs in response to a fault

indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condi-

tion with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shutdown

loop, or simply to reduce processor overhead.

In applications which may not have available GPIO, the TEMP pin may be externally connected to the adjacent

DIS1 pin. If the device temperature reaches ~135ºC all outputs will be disabled, de-energizing the motor. The

SA57A will re-energize the motor when the device temperature falls below approximately 95ºC. The TEMP pin

hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device.

2.3 UNDER-VOLTAGE LOCKOUT

The undervoltage lockout condition results in the SA57A unilaterally disabling all output FETs until VS is above the

UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout

condition is in progress. The SA57A has two VS connections: one for phase 1 and another for phase 2. The supply

voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis

on the UVLO circuit prevents oscillations with typical power supply variations.

FIGURE 6. EXTERNAL FAULT LATCH CIRCUIT

SA57A

PROCESSOR

INTERRUPT

GPIO

PWM

DIS2 TEMP

LATCHED FAULT

FAULT RESET

SA57A

10 SA57U

2.4 CURRENT SENSE

External power shunt resistors are not required

with the SA57A. Forward current in each top, P-

channel output FET is measured and mirrored to

the respective current sense output pin, I1 and

I2. By connecting a resistor between each cur-

rent sense pin and a reference, such as ground,

a voltage develops across the resistor that is pro-

portional to the output current for that phase. An

ADC can monitor the voltages on these resistors

for protection or for closed loop torque control

in some application congurations. The current

sense pins source current from the VDD supply.

Headroom required for the current sense circuit is

approximately 0.5V. The nominal scale factor for

each proportional output current is shown in the

typical performance plot on page 4 of this data-

sheet.

2.5 CYCLE-BY-CYCLE CURRENT LIMIT

In applications where the current in the motor is

not directly controlled, both the average current

rating of the motor and the inrush current must be considered when selecting a proper amplier. For example, a 1A

continuous motor might require a drive amplier that can deliver well over 10A peak in order to survive the inrush

condition at start-up.

Because the output current of each upper output FET is measured, the SA57A is able to provide a very robust cur-

rent limit scheme. This enables the SA57A to safely and easily drive virtually any DC brush motor through a start-

up inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7

shows starting current and back EMF with and without current limit enabled.

If the voltage of any of the two current

sense pins exceeds the current limit

threshold voltage (Vth), all outputs are

disabled. After all current sense pins fall

below the Vth threshold voltage AND the

offending phase’s top side input goes low,

the output stage will return to an active

state on the rising edge of ANY top side

input command signal (1t or 2t). With most

commutation schemes, the current limit

will reset each PWM cycle. This scheme

regulates the peak current in each phase

during each PWM cycle as illustrated in

the timing diagram below. The ratio of

average to peak current depends on the

inductance of the motor winding, the back

EMF developed in the motor, and the width

of the pulse.

Figure 8 illustrates the current limit trigger

and reset sequence. Current limit engages

and ILIM/DIS1 goes high when any current

sense pin exceeds Vth. Notice that the mo-

ment at which the current sense signal ex-

ceeds the Vth threshold is asynchronous

TIME

NON-LIMITED BACK EMF

LIMITED BACK EMF

LIMITED MOTOR CURRENT

NON-LIMITED MOTOR CURRENT

FIGURE 7. START-UP VOLTAGE AND CURRENT

It INPUT

OUT 1

LIM

/DIS1

FIGURE 8. CURRENT LIMIT WAVEFORMS

SA57A

SA57U 11

with respect to the input PWM signal. The difference between the PWM period and the motor winding L/R time

constant will often result in an audible beat frequency sometimes called a sub-cycle oscillation. This oscillation can

be seen on the ILIM/DIS1 pin waveform in Figure 8.

Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the

absence of rising edges of 1t and 2t. At high RPM, this may result in poor performance. At low RPM, the motor may

stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset

the current limit latch.

The current limit feature may be disabled by tying the ILIM/DIS1 pin to GND. The current sense pins will continue to

provide top FET output current information.

Typically, the current sense pins source current into grounded resistors which provide voltages to the current limit

comparators. If instead the current limit resistors are connected to a voltage output DAC, the current limit can be

controlled dynamically from the system controller. This technique essentially reduces the current limit threshold

voltage to (Vth-VDAC). During expected conditions of high torque demand, such as start-up or reversal, the DAC

can adjust the current limit dynamically to allow periods of high current. In normal operation when low current is

expected, the DAC output voltage can increase, reducing the current limit setting to provide more conservative fault

protection.

2.6 EXTERNAL FLYBACK DIODES

External y-back diodes will offer superior reverse recovery characteris-

tics and lower forward voltage drop than the internal back-body diodes. In

high current applications, external yback diodes can reduce power dis-

sipation and heating during commutation of the motor current. Reverse

recovery time and capacitance are the most important parameters to

consider when selecting these diodes. Ultra-fast rectiers offer better re-

verse recovery time and Schottky diodes typically have low capacitance.

Individual application requirements will be the guide when determining

the need for these diodes and for selecting the component which is most

suitable.

3. POWER DISSIPATION

The thermally enhanced package of the SA57A allows several options for managing the power dissipated in the

two output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation

and switching losses. Output power dissipation depends on the quadrant of operation and whether external yback

diodes are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of

the PWM cycle as described in the typical performance graphs.

FIGURE 9. SCHOTTKY DIODES

OUT 1

OUT 2

VSVS

SA57A

TOP INPUT

BOTTOM INPUT

DELAY TIMING

OUTPUT

DISABLE

td(fall) td(dis)td(rise) td(dis)

td(dis)

FIGURE 10. TIMING DIAGRAMS

SA57A

12 SA57U

4. ORDERING AND PRODUCT STATUS INFORMATION

MODEL TEMPERATURE PACKAGE PRODUCTION STATUS

SA57AHU -40 to +125ºC 44 pin Power HSOP Slug Up

(HU package drawing)

Samples Available

TOP INPUT

BOTTOM INPUT

OUTPUT

t(fall)

t(rise)

20%

80%

FIGURE 11. OUTPUT RESPONSE

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www.apexanalog.com OCT 2012

SA57U REVF