18-Bit, 1 MSPS PulSAR 7 mW ADC in
MSOP/LFCSP
Data Sheet AD7982
FEATURES
18-bit resolution with no missing codes
Throughput: 1 MSPS
Low power dissipation
4 mW at 1 MSPS (VDD only)
7 mW at 1 MSPS (total)
70 μW at 10 kSPS
INL: ±1 LSB typical, ±2 LSB maximum
Dynamic range: 99 dB typical
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.5 V to 5.0 V
Allows use of any input range
Easy to drive with the ADA4941-1 or ADA4940-1
No pipeline delay
Single-supply 2.5 V operation with 1.8 V, 2.5 V, 3 V, and 5 V
logic interface
Proprietary serial interface SPI-/QSPI™/ MICROWIRE™-/
DSP-compatible1
Ability to daisy-chain multiple ADCs and busy indicator
10-Lead MSOP and 3 mm × 3 mm 10-Lead LFCSP
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
AD7982
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO 5V
ADA4940-1/
ADA4941-1
3- OR 4-WIRE
INTERFACE
(SPI, CS
DAISY CHAIN)
2.5V TO 5V 2.5V
06513-001
±
10V, ±5V, ..
Figure 1.
GENERAL DESCRIPTION
The AD7982 is an 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. The AD7982 contains a low power, high speed, 18-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, the AD7982 samples the voltage difference between
the IN+ and IN− pins. e voltages on these pins usually swing
in opposite phases between 0 V and VREF. The reference voltage,
VREF, is applied externally and can be set independent of the
supply voltage, VDD. Its power scales linearly with throughput.
The serial peripheral interface (SPI)-compatible serial interface
also features the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus and provides an optional
busy indicator. The AD7982 is compatible with 1.8 V, 2.5 V, 3 V,
and 5 V logic, using the separate VIO supply.
The AD7982 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
Table 1. MSOP and LFCSP 14-/16-/18-Bit PulSAR® ADCs
Bits 100 kSPS 250 kSPS
400 kSPS
to 500 kSPS ≥1000 kSPS
181 AD7989-1 AD7691 AD7690 AD7982
AD7989-5 AD7984
161 AD7684 AD7687 AD7688 AD7915
AD7693
AD7916
162 AD7680 AD7685 AD7686 AD7980
AD7683 AD7694 AD7988-5 AD7983
AD7988-1
142 AD7940 AD7942 AD7946
1 True differential.
2 Pseudo differential.
1 Protected by U.S. Patent 6,703,961.
Rev. D Document Feedback
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AD7982 Data Sheet
Rev. D | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Converter Operation .................................................................. 13
Typical Connection Diagram ................................................... 14
Analog Inputs .............................................................................. 15
Driver Amplifier Choice ........................................................... 15
Single-Ended to Differential Driver......................................... 16
Voltage Reference Input ............................................................ 16
Power Supply ............................................................................... 16
Digital Interface .......................................................................... 17
CS Mode, 3-Wire Without Busy Indicator ............................. 18
CS Mode, 3-Wire with Busy Indicator .................................... 19
CS Mode, 4-Wire Without Busy Indicator ............................. 20
CS Mode, 4-Wire with Busy Indicator .................................... 21
Chain Mode Without Busy Indicator ...................................... 22
Chain Mode with Busy Indicator ............................................. 23
Applications Information .............................................................. 24
Layout .......................................................................................... 24
Evaluating the Performance of the AD7982 ............................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
1/2017—Rev. C to Rev. D
Deleted QFN .................................................................. Throughout
Changes to Features Section, Figure 1, and Table 1 ..................... 1
Changed to VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V ....... 3
Changes to Table 2 ............................................................................ 3
Deleted VIO Range Parameter, Table 3 ......................................... 4
Changed to VIO = 2.3 V to 5.5 V to VIO = 1.71 V to 5.5 V ....... 4
Changes to VIO Parameter, Table 3 ............................................... 4
Changes to Table 4 ............................................................................ 5
Added Table 5; Renumbered Sequentially .................................... 6
Changes to Figure 5 and Table 7 ..................................................... 8
Moved Typical Performance Characteristics Section .................. 9
Changes to Figure 9 .......................................................................... 9
Changes to Figure 23 ...................................................................... 14
Changes to Analog Inputs Section and Table 9 .......................... 15
Change to Single-Ended to Differential Driver Section Title ... 16
Changes to Power Supply Section ................................................ 16
Changes to Figure 30 ...................................................................... 18
Changes to Figure 32 ...................................................................... 19
Changes to Figure 34 ...................................................................... 20
Changes to Figure 36 ...................................................................... 21
Changes to Chain Mode with Busy Indicator ............................. 23
Changes to Applications Information Section ............................ 24
Changes to Ordering Guide .......................................................... 25
6/2014—Rev. B to Rev. C
Added Patent Footnote ..................................................................... 1
7/2013—Rev. A to Rev. B
Added Low Power Dissipation of 4 mW at 1 MSPS (VDD only)
to Features Section ............................................................................ 1
Changes to Power Dissipation; Table 3 ........................................... 4
Added EPAD Notation to Figure 5 and Table 6 ............................ 7
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
10/2007—Rev. 0 to Rev. A
Changes to Table 1 and Layout ........................................................ 1
Changes to Table 2 ............................................................................. 3
Changes to Layout ............................................................................. 5
Changes to Layout ............................................................................. 6
Changes to Figure 5 ........................................................................... 7
Changes to Figure 18 and Figure 20............................................. 11
Changes to Figure 23 ...................................................................... 13
Changers to Figure 26 .................................................................... 15
Changes to Digital Interface Section ........................................... 16
Changes to Figure 38 ...................................................................... 21
Changes to Figure 40 ...................................................................... 22
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/2007—Revision 0: Initial Version
Data Sheet AD7982
Rev. D | Page 3 of 25
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range IN+ − IN− −VREF +VREF V
Absolute Input Voltage IN+ and IN− −0.1 VREF + 0.1 V
Common-Mode Input Range IN+ and IN− VREF × 0.475 VREF × 0.5 VREF × 0.525 V
Analog Input Common Mode Rejection
Ratio (CMRR)
fIN = 450 kHz 67 dB
Leakage Current at 25°C Acquisition phase 200 nA
Input Impedance See the Analog Inputs section
ACCURACY
No Missing Codes 18 Bits
Differential Linearity Error (DNL) −0.85 ±0.5 +1.5 LSB1
Integral Linearity Error (INL) −2 ±1 +2 LSB1
Transition Noise VREF = 5 V 1.05 LSB1
Gain Error, TMIN to TMAX2 −0.023 +0.004 +0.023 % of FS
Gain Error Temperature Drift ±1 ppm/°C
Zero Error, TMIN to TMAX2 ±100 +700 μV
Zero Temperature Drift 0.5 ppm/°C
Power Supply Rejection Ratio (PSRR) VDD = 2.5 V ± 5% 90 dB
THROUGHPUT
Conversion Rate VIO ≥ 2.3 V 0 1 MSPS
VIO ≥ 1.71 V 0 800 kSPS
Transient Response Full-scale step 290 ns
AC ACCURACY
Dynamic Range VREF = 5 V 97 99 dB3
V
REF = 2.5 V 93 dB3
Oversampled Dynamic Range4 F
O = 1 kSPS 129 dB3
Signal-to-Noise Ratio (SNR) fIN = 1 kHz, VREF = 5 V 95.5 98 dB3
f
IN = 1 kHz, VREF = 2.5 V 92.5 dB3
Spurious-Free Dynamic Range (SFDR) fIN = 10 kHz −115 dB3
Total Harmonic Distortion5 (THD) fIN = 10 kHz −120 dB3
Signal-to-Noise-and-Distortion (SINAD) fIN = 1 kHz, VREF = 5 V 97 dB3
1 LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 μV.
2 See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
3 All specifications expressed in decibels are referred to a full-scale input range (FSR )and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 Dynamic range is obtained by oversampling the ADC running at a throughput FS of 1 MSPS followed by postdigital filtering with an output word rate of FO.
5 Tested fully in production at fIN = 1 kHz.
AD7982 Data Sheet
Rev. D | Page 4 of 25
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE
Voltage Range 2.4 5.1 V
Load Current 1 MSPS, VREF = 5 V 350 μA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 10 MHz
Aperture Delay VDD = 2.5 V 2 ns
DIGITAL INPUTS
Logic Levels
VIL VIO > 3 V –0.3 +0.3 × VIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIL VIO ≤ 3 V –0.3 +0.1 × VIO V
VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
DIGITAL OUTPUTS
Data Format Serial 18 bits, twos complement
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 μA 0.4 V
VOH ISOURCE = −500 μA VIO − 0.3 V
POWER SUPPLIES
VDD 2.375 2.5 2.625 V
VIO 1.71 5.5 V
Standby Current1, 2 VDD and VIO = 2.5 V, 25°C 0.35 μA
Power Dissipation VDD = 2.625 V, VREF = 5 V, VIO = 3 V
Total 10 kSPS throughput 70 86 μW
1 MSPS throughput 7 8.6 mW
VDD Only 4 mW
REF Only 1.7 mW
VIO Only 1.3 mW
Energy per Conversion 7.0 nJ/sample
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Data Sheet AD7982
Rev. D | Page 5 of 25
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter Symbol Min Typ Max Unit
CONVERSION AND ACQUISTION TIMES
Conversion Time: CNV Rising Edge to Data Available tCONV 500 710 ns
Acquisition Time tACQ 290 ns
Time Between Conversions tCYC 1000 ns
CNV PULSE WIDTH (CS MODE) tCNVH 10 ns
SCK
SCK Period (CS Mode) tSCK
VIO Above 4.5 V 10.5 ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns
SCK Period (Chain Mode) tSCK
VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns
SCK Low Time tSCKL 4.5 ns
SCK High Time tSCKH 4.5 ns
SCK Falling Edge to Data Remains Valid tHSDO 3 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns
CS MODE
CNV or SDI Low to SDO D17 MSB Valid tEN
VIO Above 3 V 10 ns
VIO Above 2.3 V 15 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns
SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns
SDI Valid Hold Time from CNV Rising Edge tHSDICNV 2 ns
CHAIN MODE
SDI Valid Hold Time from CNV Rising Edge tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns
SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
1 See Figure 2 and Figure 3 for load conditions.
AD7982 Data Sheet
Rev. D | Page 6 of 25
VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 2.3 V, −40°C to +85°C, unless otherwise stated.1
Table 5.
Parameter Symbol Min Typ Max Unit
THROUGHPUT RATE 800 kSPS
CONVERSION AND AQUISITION TIMES
Conversion Time: CNV Rising Edge to Data Available tCONV 500 800 ns
Acquisition Time tACQ 290 ns
Time Between Conversions tCYC 1.25 μs
CNV PULSE WIDTH (CS MODE) tCNVH 10 ns
SCK
SCK Period (CS Mode) tSCK 22 ns
SCK Period (Chain Mode) tSCK 23 ns
SCK Low Time tSCKL 6 ns
SCK High Time tSCKH 6 ns
SCK Falling Edge to Data Remains Valid tHSDO 3 ns
SCK Falling Edge to Data Valid Delay tDSDO 14 21 ns
CS MODE
CNV or SDI Low to SDO D17 MSB Valid tEN 18 40 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance tDIS 20 ns
SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns
SDI Valid Hold Time from CNV Rising Edge tHSDICNV 10 ns
CHAIN MODE
SDI Valid Hold Time from CNV Rising Edge tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge tSSDISCK 2 ns
SDI Valid Hold Time from SCK Falling Edge tHSDISCK 3 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 22 ns
1 See Figure 2 and Figure 3 for load conditions.
500µA I
OL
500µA I
OH
1.4V
TO SDO
C
L
20pF
06513-002
Figure 2. Load Circuit for Digital Interface Timing
X% VIO
1
Y% VIO
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXIMUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
06513-003
Figure 3. Voltage Levels for Timing
Data Sheet AD7982
Rev. D | Page 7 of 25
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+, IN− to GND1 −0.3 V to VREF + 0.3 V
or ±130 mA
Supply Voltage
REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +3.0 V
VDD to VIO +3 V to −6 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead LFCSP 48.7°C/W
θJC Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead LFCSP 2.96°C/W
Lead Temperatures
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD7982 Data Sheet
Rev. D | Page 8 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7982
TOP VIEW
(Not to Scale)
06513-004
Figure 4. 10-Lead MSOP Pin Configuration
REF
VDD
IN+
IN–
GND
VIO
NOTES
1. EXPOSED PAD. FOR THE LEAD FRAME CHIP SCALE
PACKAGE (LFCSP), THE EXPOSED PAD MUST BE
CONNECTED TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.
SDI
SCK
SDO
CNV
1
2
3
4
5
10
9
8
7
6
06513-005
AD7982
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin
No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be
decoupled closely to the GND pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects
the interface mode of the device: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is
low. In chain mode, the data must be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is a data input that
daisy-chains the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is
the output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the
serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator
feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
EPAD Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad must be connected to GND.
This connection is not required to meet the electrical performances.
1AI means analog input, DI means digital input, DO means digital output, and P means power.
Data Sheet AD7982
Rev. D | Page 9 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V.
06513-006
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
INL (LSB)
0 65536 131072 196608 262144
CODE
POSIT I VE I NL: +0.79 LSB
NEGATIVE INL: –0.68 LSB
Figure 6. INL vs. Code
60000
50000
40000
30000
20000
10000
0
COUNTS
3FFF0 3FFF2 3FFF4 3FFF6 3FFF8 3FFFA 3FFFC
CODE IN HEX
00
29 745 881 43 0
06513-007
0
7795
29064
50975
32476
9064
Figure 7. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
–160
–1800 100 200 300 400 500
FREQUENCY (kHz)
AMPL ITUDE ( dB OF FULL SCALE)
06513-008
f
S
= 1MSPS
f
IN
= 2kHz
SNR = 97.3d B
THD = – 121.8dB
SFD R = 1 20.2dB
SINAD = 97.3d B
Figure 8. Fast Fourier Transform (FFT) Plot
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0 0 65536 131072 196608 262144
CODE
DNL (LSB)
06513-009
Figure 9. DNL vs. Code
50000
45000
40000
35000
30000
25000
0
COUNTS
0123456789A D
CODE IN HEX
007
145 700
06513-010
20000
15000
10000
5000
222
CB
16682
44806
43239
20013
3158
2793
Figure 10. Histogram of a DC Input at the Code Transition
100
99
98
97
96
95
94
93
92
91
90
–10–9–8–7–6–5–4–3–2–1 0
INPUT LEVEL (dB)
SNR (d B RE F ERRED T O FULL SCAL E )
06513-032
Figure 11. SNR vs. Input Level
AD7982 Data Sheet
Rev. D | Page 10 of 25
100
95
90
85
80
SNR, SINAD (dB)
06513-034
2.25 2.75 3.25 3.75 4.25 4.75 5.25
REFERENCE VOLTAGE (V)
18
17
16
15
14
ENOB (Bits)
ENOB
SNR, SINAD
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
100
98
96
94
92
90
SNR (dB)
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
06513-042
Figure 13. SNR vs. Temperature
100
95
90
85
80
0.1 1 10 100 1000
FR E QUEN C Y ( k Hz)
SINAD ( d B)
06513-031
Figure 14. SINAD vs. Frequency
06513-033
–
100
–105
–110
–115
–120
–125
–130
THD ( d B)
2.25 2.75 3.25 3.75 4.25 4.75 5.25
REFERE NCE VOLTAGE (V )
130
125
120
115
110
105
100
SFDR (dB)
THD
SFDR
Figure 15. THD and SFDR vs. Reference Voltage
–
115
–117
–119
–121
–123
–125
THD (d B)
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
06513-041
Figure 16. THD vs. Temperature
–
80
–85
–90
–95
–100
–105
–110
–115
–120
–125
0.1 1 10 100 1000
FREQUE NCY (kHz)
THD (dB)
06513-030
Figure 17. THD vs. Frequency
Data Sheet AD7982
Rev. D | Page 11 of 25
06513-036
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
OPERATING CURRENTS (mA)
2.425 2.475
SUPPLY VOLTAGE (V)
2.375 2.525 2.575 2.625
I
VDD
I
REF
I
VIO
Figure 18. Operating Currents vs. Supply Voltage
06513-038
8
7
6
5
4
3
2
1
0
POWER-DOWN CURRENTS (µA)
–55 –35 –15 5 25
TEMPERATURE (°C)
45 65 85 105 125
I
VDD
+ I
VIO
Figure 19. Power-Down Currents vs. Temperature
06513-035
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
OPERATING CURRENTS (mA)
–55 –35 –15 5 25
TEMPERATURE (°C)
45 65 85 105 125
I
VDD
I
REF
I
VIO
Figure 20. Operating Currents vs. Temperature
AD7982 Data Sheet
Rev. D | Page 12 of 25
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first code transition (from 100 … 00 to 100 … 01) must
occur at a level ½ LSB above nominal negative full scale
(−4.999981 V for the ±5 V range). The last transition (from 011
… 10 to 011 … 11) must occur for an analog voltage 1½ LSB
below the nominal full scale (+4.999943 V for the ±5 V range).
The gain error is the deviation of the difference between the
actual level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise Free Code Resolution
Noise free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dB so it includes all noise sources
and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Data Sheet AD7982
Rev. D | Page 13 of 25
THEORY OF OPERATION
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
CC
2C
65,536C 4C131,072C
LSB SW+
MSB
LSB SW–
MSB
CC
2C
65,536C 4C
131,072C
IN+
REF
GND
IN–
06513-011
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7982 is a fast, low power, single-supply, precise 18-bit
ADC using a successive approximation architecture.
The AD7982 is capable of converting 1,000,000 samples per
second (1 MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it typically consumes 70 µW,
making it ideal for battery-powered applications.
The AD7982 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7982 can interface to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP
that allows space savings and flexible configurations.
It is pin for pin compatible with the 16-bit AD7980.
CONVERTER OPERATION
The AD7982 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via Switch SW+
and Switch SW−. All independent switches are connected to the
analog inputs. Therefore, the capacitor arrays are used as
sampling capacitors and acquire the analog signal on the IN+
input and the IN− input. When the acquisition phase completes
and the CNV input goes high, a conversion phase initiates. When
the conversion phase begins, SW+ and SW− open first. The two
capacitor arrays then disconnect from the inputs and connect to
the GND input. Therefore, the differential voltage between the
IN+ and IN− inputs captured at the end of the acquisition phase
applies to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 … VREF/262,144).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of the conversion phase process, the device
returns to the acquisition phase and the control logic generates
the ADC output code and a busy signal indicator.
Because the AD7982 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
AD7982 Data Sheet
Rev. D | Page 14 of 25
Transfer Functions
The ideal transfer characteristic for the AD7982 is shown in
Figure 22 and Table 8.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE (TWOS COMPLEMENT)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
06513-012
Figure 22. ADC Ideal Transfer Function Characteristic
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output
Code (Hex)
FSR – 1 LSB +4.999962 V 0x1FFFF1
Midscale + 1 LSB +38.15 μV 0x00001
Midscale 0 V 0x00000
Midscale – 1 LSB −38.15 μV 0x3FFFF
–FSR + 1 LSB −4.999962 V 0x20001
–FSR −5 V 0x200002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 23 shows an example of the recommended connection
diagram for the AD7982 when multiple supplies are available.
2.7nF
20Ω
V–
0 TO VREF
V+
4
2.7nF
20Ω
V–
VREF TO 0
V+
4
10µF
2
REF
1
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD7982
100nF
100nF
3-WIRE INTERFACE
2.5V
1.8V TO 5V
V+
ADA4807-1
2, 3
NOTES
1
SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2
C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE RECOMMENDED LAYOUT FIGURE 41 AND FIGURE 42.
3
SEE DRIVER AMPLIFIER CHOICE SECTION.
4
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
06513-013
Figure 23. Typical Application Diagram with Multiple Supplies
Data Sheet AD7982
Rev. D | Page 15 of 25
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of the
AD7982.
The two diodes, D1 and D2, provide electrostatic discharge
(ESD) protection for the IN+ analog input and the IN− analog
input. Take care to ensure the analog input signal does not
exceed the reference input voltage (REF) by more than 0.3 V. If
the analog input signal exceeds the 0.3 V level, the diodes
become forward-biased and begin conducting current. These
diodes can handle a forward-biased current of 130 mA maximum.
However, if the supplies of the input buffer (for example, the
supplies of the ADA4807-1 in Figure 23) are different from those of
the REF, the analog input signal can eventually exceed the
supply rails by more than 0.3 V. In such a case (for example, an
input buffer with a short-circuit), the current limitation can protect
the device.
C
PIN
REF
R
IN
C
IN
D1
D2
IN+ OR IN–
GND
06513-014
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these dierential
inputs, signals common to both inputs are rejected.
90
85
80
75
70
65
601 10 100 1000 10000
FREQUENCY ( kHz )
CMRR (dB)
06513-040
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase where the switches are closed, the input
impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass
filter that reduces undesirable aliasing effects and limits noise.
When the source impedance of the driving circuit is low, the
AD7982 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7982 is easy to drive, the driver amplifier must
meet the following requirements:
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7982. The noise from the driver is
filtered by the analog input circuit of the AD7982 1-pole,
low-pass filter made by RIN and CIN, or by the external
filter, if one is used. Because the typical noise of the
AD7982 is 40 μV rms, the SNR degradation due to the
amplifier is
22 )(
2
π
40
40
log20
N
3dB
LOSS
Nef
SNR
where:
f–3dB is the input bandwidth, in megahertz, of the AD7982
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp in
nV/√Hz.
For ac applications, the driver must have a THD perfor-
mance commensurate with the AD7982.
For multichannel, multiplexed applications, the driver
amplifier and the AD7982 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit level
(0.0004%, 4 ppm). In the data sheet of the amplifier, settling at
0.1% to 0.01% is more typically specified. Settling time can
differ significantly from the settling time at an 18-bit level
and must be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4941-1 Very low noise, low power, single to differential
ADA4940-1 Very low noise, low power, single to differential
ADA4807-2 Very low noise and low power
ADA4627-1 Precision, low noise and low input bias
ADA4522-2 Precision, zero drift, and electromagnetic
interference (EMI) enhanced
ADA4500-2 Precision, rail-to-rail input and output (RRIO), and
zero input crossover distortion
AD7982 Data Sheet
Rev. D | Page 16 of 25
SINGLE-ENDED TO DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended to differential
driver allows a differential input to the device. The circuit
diagram is shown in Figure 26.
R1 and R2 set the attenuation ratio between the input range and
the ADC voltage range (VREF). R1, R2, and CF are chosen
depending on the desired input resistance, signal bandwidth,
antialiasing, and noise contribution. For example, for the ±10 V
range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. Ensure the
common mode is close to VREF/2. For example, for the ±10 V
range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 =
10.5 kΩ, and R6 = 9.76 kΩ.
06513-015
20Ω
20Ω
10µF
R1
100nF
+2.5V
+5V REF
+5.2V
–0.2V
C
F
R2
R4
R6
±10V,
±5V, ..
R3
R5
REF VDD
GND
IN+
IN–
AD7982
2.7nF
2.7nF
ADA4941-1
IN
FB
OUTP
OUTN
REF
100nF
Figure 26. Single-Ended to Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7982 voltage reference input, REF, has a dynamic input
impedance and must be driven by a low impedance source with
efficient decoupling between the REF and GND pins, as
explained in the Layout section.
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8031 or the ADA4807-1), a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If using an unbuffered reference voltage, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR435 reference.
If desired, use a reference decoupling capacitor with values as
small as 2.2 μF with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7982 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, tie VIO and VDD together. The
AD7982 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 27.
95
90
85
80
75
70
65
60
PSRR (dB)
1 10 100 1000
FREQUENCY (kHz)
06513-039
Figure 27. PSRR vs. Frequency
The AD7982 powers down automatically at the end of each
conversion phase; therefore, the power scales linearly with the
sampling rate. The power scaling linearly with throughput makes
the device ideal for low sampling rates (even of a few hertz) and low
battery-powered applications.
06513-037
10.000
1.000
0.100
0.010
0.001
OPER
A
TING CURRENTS (mA)
100000
SAMPLING RATE (SPS)
10000 1000000
I
VDD
I
VIO
I
REF
Figure 28. Operating Currents vs. Sampling Rate
Data Sheet AD7982
Rev. D | Page 17 of 25
DIGITAL INTERFACE
Although the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7982 is compatible with SPI, QSPI,
digital hosts, and digital signal processors (DSPs). In CS mode,
the AD7982 can use either a 3-wire or 4-wire interface. A 3-
wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent of
the readback timing (SDI). The 4-wire interface is useful in low
jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7982 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high, and the chain mode is selected if SDI is
low. The SDI hold time is such that when SDI and CNV are
connected together, the chain mode is always selected.
In either mode, the AD7982 offers the option of forcing a start
bit in front of the data bits. The start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.
The busy indicator feature is enabled
• In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 32 and Figure 36).
• In the chain mode if SCK is high during the CNV rising
edge (see Figure 40).
AD7982 Data Sheet
Rev. D | Page 18 of 25
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
CS mode, 3-wire without busy indicator is usually used when a
single AD7982 is connected to an SPI-compatible digital host.
The connection diagram is shown in Figure 29, and the
corresponding timing is given in Figure 30.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. After a conversion is initiated, it continues until
completion irrespective of the state of CNV. This feature can be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
When the conversion completes, the AD7982 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the 18th SCK
falling edge or when CNV goes high (whichever occurs first),
SDO returns to high impedance.
AD7982
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
06513-016
Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDO D17 D16 D15 D1 D0
tDIS
SCK 123 161718
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSIONACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
06513-017
Figure 30. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Data Sheet AD7982
Rev. D | Page 19 of 25
CS MODE, 3-WIRE WITH BUSY INDICATOR
CS mode, 3-wire with busy indicator is usually used when a
single AD7982 is connected to an SPI-compatible digital host
having an interrupt input.
The connection diagram is shown in Figure 31, and the
corresponding timing is given in Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion completes, SDO goes from high impedance
to low impedance. With a pull-up resistor on the SDO line, the
high impedance to low impedance transition can be used as an
interrupt signal to initiate the data reading controlled by the digital
host. The AD7982 then enters the acquisition phase and powers
down. The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge
or when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If multiple AD7982 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
AD7982
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
06513-018
IRQ
VIO
47kΩ
Figure 31. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDO D17 D16 D1 D0
tDIS
SCK 123 171819
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSIONACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
06513-019
Figure 32. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
AD7982 Data Sheet
Rev. D | Page 20 of 25
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
CS mode, 4-wire without busy indicator is usually used when
multiple AD7982 devices are connected to an SPI-compatible
digital host.
A connection diagram example using two AD7982 devices is
shown in Figure 33, and the corresponding timing is given in
Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers, but SDI
must be returned high before the minimum conversion time
elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
When the conversion completes, the AD7982 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the 18th SCK
falling edge or when SDI goes high (whichever occurs first), SDO
returns to high impedance and another AD7982 can be read.
AD7982
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-020
CS1
CS2
AD7982
SDI SDO
CNV
SCK
Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO D17 D16 D15 D1 D0
t
DIS
SCK 123 343536
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
S
DI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
16 17
t
SCK
t
SCKL
t
SCKH
D0 D17 D16
19 2018
S
DI(CS2)
06513-021
Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Data Sheet AD7982
Rev. D | Page 21 of 25
CS MODE, 4-WIRE WITH BUSY INDICATOR
CS mode, 4-wire with busy indictor is usually used when a
single AD7982 is connected to an SPI-compatible digital host
with an interrupt input and when it is desired to keep CNV,
which samples the analog input, independent of the signal used
to select the data reading. This independence is particularly
important in applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low.
Prior to the minimum conversion time, SDI can select other SPI
devices, such as analog multiplexers, but SDI must be returned
low before the minimum conversion time elapses and then held
low for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
the high impedance to low impedance transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7982 then enters the acquisition phase
and powers down. The data bits then clock out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the optional 19th
SCK falling edge or SDI going high (whichever occurs first),
SDO returns to high impedance.
AD7982
SDI SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-022
IRQ
VIO
47kΩ
CS1
Figure 35. CS Mode, 4-Wire with Busy Indicator Connection Diagram
SDO D17 D16 D1 D0
t
DIS
SCK 1 2 3 17 18 19
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
06513-023
Figure 36. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
AD7982 Data Sheet
Rev. D | Page 22 of 25
CHAIN MODE WITHOUT BUSY INDICATOR
Chain mode without busy indicator can be used to daisy-chain
multiple AD7982 devices on a 3-wire serial interface. The chain
mode without busy indicator feature reduces component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
Figure 37 shows a connection diagram example using two AD7982
devices, and Figure 38 shows the corresponding timing.
When SDI and CNV are low, SDO is driven low. With SCK low, a
rising edge on CNV initiates a conversion, selects the chain mode,
and disables the busy indicator.
In this mode, CNV is held high during the conversion phase and
the subsequent data readback.
When the conversion completes, the MSB is output onto SDO
and the AD7982 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can capture the data, a digital host using the SCK falling edge
allows a faster reading rate and consequently more AD7982
devices in the chain, provided the digital host has an acceptable
hold time. The maximum conversion rate can be reduced due to
the total readback time.
CONVERT
DATA IN
CLK
DIGITAL HOST
0
6513-024
AD7982
SDI SDO
CNV
B
SCK
AD7982
SDI SDO
CNV
A
SCK
Figure 37. Chain Mode Without Busy Indicator Connection Diagram
SDO
A
= SDI
B
D
A
17 D
A
16 D
A
15
SCK 1 2 3 34 35 36
t
SSDISCK
t
HSDISCK
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
16 17
t
SCK
t
SCKL
t
SCKH
D
A
0
19 2018
SDI
A
= 0
SDO
B
D
B
17 D
B
16 D
B
15 D
A
1D
B
1D
B
0D
A
17 D
A
16
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
06513-025
Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing
Data Sheet AD7982
Rev. D | Page 23 of 25
CHAIN MODE WITH BUSY INDICATOR
Chain mode with busy indicator can also daisy-chain multiple
AD7982 devices on a 3-wire serial interface while providing a
busy indicator. This chain mode with busy indicator feature
reduces component count and wiring connections, for example,
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
Figure 39 shows a connection diagram example using three
AD7982 devices, and Figure 40 shows the corresponding timing.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature.
In this mode, CNV is held high during the conversion phase
and the subsequent data readback. When all ADCs in the chain
have completed their conversions, the SDO pin of the ADC
closest to the digital host (see the AD7982 ADC labeled C in
Figure 39) is driven high. The transition of driving the SDO pin
of the ADC to high can be used as a busy indicator to trigger the
data readback controlled by the digital host. The AD7982 then
enters the acquisition phase and powers down. The data bits
stored in the internal shift register are clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 18 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge can capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7982 devices in the chain, provided the
digital host has an acceptable hold time.
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-026
AD7982
SDI SDO
CNV
C
SCK
AD7982
SDI SDO
CNV
A
SCK IRQ
AD7982
SDI SDO
CNV
B
SCK
Figure 39. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIBDA17 DA16 DA15
SCK 123 39 53 54
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
417
tSCK
tSCKH
tSCKL
DA0
19 3818
SDOB = SDICDB17 DB16 DB15 DA1DB1D
B0D
A17 DA16
55
tSSDISCK tHSDISCK
tHSDO
tDSDO
SDOCDC17 DC16 DC15 DA1D
A0DC1D
C0D
A16
21 35 3620 37
DB1D
B0D
A17DB17 DB16
tDSDOSDI
tSSCKCNV
tHSCKCNV
DA0
tDSDOSDI
tDSDOSDI
tDSDOSDI
tDSDOSDI
06513-027
Figure 40. Chain Mode with Busy Indicator Serial Interface Timing
AD7982 Data Sheet
Rev. D | Page 24 of 25
APPLICATIONS INFORMATION
LAYOUT
The printed circuit board (PCB) that houses the AD7982 must
be designed so the analog and digital sections are separated and
confined to certain areas of the PCB. The pin configuration of
the AD7982, with its analog signals on the left side and its digital
signals on the right side, eases the task of separating the analog
and digital circuitry on a PCB.
Avoid running digital lines under the device; these couple noise
onto the die, unless a ground plane under the AD7982 is used
as a shield. Fast switching signals, such as CNV or clocks, must
not run near analog signal paths. Crossover of digital and
analog signals must be avoided.
It is recommended to use at least one ground plane. It can be
common or split between the digital and analog sections. In the
latter case, the planes must be joined underneath the AD7982
devices.
The AD7982 voltage reference input REF has a dynamic input
impedance and must be decoupled with minimal parasitic
inductances. Decoupling is done by placing the reference
decoupling ceramic capacitor close to, ideally right up against,
the REF and GND pins and connecting them with wide, low
impedance traces.
Finally, decouple the power supplies of the AD7982, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7982 and connected using short, wide traces to provide
low impedance paths and to reduce the effect of glitches on the
power supply lines.
An example of layout following these rules is shown in Figure 41
and Figure 42.
EVALUATING THE PERFORMANCE OF THE AD7982
Other recommended layouts for the AD7982 are outlined in the
UG-340 user guide for the EVA L -AD7982SDZ. The evaluation
board package includes a fully assembled and tested evaluation
board, the user guide, and software for controlling the
evaluation board from a PC via the E VAL -SDP-CB1Z.
06513-028
AD7982
Figure 41. Example Layout of the AD7982 (Top Layer)
06513-029
Figure 42. Example Layout of the AD7982 (Bottom Layer)
Data Sheet AD7982
Rev. D | Page 25 of 25
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 43. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 I NDE X
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0.15)
FO R P ROPE R CO NNE CTI O N OF
THE EXPOSED PAD, REFER TO
THE PIN C ONFIG U RATION AND
FUNCTI ON DES C RIPTI ONS
SECTION OF T HIS DATA SHEET.
COPLANARITY
0.08
0
2-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 MI N
Figure 44. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option Branding Ordering Quantity
AD7982BRMZ −40°C to +85°C 10-Lead MSOP, Tube RM-10 C5F 50
AD7982BRMZRL7 −40°C to +85°C 10-Lead MSOP, 7” Reel RM-10 C5F 1,000
AD7982BCPZ-RL7 −40°C to +85°C 10-Lead LFCSP, 7” Reel CP-10-9 C5F 1,500
AD7982BCPZ-RL −40°C to +85°C 10-Lead LFCSP, 13” Reel CP-10-9 C5F 5,000
EVAL-AD7982SDZ Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS compliant part.
2 The EVAL-AD7982SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SDZ designator.
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06513-0-1/17(D)
