3.3 V Dual-Loop 50 Mbps to 1.25 Gbps
Laser Diode Driver
ADN2848
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
50 Mbps to 1.25 Gbps operation
Single 3.3 V operation
Bias current range: 2 to 100 mA
Modulation current range: 5 to 80 mA
Monitor photo diode current: 50 μA to 1200 μA
50 mA supply current at 3.3 V
Closed-loop control of power and extinction ratio
Full current parameter monitoring
Laser fail and laser degrade alarms
Automatic laser shutdown (ALS)
Optional clocked data
Supports FEC rates
32-lead, 5 mm × 5 mm LFCSP_VQ package
APPLICATIONS
SONET OC-1/3/12/24
SDH STM-0/1/4
Fibre Channel
Gigabit Ethernet
GENERAL DESCRIPTION
The ADN2848 uses a unique control algorithm to control both
the average power and the extinction ratio of the laser diode
(LD) after initial factory setup. External component count and
PCB area are low because both power and extinction ratio
control are fully integrated. Programmable alarms are provided
for laser fail (end of life) and laser degrade (impending fail).
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
GND
V
CC
LD
GND
DATAP
DATAN
CLKP
CLKN
IMODP
I
BIAS
ASET
ADN2848
I
BIAS
I
MOD
GND GND
CONTROL
IMPD
PSET
ERSET
LBWSET
ERCAP PAVCAP
GND
V
CC
CLKSEL
IMODN
V
CC
DEGRADE
FAIL
ALS
IMPDMON
IMMON
IBMON
MPD
02746-001
V
CC
R
Z
Figure 1.
ADN2848
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Theory of Operation ........................................................................ 7
Control........................................................................................... 7
Loop Bandwidth Selection .......................................................... 7
Alarms.............................................................................................7
Monitor Currents ..........................................................................8
Data and Clock Inputs..................................................................8
CCBIAS...........................................................................................8
IBIAS...................................................................................................8
Automatic Laser Shutdown..........................................................8
Alarm Interfaces ............................................................................8
Power Consumption .....................................................................9
Laser Diode Interfacing................................................................9
Optical Supervisor.........................................................................9
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Figure 1.......................................................................... 1
Changes to Specifications................................................................ 3
Changes to Figure 8........................................................................ 10
Changes to Figure 9 to Figure11................................................... 11
Updated Outline Dimensions....................................................... 12
Changes to Ordering Guide .......................................................... 12
1/03—Revision 0: Initial Version
ADN2848
Rev. A | Page 3 of 12
SPECIFICATIONS
VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1 Typical values are specified at 25°C.
Table 1.
Parameter Min Typ Max Unit Conditions/Comments
LASER BIAS Current (IBIAS, ALS)
Output Current IBIAS 2 100 mA
Compliance Voltage 1.2 VCC V IBIAS
IBIAS 0.1 mA When ALS asserted
ALS Response Time 5 μs IBIAS < 10% of nominal
CCBIAS Compliance Voltage 1.2 VCC V
MODULATION CURRENT (IMODP, IMODN)
Output Current IMOD 5 80 mA
Compliance Voltage 1.5 VCC V
IMOD 0.1 mA When ALS asserted
Rise Time2 80 170 ps
Fall Time2 80 170 ps
Random Jitter2 1 1.5 ps RMS
Pulse Width Distortion2 15 ps IMOD = 40 mA
MONITOR PD (MPD)
Current 50 1200 μA Average current
Compliance Voltage 1.65 V
POWER SET INPUT (PSET)
Capacitance 80 pF
Monitor Photodiode Current into RPSET Resistor 50 1200 μA Average current
Voltage 1.1 1.2 1.3 V
EXTINCTION RATIO SET INPUT (ERSET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
ALARM SET (ASET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
Hysteresis 5 %
CONTROL LOOP Low loop bandwidth selection
Time Constant 0.22 sec LBWSET = GND
2.25 sec LBWSET = VCC
DATA INPUTS (DATAP, DATAN, CLKP, CLKN)3
V p-p (Single-Ended, Peak-to-Peak) 100 500 mV Data and clock inputs are
Input Impedance (Single-Ended) 50 Ω ac-coupled
tSETUP4 50 ps See
Figure 2
tHOLD4 100 ps See
Figure 2
LOGIC INPUTS (ALS, LBWSET, CLKSEL)
VIH 2.4 V
VIL 0.8 V
ALARM OUTPUTS (FAIL, DEGRADE) Internal 30 kΩ pull-up
VOH 2.4 V
VOL 0.8 V
IBMON, IMMON, IMPDMON
IMMON Division Ratio 100 A/A
IMPDMON 1 A/A
Compliance Voltage 0 VCC − 1.2 V
ADN2848
Rev. A | Page 4 of 12
Parameter Min Typ Max Unit Conditions/Comments
SUPPLY
ICC5 50 mA IBIAS = IMOD = 0
VCC63.0 3.3 3.6 V
1 Temperature range is −40°C to +85°C.
2 Measured into a 25 Ω load using a 0-1 pattern at 622 Mbps.
3 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
4 Guaranteed by design and characterization. Not production tested.
5 ICCMIN for power calculation on Page 9 is the typical ICC given.
6 All VCC pins should be shorted together.
t
S
t
H
SETUP HOLD
DATAP/DATAN
CLKP
02746-002
Figure 2. Setup and Hold Time
ADN2848
Rev. A | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC to GND 4.2 V
Digital Inputs
(ALS, LBWSET, CLKSEL) −0.3 V to VCC + 0.3 V
IMODN, IMODP VCC + 1.2 V
Operating Temperature Range
Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Max) 150°C
32-Lead LFCSP_VQ Package
Power Dissipation1 (TJ Max – TA)/θJA W
θJA Thermal Impedance2 32°C/W
Lead Temperature (Soldering for 10 sec) 300°C
1Power consumption formulas are provided on Page 9.
2θJA is defined when device is soldered in a 4-layer board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADN2848
Rev. A | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
24 IBMON
23 IMMON
22 GND3
21 V
CC
3
LBWSET 1
ASET 2
ERSET 3
32 CCBIAS
20 ALS
19 FAIL
18 DEGRADE
17 CLKSEL
9
10
11
12
13
14
15
16
PSET 4
IMPD 5
IMPDMON 6
GND4 7
V
CC
48
31 I
BIAS
30 GND2
29 GND2
28 IMODP
27 GND2
26 IMODN
25 V
CC
2
ADN2848
ERCAP
PAVCAP
V
CC
1
DATAN
DATAP
GND1
CLKP
CLKN
02746-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 LBWSET Loop Bandwidth Select.
2 ASET Alarm Threshold Set Pin.
3 ERSET Extinction Ratio Set Pin.
4 PSET Average Optical Power Set Pin.
5 IMPD Monitor Photodiode Input.
6 IMPDMON Mirrored Current from Monitor Photodiode—Current Source.
7 GND4 Supply Ground.
8 VCC4 Supply Voltage.
9 ERCAP Extinction Ratio Loop Capacitor.
10 PAVCAP Average Power Loop Capacitor.
11 VCC1 Supply Voltage.
12 DATAN Data Negative Differential Terminal.
13 DATAP Data Positive Differential Terminal.
14 GND1 Supply Ground.
15 CLKP Data Clock Positive Differential Terminal. This pin is used if CLKSEL = VCC.
16 CLKN Data Clock Negative Differential Terminal. This pin is used if CLKSEL = VCC.
17 CLKSEL Clock Select (Active = VCC). This pin is used if data is clocked into chip.
18 DEGRADE DEGRADE Alarm Output.
19 FAIL FAIL Alarm Output.
20 ALS Automatic Laser Shutdown.
21 VCC3 Supply Voltage.
22 GND3 Supply Ground.
23 IMMON Modulation Current Mirror Output—Current Source.
24 IBMON Bias Current Mirror Output—Current Source.
25 VCC2 Supply Voltage.
26 IMODN Modulation Current Negative Output. Connect this pin via a matching resistor to VCC.
27 GND2 Supply Ground.
28 IMODP Modulation Current Positive Output. Connect this pin to the laser diode.
29, 30 GND2 Supply Ground.
31 IBIAS Laser Diode Bias Current—Current Sink.
32 CCBIAS Connected to Vcc When DC-Coupled to Laser Diode; Connected to IBIAS When AC-Coupled to Laser
Diode—Current Sink.
ADN2848
Rev. A | Page 7 of 12
THEORY OF OPERATION
A laser diode (LD) has current-in to light-out transfer functions, as
shown in Figure 4. Two key characteristics of this transfer function
are the threshold current, ITH, and slope in the linear region beyond
the threshold current, referred to as slope efficiency, or LI.
P1
P
AV
P0
OPTICAL POWER
I
TH
ΔP
ΔI
CURRENT
LI = ΔP
ΔI
ER = P1
P0
P
AV
= P1 + P0
2
0
2746-004
Figure 4. Laser Transfer Function
CONTROL
A monitor photodiode, MPD, is required to control the LD. The
MPD current is fed into the ADN2848 to control the power and
extinction ratio, continuously adjusting the bias current and
modulation current in response to the laser’s changing
threshold current and light-to-current slope efficiency.
The ADN2848 uses automatic power control, APC, to maintain
a constant average power over time and temperature.
The ADN2848 uses closed-loop extinction ratio control to
allow optimum setting of extinction ratio for every device.
Thus, SONET/SDH interface standards can be met over device
variation, temperature, and laser aging. Closed-loop
modulation control eliminates the need to either overmodulate
the LD or include external components for temperature
compensation. This reduces research and development time
and second sourcing issues caused by characterizing LDs.
Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected
between these pins and ground. The potentiometer RPSET is used
to change the average power. The potentiometer RERSET is used
to adjust the extinction ratio. Both PSET and ERSET are kept
1.2 V above GND.
For an initial setup, RPSET and RERSET potentiometers can be
calculated using the following formulas:
()
Ω=
AV
PSET I
RV2.1
()
Ω
×
+
−
×
=
AV
CW
CWMPD
ERSET P
ER
ER
P
I
R
1
1
V2.1
_
where:
IAV is the average MPD current.
PCW is the dc optical power specified on the laser data sheet.
IMPD_CW is the MPD current at that specified PCW.
PAV is the average power required.
ER is the desired extinction ratio (ER = P1/P0).
Note that IERSET and IPSET change from device to device; however,
the control loops determine the actual values. It is not required
to know the exact values for LI or MPD optical coupling.
LOOP BANDWIDTH SELECTION
For continuous operation, the user hardwires the LBWSET pin
high and uses 1 μF capacitors to set the actual loop bandwidth.
These capacitors are placed between the PAVCAP and ERCAP pins
and ground. It is important that these capacitors are low leakage
multilayer ceramics with an insulation resistance greater than
100 GΩ or a time constant of 1000 seconds, whichever is less.
Setting LBSET low and using 47 nF capacitors results in a
shorter loop time constant (a 10× reduction over using 1 μF
capacitors and keeping LBWSET high).
Table 4.
Operation
Mode LBWSET
Recommended
PAVCAP
Recommended
ERCAP
Continuous
50 Mbps to
1.25 Gbps
High 1 μF 1 μF
Optimized for
1.25 Gbps
Low 47 nF 47 nF
ALARMS
The ADN2848 is designed to allow interface compliance to
ITU-T-G958 (11/94), section 10.3.1.1.2 (transmitter fail) and
section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two
active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which
these alarms are raised. The current through the ASET resistor
is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE
alarm is raised at 90% of this level.
ADN2848
Rev. A | Page 8 of 12
Example:
mA45mA50 == DEGRADEFAIL IsoI
μA500
100
mA50
100 === FAIL
ASET
I
I
kΩ4.2
μA500
2.1V2.1
*===
ASET
ASET I
R
*The smallest valid value for RASET is 1.2 kΩ, because this corresponds to the
IBIAS maximum of 100 μA.
The laser degrade alarm, DEGRADE, is provided to give a
warning of imminent laser failure if the laser diode degrades
further or if environmental conditions such as increasing
temperature continue to stress the LD.
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arise:
• The ASET threshold is reached.
• The ALS pin is set high. This shuts off the modulation
and bias currents to the LD, resulting in the MPD
current dropping to zero. This gives closed-loop
feedback to the system that ALS has been enabled.
DEGRADE is raised only when the bias current exceeds 90% of
ASET current.
MONITOR CURRENTS
IBMON, IMMON, and IMPDMON are current controlled
current sources from VCC. They mirror the bias, modulation,
and MPD current for increased monitoring functionality. An
external resistor to GND gives a voltage proportional to the
current monitored.
If the monitoring function IMPDMON is not required, the
IMPD pin must be grounded and the monitor photodiode
output must be connected directly to the PSET pin.
DATA AND CLOCK INPUTS
Data and clock inputs are ac-coupled (10 nF capacitors
recommended) and terminated via a 100 Ω internal resistor
between DATAP and DATAN and also between the CLKP and
CLKN pins. There is a high impedance circuit to set the
common-mode voltage, which is designed to allow for
maximum input voltage headroom over temperature. It is
necessary that ac coupling be used to eliminate the need for
matching between common-mode voltages.
ADN2848
TO FLIP-FLOPS
50Ω50Ω
V
REG
R
R = 2.5kΩ, DATA
R = 3kΩ, CLK
400µA TYP
DATAP
DATAN
02746-005
Figure 5. AC Coupling of Data Inputs
For input signals that exceed 500 mV p-p single-ended, it is
necessary to insert an attenuation circuit as shown in Figure 6.
02746-006
DATAP/CLKP
DATAN/CLKN
R3
R1
R2
R
IN
ADN2848
NOTE THAT R
IN
= 100Ω = THE DIFFERENTIAL
INPUT IMPEDANCE OF THE ADN2848.
Figure 6. Attenuation Circuit
CCBIAS
When the laser is used in ac-coupled mode, the CCBIAS pin
and the IBIAS pin are tied together (see Figure 9). In dc-coupled
mode, CCBIAS is tied to VCC.
IBIAS
To achieve optimum optical eye quality, a pull-up resistor RZ, as
shown in Figure 8 and Figure 9, is required. The recommended
RZ value is approximately 200 Ω ~ 500 Ω.
AUTOMATIC LASER SHUTDOWN
The ADN2848 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both the bias and the
modulation currents are turned off. Correct operation of ALS is
confirmed by the FAIL alarm being raised when ALS is
asserted. Note that this is the only time that DEGRADE is low
while FAIL is high.
ALARM INTERFACES
The FAIL and DEGRADE outputs have an internal 30 kΩ pull-
up resistor that is used to pull the digital high value to VCC.
However, the alarm output can be overdriven with an external
resistor, allowing alarm interfacing to non-VCC levels. Non-VCC
alarm output levels must be below the VCC used for the
ADN2848.
ADN2848
Rev. A | Page 9 of 12
POWER CONSUMPTION
The ADN2848 die temperature must be kept below 125°C. The
LFCSP_VQ package has an exposed paddle. The exposed
paddle should be connected in such a manner that it is at the
same potential as the ADN2848 ground pins. The θJA for the
package is shown under the Absolute Maximum Ratings. Power
consumption can be calculated using
ICC = ICCMIN + 0.3 IMOD
P = VCC × ICC + (IBIAS × VBIAS_PIN) + IMOD (VMODP_PIN + VMODN_PIN)/2
TDIE = TAMBIENT + θJA × P
Thus, the maximum combination of IBIAS + IMOD must be
calculated
where:
ICCMIN = 50 mA, the typical value of ICC provided on Page 3 with
IBIAS = IMOD = 0.
TDIE = die temperature.
TAMBIENT = ambient temperature.
VBIAS_PIN = voltage at IBIAS pin.
VMODP_PIN = average voltage at IMODP pin.
VMODN_PIN = average voltage at IMODN pin.
LASER DIODE INTERFACING
Many laser diodes designed for 1.25 Gbps operation are
packaged with an internal resistor to bring the effective
impedance up to 25 Ω in order to minimize transmission line
effects. In high current applications, the voltage drop across this
resistor, combined with the laser diode forward voltage, makes
direct connection between the laser and the driver impractical
in a 3 V system. AC coupling the driver to the laser diode
removes this headroom constraint.
Caution must be used when choosing component values for
ac coupling to ensure that the time constants (L/R and RC, see
Figure 9) are sufficiently long for the data rate and the expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.
For designs with low series resistance, or where external
components become impractical, the ADN2848 supports direct
connection to the laser diode (see Figure 8). In this case, care
must be taken to ensure that the voltage drop across the laser
diode does not violate the minimum compliance voltage on the
IMODP pin.
OPTICAL SUPERVISOR
The PSET and ERSET potentiometers can be replaced with a
dual digital potentiometer, the ADN2850 (see Figure 7). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent
stability over temperature.
V
CC
V
CC
ADN2848
IMPD
PSET
ERSET
DATAP
DATAN
IDTONE
IMODP
I
BIAS
DATAP
DATAN
IDTONE
SDI
SDO
CLK
CS
DAC1
DAC2
ADN2850
V
CC
Tx
Rx
CLK
CS
02746-007
Figure 7. Application Using the ADN2850 Dual 10-Bit Digital Potentiometer
with Extremely Low Temperature Coefficient as an Optical Supervisor
ADN2848
Rev. A | Page 10 of 12
V
CC
2
IMODN
GND2
IMODP
GND2
GND2
I
BIAS
CCBIAS
CLKN
CLKP
GND1
DATAP
DATAN
V
CC
1
PAVCAP
ERCAP
LBWSET
ASET
IBMON
IMMON
FAIL
DEGRADE
ERSET
PSET
IMPD
IMPDMON
GND4
V
CC
4
GND3
V
CC
3
ALS
FAIL
DEGRADE
CLKSEL
A
LS
1kΩ
1.5kΩ15kΩ
1724
25
32
V
CC
V
CC
V
CC
10µH
LDMPD
*
**
*
** **
18
1.5kΩ
9
16
1µF
1µF
10nF
10nF
10nF
10nF
CLKN
CLKP
DATAP
DATAN
10nF 10nF 10nF10nF 10µF
V
CC
GND
EACH V
CC
SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
NOTES
DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
FOR DIGITAL PROGRAMMING. THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
*
**
ADN2848
02746-008
+
V
CC
R
Z
Figure 8. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
ADN2848
Rev. A | Page 11 of 12
V
CC
2
IMODN
GND2
IMODP
GND2
GND2
I
BIAS
CCBIAS
CLKN
CLKP
GND1
DATAP
DATAN
V
CC
1
PAVCAP
ERCAP
LBWSET
ASET
IBMON
IMMON
FAIL
DEGRADE
ERSET
PSET
IMPD
IMPDMON
GND4
V
CC
4
GND3
V
CC
3
ALS
FAIL
DEGRADE
CLKSEL
ALS
1kΩ
1.5kΩ15kΩ
1724
25
32
V
CC
V
CC
V
CC
10µH
LD
V
CC
MPD
**
*
** **
18
1.5kΩ
9
16
1µF
1µF
10nF
10nF
10nF
10nF
CLKN
CLKP
DATAP
DATAN
10nF 10nF 10nF10nF 10µF
V
CC
GND
EACH V
CC
SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
NOTES
DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
FOR DIGITAL PROGRAMMING. THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
*
**
ADN2848
*
*
*
*
*
*
02746-009
+
R
Z
Figure 9. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
02746-010
Figure 10. A 1.244 Mbps Optical Eye. Temperature at 25°C.
Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31 Pattern,
1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser.
02746-011
Figure 11. A 1.244 Mbps Optical Eye. Temperature at 85°C.
Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS 31 Pattern,
1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser.
ADN2848
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 12. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADN2848ACP-32 –40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2848ACP-32-RL –40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2848ACP-32-RL7 –40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2848ACPZ-321–40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2848ACPZ-32-RL1 –40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
ADN2848ACPZ-32-RL71 –40°C to +85°C 32-Lead LFCSP_VQ CP-32-2
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02746-0-10/06(A)
