3.3 V Dual-Loop 50 Mbps to 1.25 Gbps Laser Diode Driver ADN2848 FEATURES GENERAL DESCRIPTION 50 Mbps to 1.25 Gbps operation Single 3.3 V operation Bias current range: 2 to 100 mA Modulation current range: 5 to 80 mA Monitor photo diode current: 50 A to 1200 A 50 mA supply current at 3.3 V Closed-loop control of power and extinction ratio Full current parameter monitoring Laser fail and laser degrade alarms Automatic laser shutdown (ALS) Optional clocked data Supports FEC rates 32-lead, 5 mm x 5 mm LFCSP_VQ package The ADN2848 uses a unique control algorithm to control both the average power and the extinction ratio of the laser diode (LD) after initial factory setup. External component count and PCB area are low because both power and extinction ratio control are fully integrated. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). APPLICATIONS SONET OC-1/3/12/24 SDH STM-0/1/4 Fibre Channel Gigabit Ethernet GND IMODN VCC VCC CLKSEL DEGRADE FAIL ALS IMPDMON IMMON IBMON FUNCTIONAL BLOCK DIAGRAM VCC MPD VCC LD IMODP IMPD DATAP DATAN IMOD CLKP CLKN CONTROL PSET IBIAS VCC RZ IBIAS ASET GND ERSET GND ERCAP GND PAVCAP GND LBWSET 02746-001 GND ADN2848 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADN2848 TABLE OF CONTENTS Features .............................................................................................. 1 Alarms.............................................................................................7 Applications....................................................................................... 1 Monitor Currents ..........................................................................8 General Description ......................................................................... 1 Data and Clock Inputs..................................................................8 Functional Block Diagram .............................................................. 1 CCBIAS...........................................................................................8 Revision History ............................................................................... 2 IBIAS ...................................................................................................8 Specifications..................................................................................... 3 Automatic Laser Shutdown..........................................................8 Absolute Maximum Ratings............................................................ 5 Alarm Interfaces ............................................................................8 ESD Caution.................................................................................. 5 Power Consumption .....................................................................9 Pin Configuration and Function Descriptions............................. 6 Laser Diode Interfacing................................................................9 Theory of Operation ........................................................................ 7 Optical Supervisor.........................................................................9 Control........................................................................................... 7 Outline Dimensions ....................................................................... 12 Loop Bandwidth Selection .......................................................... 7 Ordering Guide .......................................................................... 12 REVISION HISTORY 8/06--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Figure 1.......................................................................... 1 Changes to Specifications ................................................................ 3 Changes to Figure 8........................................................................ 10 Changes to Figure 9 to Figure11................................................... 11 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 1/03--Revision 0: Initial Version Rev. A | Page 2 of 12 ADN2848 SPECIFICATIONS VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1 Typical values are specified at 25C. Table 1. Parameter LASER BIAS Current (IBIAS, ALS) Output Current IBIAS Compliance Voltage IBIAS ALS Response Time CCBIAS Compliance Voltage MODULATION CURRENT (IMODP, IMODN) Output Current IMOD Compliance Voltage IMOD Rise Time2 Fall Time2 Random Jitter2 Pulse Width Distortion2 MONITOR PD (MPD) Current Compliance Voltage POWER SET INPUT (PSET) Capacitance Monitor Photodiode Current into RPSET Resistor Voltage EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN, CLKP, CLKN)3 V p-p (Single-Ended, Peak-to-Peak) Input Impedance (Single-Ended) tSETUP4 tHOLD4 LOGIC INPUTS (ALS, LBWSET, CLKSEL) VIH VIL ALARM OUTPUTS (FAIL, DEGRADE) VOH VOL IBMON, IMMON, IMPDMON IMMON Division Ratio IMPDMON Compliance Voltage Min Typ 2 1.2 1.2 5 1.5 80 80 1 15 50 Max Unit Conditions/Comments 100 VCC 0.1 5 VCC mA V mA s V IBIAS When ALS asserted IBIAS < 10% of nominal 80 VCC 0.1 170 170 1.5 mA V mA ps ps ps ps 1200 1.65 A V pF A V 50 1.1 1.2 80 1200 1.3 1.2 1.1 1.2 25 1.3 k V 25 1.3 k V % 1.2 1.1 1.2 5 0.22 2.25 100 sec sec 500 50 mV ps 100 ps 50 2.4 0.8 V V 0.8 V V VCC - 1.2 A/A A/A V When ALS asserted RMS IMOD = 40 mA Average current Average current Low loop bandwidth selection LBWSET = GND LBWSET = VCC Data and clock inputs are ac-coupled See Figure 2 See Figure 2 Internal 30 k pull-up 2.4 100 1 0 Rev. A | Page 3 of 12 ADN2848 Parameter SUPPLY ICC 5 VCC 6 Min Typ Max Unit Conditions/Comments 50 3.3 3.6 mA V IBIAS = IMOD = 0 3.0 1 Temperature range is -40C to +85C. Measured into a 25 load using a 0-1 pattern at 622 Mbps. When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin. 4 Guaranteed by design and characterization. Not production tested. 5 ICCMIN for power calculation on Page 9 is the typical ICC given. 6 All VCC pins should be shorted together. 2 3 SETUP HOLD tS tH 02746-002 DATAP/DATAN CLKP Figure 2. Setup and Hold Time Rev. A | Page 4 of 12 ADN2848 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC to GND Digital Inputs (ALS, LBWSET, CLKSEL) IMODN, IMODP Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ Max) 32-Lead LFCSP_VQ Package Power Dissipation1 JA Thermal Impedance2 Lead Temperature (Soldering for 10 sec) Rating 4.2 V -0.3 V to VCC + 0.3 V VCC + 1.2 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -40C to +85C -65C to +150C 150C (TJ Max - TA)/JA W 32C/W 300C 1 Power consumption formulas are provided on Page 9. JA is defined when device is soldered in a 4-layer board. 2 ESD CAUTION Rev. A | Page 5 of 12 ADN2848 32 CCBIAS 31 IBIAS 30 GND2 29 GND2 28 IMODP 27 GND2 26 IMODN 25 VCC2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADN2848 TOP VIEW (Not to Scale) 24 IBMON 23 IMMON 22 GND3 21 VCC3 20 ALS 19 FAIL 18 DEGRADE 17 CLKSEL 02746-003 ERCAP PAVCAP VCC1 DATAN DATAP GND1 CLKP CLKN 9 10 11 12 13 14 15 16 LBWSET ASET ERSET PSET IMPD IMPDMON GND4 VCC4 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29, 30 31 32 Mnemonic LBWSET ASET ERSET PSET IMPD IMPDMON GND4 VCC4 ERCAP PAVCAP VCC1 DATAN DATAP GND1 CLKP CLKN CLKSEL DEGRADE FAIL ALS VCC3 GND3 IMMON IBMON VCC2 IMODN GND2 IMODP GND2 IBIAS CCBIAS Description Loop Bandwidth Select. Alarm Threshold Set Pin. Extinction Ratio Set Pin. Average Optical Power Set Pin. Monitor Photodiode Input. Mirrored Current from Monitor Photodiode--Current Source. Supply Ground. Supply Voltage. Extinction Ratio Loop Capacitor. Average Power Loop Capacitor. Supply Voltage. Data Negative Differential Terminal. Data Positive Differential Terminal. Supply Ground. Data Clock Positive Differential Terminal. This pin is used if CLKSEL = VCC. Data Clock Negative Differential Terminal. This pin is used if CLKSEL = VCC. Clock Select (Active = VCC). This pin is used if data is clocked into chip. DEGRADE Alarm Output. FAIL Alarm Output. Automatic Laser Shutdown. Supply Voltage. Supply Ground. Modulation Current Mirror Output--Current Source. Bias Current Mirror Output--Current Source. Supply Voltage. Modulation Current Negative Output. Connect this pin via a matching resistor to VCC. Supply Ground. Modulation Current Positive Output. Connect this pin to the laser diode. Supply Ground. Laser Diode Bias Current--Current Sink. Connected to Vcc When DC-Coupled to Laser Diode; Connected to IBIAS When AC-Coupled to Laser Diode--Current Sink. Rev. A | Page 6 of 12 ADN2848 THEORY OF OPERATION A laser diode (LD) has current-in to light-out transfer functions, as shown in Figure 4. Two key characteristics of this transfer function are the threshold current, ITH, and slope in the linear region beyond the threshold current, referred to as slope efficiency, or LI. P1 P1 P0 PAV = IAV is the average MPD current. PCW is the dc optical power specified on the laser data sheet. IMPD_CW is the MPD current at that specified PCW. P1 + P0 2 PAV is the average power required. ER is the desired extinction ratio (ER = P1/P0). P PAV I P LI = I P0 ITH CURRENT Note that IERSET and IPSET change from device to device; however, the control loops determine the actual values. It is not required to know the exact values for LI or MPD optical coupling. 02746-004 OPTICAL POWER ER = where: LOOP BANDWIDTH SELECTION Figure 4. Laser Transfer Function CONTROL A monitor photodiode, MPD, is required to control the LD. The MPD current is fed into the ADN2848 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser's changing threshold current and light-to-current slope efficiency. The ADN2848 uses automatic power control, APC, to maintain a constant average power over time and temperature. For continuous operation, the user hardwires the LBWSET pin high and uses 1 F capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and ERCAP pins and ground. It is important that these capacitors are low leakage multilayer ceramics with an insulation resistance greater than 100 G or a time constant of 1000 seconds, whichever is less. Setting LBSET low and using 47 nF capacitors results in a shorter loop time constant (a 10x reduction over using 1 F capacitors and keeping LBWSET high). The ADN2848 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. Thus, SONET/SDH interface standards can be met over device variation, temperature, and laser aging. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation. This reduces research and development time and second sourcing issues caused by characterizing LDs. Table 4. Average power and extinction ratio are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer RPSET is used to change the average power. The potentiometer RERSET is used to adjust the extinction ratio. Both PSET and ERSET are kept 1.2 V above GND. ALARMS For an initial setup, RPSET and RERSET potentiometers can be calculated using the following formulas: RPSET = Operation Mode Continuous 50 Mbps to 1.25 Gbps Optimized for 1.25 Gbps I MPD _ CW PCW Recommended PAVCAP 1 F Recommended ERCAP 1 F Low 47 nF 47 nF The ADN2848 is designed to allow interface compliance to ITU-T-G958 (11/94), section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two active high alarms, DEGRADE and FAIL. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE alarm is raised at 90% of this level. 1.2 V ( ) I AV RERSET = LBWSET High 1.2 V () ER - 1 x x PAV ER + 1 Rev. A | Page 7 of 12 ADN2848 Example: ADN2848 I FAIL = 50 mA so I DEGRADE = 45 mA RASET I FAIL = 100 100 TO FLIP-FLOPS DATAN = 500 A 50 50 VREG 1.2 V 1.2 *= = = 2.4 k I ASET 500 A R R = 2.5k, DATA R = 3k, CLK *The smallest valid value for RASET is 1.2 k, because this corresponds to the IBIAS maximum of 100 A. 02746-005 400A TYP The laser degrade alarm, DEGRADE, is provided to give a warning of imminent laser failure if the laser diode degrades further or if environmental conditions such as increasing temperature continue to stress the LD. Figure 5. AC Coupling of Data Inputs The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH compliant. This occurs when one of the following conditions arise: * The ASET threshold is reached. * The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system that ALS has been enabled. For input signals that exceed 500 mV p-p single-ended, it is necessary to insert an attenuation circuit as shown in Figure 6. R1 R2 DATAP/CLKP ADN2848 RIN R3 DATAN/CLKN NOTE THAT RIN = 100 = THE DIFFERENTIAL INPUT IMPEDANCE OF THE ADN2848. 02746-006 I ASET = 50 mA DATAP Figure 6. Attenuation Circuit CCBIAS DEGRADE is raised only when the bias current exceeds 90% of ASET current. MONITOR CURRENTS IBMON, IMMON, and IMPDMON are current controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality. An external resistor to GND gives a voltage proportional to the current monitored. When the laser is used in ac-coupled mode, the CCBIAS pin and the IBIAS pin are tied together (see Figure 9). In dc-coupled mode, CCBIAS is tied to VCC. IBIAS To achieve optimum optical eye quality, a pull-up resistor RZ, as shown in Figure 8 and Figure 9, is required. The recommended RZ value is approximately 200 ~ 500 . AUTOMATIC LASER SHUTDOWN If the monitoring function IMPDMON is not required, the IMPD pin must be grounded and the monitor photodiode output must be connected directly to the PSET pin. DATA AND CLOCK INPUTS Data and clock inputs are ac-coupled (10 nF capacitors recommended) and terminated via a 100 internal resistor between DATAP and DATAN and also between the CLKP and CLKN pins. There is a high impedance circuit to set the common-mode voltage, which is designed to allow for maximum input voltage headroom over temperature. It is necessary that ac coupling be used to eliminate the need for matching between common-mode voltages. The ADN2848 ALS allows compliance to ITU-T-G958 (11/94), section 9.7. When ALS is logic high, both the bias and the modulation currents are turned off. Correct operation of ALS is confirmed by the FAIL alarm being raised when ALS is asserted. Note that this is the only time that DEGRADE is low while FAIL is high. ALARM INTERFACES The FAIL and DEGRADE outputs have an internal 30 k pullup resistor that is used to pull the digital high value to VCC. However, the alarm output can be overdriven with an external resistor, allowing alarm interfacing to non-VCC levels. Non-VCC alarm output levels must be below the VCC used for the ADN2848. Rev. A | Page 8 of 12 ADN2848 P = VCC x ICC + (IBIAS x VBIAS_PIN) + IMOD (VMODP_PIN + VMODN_PIN)/2 Caution must be used when choosing component values for ac coupling to ensure that the time constants (L/R and RC, see Figure 9) are sufficiently long for the data rate and the expected number of CIDs (consecutive identical digits). Failure to do this could lead to pattern dependent jitter and vertical eye closure. For designs with low series resistance, or where external components become impractical, the ADN2848 supports direct connection to the laser diode (see Figure 8). In this case, care must be taken to ensure that the voltage drop across the laser diode does not violate the minimum compliance voltage on the IMODP pin. TDIE = TAMBIENT + JA x P OPTICAL SUPERVISOR Thus, the maximum combination of IBIAS + IMOD must be calculated The PSET and ERSET potentiometers can be replaced with a dual digital potentiometer, the ADN2850 (see Figure 7). The ADN2850 provides an accurate digital control for the average optical power and extinction ratio and ensures excellent stability over temperature. POWER CONSUMPTION The ADN2848 die temperature must be kept below 125C. The LFCSP_VQ package has an exposed paddle. The exposed paddle should be connected in such a manner that it is at the same potential as the ADN2848 ground pins. The JA for the package is shown under the Absolute Maximum Ratings. Power consumption can be calculated using ICC = ICCMIN + 0.3 IMOD where: ICCMIN = 50 mA, the typical value of ICC provided on Page 3 with IBIAS = IMOD = 0. VCC TDIE = die temperature. VCC IMPD VCC TAMBIENT = ambient temperature. ADN2850 CLK VMODN_PIN = average voltage at IMODN pin. CS PSET DAC2 ERSET CLK CS LASER DIODE INTERFACING Many laser diodes designed for 1.25 Gbps operation are packaged with an internal resistor to bring the effective impedance up to 25 in order to minimize transmission line effects. In high current applications, the voltage drop across this resistor, combined with the laser diode forward voltage, makes direct connection between the laser and the driver impractical in a 3 V system. AC coupling the driver to the laser diode removes this headroom constraint. DATAP DATAN IDTONE IBIAS 02746-007 VMODP_PIN = average voltage at IMODP pin. IMODP DAC1 IDTONE SDI SDO DATAN Tx Rx DATAP VBIAS_PIN = voltage at IBIAS pin. ADN2848 Figure 7. Application Using the ADN2850 Dual 10-Bit Digital Potentiometer with Extremely Low Temperature Coefficient as an Optical Supervisor Rev. A | Page 9 of 12 ADN2848 ALS FAIL DEGRADE 1k 1.5k 15k * CLKSEL ALS FAIL VCC3 10nF CLKN CLKP 10nF GND1 GND2 * 16 CLKN CLKP IMODN LD * GND3 VCC2 * IMODP VCC ADN2848 GND2 IBIAS 1F ERCAP VCC4 9 GND4 IMPD PSET ERSET ASET IMPDMON PAVCAP CCBIAS VCC DATAN 10nF VCC1 GND2 32 DATAP DATAN RZ 10H 10nF DATAP LBWSET 1 EACH VCC SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2848 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS. 8 ** ** 1F 1.5k VCC LD = LASER DIODE MPD = MONITOR PHOTODIODE 10nF 10nF 10nF 10nF + 10F GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED. ** FOR DIGITAL PROGRAMMING. THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED. Figure 8. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked Rev. A | Page 10 of 12 02746-008 MPD DEGRADE VCC IMMON 25 VCC 17 IBMON 24 ADN2848 FAIL ALS VCC DEGRADE 1k * * VCC2 CLKSEL FAIL ALS VCC3 DEGRADE VCC 17 GND3 25 * 15k 24 IMMON VCC 1.5k * * IBMON * IMODN 16 10nF CLKN CLKN CLKP CLKP 10nF MPD GND2 LD GND1 IMODP * * ADN2848 GND2 IBIAS ERCAP VCC4 9 GND4 IMPDMON IMPD PSET ERSET ASET LBWSET VCC 1F PAVCAP CCBIAS 32 DATAN 10nF VCC1 GND2 RZ DATAP DATAN * 10H 10nF DATAP 1 EACH V CC SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2848 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS. 8 ** ** 1F 1.5k VCC 10nF 10nF 10nF 10nF + 10F GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED. ** FOR DIGITAL PROGRAMMING. THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED. 02746-009 LD = LASER DIODE MPD = MONITOR PHOTODIODE 02746-010 02746-011 Figure 9. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked Figure 10. A 1.244 Mbps Optical Eye. Temperature at 25C. Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser. Figure 11. A 1.244 Mbps Optical Eye. Temperature at 85C. Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS 31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser. Rev. A | Page 11 of 12 ADN2848 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12 MAX 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 12. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model ADN2848ACP-32 ADN2848ACP-32-RL ADN2848ACP-32-RL7 ADN2848ACPZ-32 1 ADN2848ACPZ-32-RL1 ADN2848ACPZ-32-RL71 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Z = Pb-free part. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02746-0-10/06(A) Rev. A | Page 12 of 12 Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2