SRAM MT5C1008 Austin Semiconductor, Inc. 128K x 8 SRAM PIN ASSIGNMENT (Top View) WITH DUAL CHIP ENABLE 32-Pin DIP (C, CW) 32-Pin CSOJ (SOJ) AVAILABLE AS MILITARY SPECIFICATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS *SMD 5962-89598 *MIL-STD-883 FEATURES * * * * * * High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS process Single +5V (+10%) Power Supply Easy memory expansion with CE1\, CE2, and OE\ options. * All inputs and outputs are TTL compatible -12 (contact factory) -15 -20 -25 -35 -45 -55* -70* * Package(s)* Ceramic DIP (400 mil) Ceramic DIP (600 mil) Ceramic LCC Ceramic LCC Ceramic Flatpack Ceramic SOJ Ceramic SOJ C CW EC ECA F DCJ SOJ * 2V data retention/low power L NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-Pin LCC (ECA) A12 A14 A10 6 NC VCC A15 CE2 4 3 2 1 32 31 30 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 WE \ A13 A8 A9 A11 OE \ A10 CE1\ DQ8 14 15 16 17 18 19 20 GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. For design flexibility in high-speed memory applications, this device offers dual chip enables (CE1\, CE2) and output enable (OE\). These control pins can place the outputs in High-Z for additional flexibility in system design. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. Writing to these devices is accomplished when write enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE\ and CE2 remain HIGH and CE1\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled, allowing system designs to achieve low standby power requirements. The "L" version offers a 2V data retention mode, reducing current consumption to 1mA maximum. No. 111 No. 112 No. 207 No. 208 No. 303 No. 501 No. 507 *Electrical characteristics identical to those provided for the 45ns access devices. For more products and information please visit our web site at www.austinsemiconductor.com MT5C1008 Rev. 6.5 7/02 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 32-Pin Flat Pack (F) MARKING * Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DQ2 DQ3 VSS DQ4 DQ5 DQ6 DQ7 OPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin LCC (EC) 32-Pin SOJ (DCJ) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM MT5C1008 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM VCC I/O CONTROL DQ8 ROW DECODER A A A A A A A A A GND 1,048,576-BIT MEMORY ARRAY DQ1 (LSB) CE1\ CE2 COLUMN DECODER (LSB) A A A A A A A A OE\ WE\ POWER DOWN NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code. TRUTH TABLE MODE STANDBY STANDBY READ READ WRITE MT5C1008 Rev. 6.5 7/02 OE\ X X L H X CE1\ H X L L L CE2 X L H H H WE\ X X H H L DQ HIGH-Z HIGH-Z Q HIGH-Z D POWER STANDBY STANDBY ACTIVE ACTIVE ACTIVE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM MT5C1008 Austin Semiconductor, Inc. *Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. Refer to page 17 of this datasheet for a technical note on this subject. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range (Vcc)...............................-.5V to +6.0V Storage Temperature ....................................-65C to +150C Short Circuit Output Current (per I/O)..........................20mA Voltage on any Pin Relative to Vss................-.5V to Vcc+1 V Max Junction Temperature**.......................................+150C Power Dissipation .....................................................................1 W ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC & -45oC to +85oC; VCC = 5.0V +10%) DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.2 VCC+0.5 V 1 Input Low (Logic 0) Voltage VIL -0.5 0.8 V 1, 2 0VVIH ICCSP VCC = MAX, f = MAX = 1/tRC (MIN) Output Open *L version only ICCLP * Power Supply Current: Standby 0.4 V UNITS NOTES 3 CE\=VIH, CE2=VIL; Other Inputs at VIH, VCC = MAX f = 0 Hz CE\ > VCC -0.2V; VCC = MAX VIL < VSS -0.2V VIH > VCC -0.2V; F = 0 Hz CAPACITANCE DESCRIPTION Input Capacitance (A0-A16) Output Capacitance Input Capacitance (CE\, WE\, OE\) MT5C1008 Rev. 6.5 7/02 CONDITIONS o TA = 25 C, f = 1MHz VCC = 5V SYM MAX UNITS NOTES CI 12 pF 4 CO 14 pF 4 CI 20 pF 4 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM MT5C1008 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55oC < TC < 125oC & -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION READ CYCLE READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output disable to output in High-Z WRITE CYCLE WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z MT5C1008 Rev. 6.5 7/02 -12 -15 -20 -25 -35 -45 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE 12 tWC tCW tAW tAS tAH tWP tDS tDH 12 11 11 0 0 11 8 0 5 tLZWE tHZWE 15 12 12 3 3 20 15 15 3 3 7 7 0 3 3 7 7 0 7 3 3 0 15 12 12 0 0 12 8 0 5 3 3 0 20 ns ns ns ns ns ns ns ns ns ns 3 3 0 20 20 0 15 35 25 25 0 0 25 20 0 5 10 20 ns ns ns ns ns ns ns ns ns 45 45 15 15 10 25 20 20 0 0 20 15 0 5 9 45 35 35 10 10 8 20 15 15 0 0 15 10 0 5 7 35 25 25 8 7 7 7 25 20 20 45 35 35 0 5 35 20 0 5 15 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM MT5C1008 Austin Semiconductor, Inc. +5V +5V AC TEST CONDITIONS 480 Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 5ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load .............................. See Figures 1 and 2 Q 30 255 480 Q Fig. 1 Output Load Equivalent 7. NOTES 1. 2. 3. 4. 5. 6. All voltages referenced to VSS (GND). -2V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz. t RC (MIN) This parameter is guaranteed but not tested. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. t LZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured 200mV typical from steady state voltage, allowing for actual tester RC time constant. 8. 9. 10. 11. 12. 13. 5 pF 255 Fig. 2 Output Load Equivalent At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than t LZWE and tHZOE is less than tLZOE. WE\ is HIGH for READ cycle. Device is continuously selected. Chip enables and output enables are held in their active state. Address valid prior to, or coincident with, latest occurring chip enable. t RC = Read Cycle Time. CE2 timing is the same as CE1\ timing. The waveform is inverted. Chip enable (CE1\, CE2) and write enable (WE\) can initiate and terminate a WRITE cycle. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION SYMBOL CONDITIONS VCC for Retention Data MIN 2 VDR MAX --- UNITS NOTES V CE\ > (VCC - 0.2V) Data Retention Current VIN > (VCC - 0.2V) or < 0.2V, f=0 VCC = 2V Chip Deselect to Data Retention Time Operation Recovery Time ICCDR tCDR 0 tR tRC 1.0 mA --- ns 4 ns 4, 11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE VCC 4.5V VDR > 2V t t CDR MT5C1008 Rev. 6.5 7/02 CE1\ VIH VIL CE2 VIH VIL 1234 123456789 123 123456789 123 1234 123456789 123 1234 123456789 123 1234 123456789 123 1234 123456789 123 1234 123456789 123 1234 123456789 123 1234 4.5V R VDR