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AV-5V1-1.3
Volume 1: Device Overview and Datasheet
Arria V Device Handbook
Document last updated for Altera Complete Design Suite version:
Document publication date:
11.1
February 2012
Arria V Device Handbook Volume 1: Device Overview and
Datasheet
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ISO
9001:2008
Registered
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Chapter 1. Overview for the Arria V Device Family
Arria V Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Arria V Family Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Low-Power Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
PMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
PCS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
PCIe Gen1 and Gen2 Hard IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
FPGA GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Variable-Precision DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Dynamic and Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Clock Networks and PLL Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Enhanced Configuration and Configuration via Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
SoC FPGA with HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Features of the HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
HPS-FPGA AXI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
HPS SDRAM Controller Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
FPGA Configuration and Processor Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Hardware and Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
Chapter 2. Device Datasheet for Arria V Devices
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Temperature Sensing Diode Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
DQS Logic Block and Memory Output Clock Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . 2–35
iv Contents
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36
Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36
Configuration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
POR Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
JTAG Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
DCLK-to-DATA[] Ratio (r) for FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
FPP Configuration Timing when DCLK to DATA[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
FPP Configuration Timing when DCLK to DATA[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41
AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43
PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44
Remote System Upgrades Circuitry Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
User Watchdog Internal Oscillator Frequency Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Chapter Revision Dates
The chapters in this document, Volume 1: Device Overview and Datasheet, were
revised on the following dates. Where chapters or groups of chapters are available
separately, part numbers are listed.
Chapter 1. Overview for the Arria V Device Family
Revised: February 2012
Part Number: AV51001-1.3
Chapter 2. Device Datasheet for Arria V Devices
Revised: February 2012
Part Number: AV-51002-1.3
vi Chapter Revision Dates
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
AV51001-1.3
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
Subscribe
ISO
9001:2008
Registered
1. Overview for the Arria V Device Family
Built on the 28-nm low-power process technology, Arria® V devices offer the lowest
power and lowest system cost for mainstream applications. Arria V devices include
unique innovations such as the lowest static power in its class, the lowest power
transceivers of any midrange family, support for serial data rates up to
10.3125 gigabits per second (Gbps), a powerful collection of integrated hard
intellectual property (IP), and a power-optimized core architecture, making Arria V
devices ideal for the following applications:
■Power sensitive wireless infrastructure equipment
■20G/40G bridging, switching, and packet processing applications
■High-definition video processing and image manipulation
■Intensive digital signal processing (DSP) applications
Arria V devices are available in the following variants:
■Arria V GX—FPGA with integrated 6-Gbps transceivers, this variant provides
bandwidth, cost, and power levels that are optimized for high-volume data and
signal-processing applications.
■Arria V GT—FPGA with integrated 10-Gbps transceivers, this variant provides
enhanced high-speed serial I/O bandwidth for cost-sensitive data and signal
processing applications.
■Arria V SX—system-on-a-chip (SoC) FPGA with integrated Arria V FPGA and
ARM®-based hard processor system (HPS).
■Arria V ST—SoC FPGA with integrated Arria V FPGA, ARM-based HPS, and
10-Gbps transceivers.
The Arria V SoC FPGA variants feature an FPGA integrated with an HPS that consists
of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals, and a
shared multiport SDRAM memory controller.
The unique feature set in Arria V devices was chosen to optimize power, cost, and
performance. These features include a redesigned adaptive logic module (ALM),
distributed memory, new 10-Kbit (M10K) internal memory blocks, variable-precision
DSP blocks, and fractional clock synthesis phase-locked loops (PLLs) with a highly
flexible clocking network, all interconnected by a power-optimized MultiTrack
routing architecture.
February 2012
AV51001-1.3
1–2 Chapter 1: Overview for the Arria V Device Family
Arria V Feature Summary
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Arria V devices provide interface support flexibility with up to 10-Gbps transceivers,
1.25-Gbps LVD S, 1.333-Gbps memory interfaces with low latency, and support for all
mainstream single-ended and differential I/O standards, including 3.3 V. Arria V
devices also offer the lowest system cost by requiring only three power supplies to
operate the devices and a thermal composite flip chip ball-grid array (BGA)
packaging option. Arria V devices also support innovative features, such as
configuration via protocol (CvP), partial reconfiguration, and design security.
Arria V devices provide the power, features, and cost you require to succeed with
your designs. With these innovations, Arria V devices deliver ideal performance and
capability for a wide range of applications.
Arria V Feature Summary
Table 1–1 lists the Arria V device features.
Table 1–1. Feature Summary for Arria V Devices (Part 1 of 3)
Feature Details
Technology
■28-nm TSMC low-power process technology
■Lowest static power in its class (less than 800 mW for 500 K logic elements (LEs) at 85°C
junction under typical conditions)
■1.1-V core nominal voltage
Lowest-power serial
transceivers of any
midrange FPGA
■611-Mbps to 10.3125-Gbps integrated transceivers
■Transmit pre-emphasis and receiver equalization
■Dynamic reconfiguration of individual channels
FPGA General-purpose
I/Os (GPIOs)
■1.25-Gbps LVDS
■667-MHz/1.333-Gbps external memory interface
■On-chip termination (OCT)
■3.3-V support
Embedded transceiver
hard IP
■Custom implementation up to 10.3125 Gbps
■PCI Express® (PCIe®) Gen1 and Gen2
■Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS)
■Common Public Radio Interface (CPRI) PCS
■Gigabit-capable passive optical network (GPON) PCS
Chapter 1: Overview for the Arria V Device Family 1–3
Arria V Feature Summary
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
HPS (Arria V SX and ST
devices only)
■Dual-core ARM Cortex-A9 MPCore processor. Up to 800 MHz maximum frequency that
supports symmetric and asymmetric multiprocessing
■Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-
The-Go (OTG) controller, Quad SPI flash controller, NAND flash controller, and
SD/MMC/SDIO controller, UART, serial peripheral interface (SPI), I2C interfaces, and up to
86 GPIO interfaces
■System peripherals—general-purpose and watchdog timers, direct memory access (DMA)
controller, FPGA configuration manager, and clock and reset managers
■On-chip RAM and boot ROM
■HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-
FPGA bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and
vice versa
■FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the
multiport front end of the HPS SDRAM controller
■ARM CoreSight™ JTAG debug, trace port, and on-chip trace storage
■Three fractional PLLs
Physical medium
attachment (PMA) with
soft PCS
■10GBASE-R
■9.8304-Gbps CPRI
High-performance core
fabric
■Enhanced ALM with four registers
■Improved routing architecture to reduce congestion and improve compilation time
Variable-precision DSP
blocks
■Natively supports three-signal processing precision ranging from 9 x 9, 18 x 19, or 27 x 27
in the same DSP block
■64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
■Embedded internal coefficient memory
■Pre-adder/subtractor improves efficiency
Internal memory blocks
■M10K, 10 Kbit with soft error correction code (ECC)
■Memory logic array block (MLAB), 640-bit distributed LUTRAM—you can use up to 25% of
the LEs as MLAB memory
■Hardened double data rate3 (DDR3) and DDR2 memory controllers
High-resolution Fractional
PLLs
■Integer mode and fractional mode
■Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
Clock networks
■625-MHz global clock network
■Global, quadrant, and peripheral clock networks
■Unused clock networks can be powered down to reduce dynamic power
Table 1–1. Feature Summary for Arria V Devices (Part 2 of 3)
Feature Details
1–4 Chapter 1: Overview for the Arria V Device Family
Arria V Family Plan
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Arria V Family Plan
Arria V devices offer various thermal composite flip chip BGA packaging options
with differing price and performance points. Table 1–2 and Table 1–3 list the Arria V
devices features.
Configuration
■Partial and dynamic reconfigurations
■CvP
■Configuration via HPS
■Serial and parallel flash interface
■Enhanced advanced encryption standard (AES) design security features
■Tamper protection
■Remote system upgrade
Packaging
■Thermal composite flip chip BGA packaging
■Multiple device densities with identical package footprints for seamless migration between
different device densities
■Lead, lead-free (Pb-free), and RoHS-compliant options
Table 1–1. Feature Summary for Arria V Devices (Part 3 of 3)
Feature Details
Table 1–2. Maximum Resource Counts for Arria V GX Devices —Preliminary
Feature
Arria V GX Device
5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7
ALMs 28,302 56,100 71,698 91,680 113,208 136,880 158,491 190,240
LE (K) 75 148 190 242 300 362 420 504
M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414
MLAB memory (Kbit) 463 873 1,173 1,448 1,852 2,098 2,532 2,906
Block memory (Kbit) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140
Variable-precision DSP blocks 240 396 600 800 920 1,045 1,092 1,139
18 x 19 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,278
Fractional PLLs (1) 10 10 12 12 12 12 16 16
GPIO 480 480 544 544 704 704 704 704
LVDS transmitter (TX) (2) 68 68 120 120 160 160 156 160
LVDS receiver (RX) (2) 80 80 136 136 176 176 172 176
PCIe hard IP blocks 1 1 2 2 2 2 2 2
Hard memory controllers 2 2 4 4 4 4 4 4
Notes to Table 1–2:
(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs that are
not used by the transceiver I/O can be used as general-purpose fractional PLLs.
(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.
Chapter 1: Overview for the Arria V Device Family 1–5
Arria V Family Plan
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Table 1–3. Maximum Resource Counts for Arria V GT, SX, and ST Devices—Preliminary
Feature
Arria V GT Device Arria V SX Device Arria V ST Device
5AGTD3 5AGTD7 5ASXB3 5ASXB5 5ASTD3 5ASTD5
ALMs 136,880 190,240 132,075 174,340 132,075 174,340
LE (K) 362 504 350 462 350 462
M10K memory blocks 1,726 2,414 1,729 2,282 1,729 2,282
MLAB memory (Kb) 2,098 2,906 2,014 2,658 2,014 2,658
Block memory (Kb) 17,260 24,140 17,288 22,820 17,288 22,820
Variable-precision DSP blocks 1,045 1,156 809 1,068 809 1,068
18 x 19 multipliers 2,090 2,312 1,618 2,186 1,618 2,186
FPGA Fractional PLLs (1) 12 16 TBD TBD TBD TBD
HPS PLLs (1) — — TBD TBD TBD TBD
FPGA GPIO 704 704 528 528 528 528
HPS I/O — — 216 216 216 216
LVDS TX (2) 160 160 120 120 120 120
LVDS RX (2) 176 176 120 120 120 120
PCIe hard IP blocks 222222
Hard memory controllers443333
HPS memory controllers——1111
ARM Cortex–A9 MPCore
processor — — Dual-core Dual-core Dual-core Dual-core
Notes to Table 1–3:
(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs,
when not used by the transceiver I/O, can be used as a general-purpose fractional PLL.
(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.
1–6 Chapter 1: Overview for the Arria V Device Family
Arria V Family Plan
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 1–4 lists the Arria V package plan. The package plan shows the GPIO counts,
the maximum number of 6-Gbps transceivers available, and the maximum number of
10-Gbps transceivers available per density and package. Various combinations of
6-Gbps and 10-Gbps transceiver counts are available.
Table 1–4. Package Plan for Arria V Devices —Preliminary (1)
Varients Devices
F672 (27 mm)
Flip Chip
F896 (31 mm)
Flip Chip
F1152 (35 mm)
Flip Chip
F1517 (40 mm)
Flip Chip
GPIO XCVR GPIO
(2)
HPS
I/O XCVR GPIO HPS
I/O XCVR GPIO HPS
I/O XCVR
Arria V GX
(3)
5AGXA1 336 9 480 — 12 — — — — — —
5AGXA3 336 9 480 — 12 — — — — — —
5AGXA5 336 9 384 — 18 544 — 24 — — —
5AGXA7 336 9 384 — 18 544 — 24 — — —
5AGXB1 — — 384 — 18 544 — 24 704 — 24
5AGXB3 — — 384 — 18 544 — 24 704 — 24
5AGXB5 — — — — — 544 — 24 704 — 36
5AGXB7 — — — — — 544 — 24 704 — 36
Arria V GT
(4),(5)
5AGTD3 — — 384 — 12, 2 544 — 12, 4 704 — 12, 4
5AGTD7 — — — — — 544 — 12, 4 704 — 12, 8
Arria V SX
(3)
5ASXB3 — — 178 216 12 350 216 18 528 216 30
5ASXB5 — — 178 216 12 350 216 18 528 216 30
Arria V ST
(4),(5)
5ASTD3 — — 178 216 6, 2 350 216 12, 2 528 216 12, 6
5ASTD5 — — 178 216 6, 2 350 216 12, 2 528 216 12, 6
Notes to Table 1–4:
(1) The arrows indicate the package vertical migration capability. Vertical migration allows you to migrate across device densities for devices having
the same dedicated pins, configuration pins, and power pins for a given package.
(2) In the F896 package, the PCIe hard IP block on the right side of the 5AGXA5, 5AGXA7, 5AGXB1, 5AGXB3, and 5AGTD3 devices supports x1 for
Gen1 and Gen2 data rates.
(3) The transceiver counts listed are for 6-Gbps transceivers.
(4) The transceiver counts listed are for 6-Gbps and 10-Gbps transceivers, respectively.
(5) You can alternatively configure any pair of 10-Gbps channels as six 6-Gbps channels. For instance, you can alternatively configure the 5AGTD7
device in the F1517 package as eighteen 6-Gbps and six 10-Gbps, twenty-four 6-Gbps and four 10-Gbps, or thirty 6-Gbps and two 10-Gbps
channels.
Chapter 1: Overview for the Arria V Device Family 1–7
Low-Power Serial Transceivers
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Low-Power Serial Transceivers
Arria V devices deliver the industry’s lowest power 10-Gbps transceivers at less than
140 mW and 6-Gbps transceivers at less than 100 mW power consumption per
channel. Arria V transceivers are designed to be standard compliant for a wide range
of protocols and data rates.
The transceivers are positioned on the left and right outer edges of the device, as
shown in Figure 1–1.
Figure 1–1. Device Chip Overview for Arria V Devices (1),(2)
Notes to Figure 1–1:
(1) This figure represents an Arria V device with transceivers. Other Arria V devices may have a different floor plan than the one shown here.
(2) This figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for flip chip packages.
General Purpose I/Os (LVDS, Memory Interface)
Integrated Multiport Memory Controllers
Integrated Multiport Memory Controllers
General Purpose I/Os (LVDS, Memory Interface)
Transceiver PMA
Transceiver PMA
Hard PCS
Hard PCS
PCIe Hard IP
PCIe Hard IP
Fractional PLL
Fractional PLL
ALM
Variable-Precision DSP Blocks
M10K Internal Memory Blocks
1–8 Chapter 1: Overview for the Arria V Device Family
Low-Power Serial Transceivers
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
PMA Support
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip, ensuring optimal signal integrity. The transceiver
channels consist of the PMA, PCS, and clock networks. You can also use the unused
receiver PMA channels as additional transmit PLLs.
Table 1–5 lists the transceiver PMA features.
PCS Support
The Arria V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit
interface, depending on the transceiver data rate and protocol. Arria V devices
contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, GbE, Serial
RapidIO®(SRIO), and CPRI protocols. All other standard and proprietary protocols
from 611 Mbps to 6.5536 Gbps are supported through the custom double-width mode
(up to 6.5536 Gbps) and custom single-width mode (up to 3.75 Gbps) transceiver PCS
hard IP. A dedicated 80-bit interface to the core logic connects directly from the PMA,
bypassing the PCS hard IP, to support all protocols beyond 6.5536 Gbps up to 10.3125
Gbps.
Table 1–6 lists the transceiver PCS features.
Table 1–5. Transceiver PMA Features for Arria V Devices
Features Capability
Backplane support Up to 16” FR4 PCB fabric drive capability at up
to 6.5536 Gbps
Chip-to-chip support Up to 10.3125 Gbps
PLL-based clock recovery Superior jitter tolerance
Programmable serializer and deserializer
(SERDES) Flexible SERDES width
Equalization and pre-emphasis Up to 6 dB of pre-emphasis and 4 dB of
equalization
Ring oscillator transmit PLLs 611 Mbps to 10.3125 Gbps
Input reference clock range 27 MHz to 710 MHz
Transceiver dynamic reconfiguration Allows reconfiguration of single channels
without affecting operation of other channels
Table 1–6. Transceiver PCS Features for Arria V Devices (Part 1 of 2)
PCS Support (1) Data Rates (Gbps) Transmitter Data Path Receiver Data Path
Custom single- and
double-width modes 0.61 to ~6.5536 Phase compensation FIFO, byte
serializer, and 8B/10B encoder
Word aligner, 8B/10B decoder, byte
deserializer, and phase
compensation FIFO
PCIe Gen1: x1, x2, x4, x8
PCIe Gen2: x1, x2, x4 (2) 2.5 and 5.0
The same as custom single- and
double-width modes, plus PIPE 2.0
interface to the core logic
The same as custom single- and
double-width modes, plus rate
match FIFO and PIPE 2.0 interface
to the core logic
GbE 1.25 The same as custom single- and
double-width modes
The same as custom single- and
double-width modes, plus rate
match FIFO
Chapter 1: Overview for the Arria V Device Family 1–9
Low-Power Serial Transceivers
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
XAUI 3.125
The same as custom single- and
double-width modes, plus the XAUI
state machine for bonding four
channels
The same as custom single- and
double-width modes, plus the XAUI
state machine for realigning four
channels, and deskew FIFO circuitry
SRIO 1.25 to 6.25 The same as custom single- and
double-width modes
The same as custom single- and
double-width modes
SDI 0.27 (3), 1.485, 2.97 Phase compensation FIFO, byte
serializer
Byte deserializer and phase
compensation FIFO
Serial ATA 1.5, 3.0, 6.0 Phase compensation FIFO, byte
serializer, 8B/10B encoder
Phase compensation FIFO, byte
deserializer, word aligner, and
8B/10B decoder
CPRI (4) 0.6144 to 6.144
The same as custom single- and
double-width modes, plus the TX
deterministic latency
The same as custom single- and
double-width modes, plus the RX
deterministic latency
GPON (5) 1.25 and 2.5 Phase compensation FIFO and byte
serializer
Phase compensation FIFO and byte
deserializer
Notes to Table 1–6:
(1) Data rates above 6.5536 Gbps up to 10.3125 Gbps, such as 10GBASE-R, are supported through soft PCS.
(2) PCIe Gen2 is supported with the PCIe hard IP only.
(3) The 0.27-Gbps data rate is supported using oversampling user logics that you must implement in the FPGA fabric.
(4) CPRI data rates above 6.5536 Gbps, such as 9.8304 Gbps, are supported through soft PCS.
(5) The GPON standard does not support burst mode.
Table 1–6. Transceiver PCS Features for Arria V Devices (Part 2 of 2)
PCS Support (1) Data Rates (Gbps) Transmitter Data Path Receiver Data Path
1–10 Chapter 1: Overview for the Arria V Device Family
PCIe Gen1 and Gen2 Hard IP
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
PCIe Gen1 and Gen2 Hard IP
Arria V devices contain PCIe hard IP designed for performance, ease-of-use, and
increased functionality. The PCIe hard IP consists of the PHY MAC, data link, and
transaction layers. The PCIe hard IP supports PCIe Gen2 end point and root port for
up to x4 lane configurations, and PCIe Gen1 end point and root port for up to x8 lane
configurations. PCIe endpoint support includes multifunction support for up to eight
functions, as shown in Figure 1–2.
The Arria V PCIe hard IP operates independently from the core logic, which allows
the PCIe link to wake up and complete link training in less than 100 ms, while the
Arria V device completes loading the programming file for the rest of the device. In
addition, the Arria V PCIe hard IP has improved end-to-end data path protection
using ECC.
FPGA GPIOs
Arria V devices offer highly configurable GPIOs. The following list describes the
many features of the GPIOs:
■Programmable bus hold and weak pull-up.
■LV D S output buffer with programmable differential output voltage (VOD) and
programmable pre-emphasis.
■Dynamic on-chip parallel termination (RT OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation.
■On-chip dynamic termination to swap between serial and parallel termination,
depending on whether there is reading or writing on a common bus for signal
integrity.
■Configurable unused voltage reference (
VREF
) pins as user I/Os.
■Easy timing closure support using the hardened read FIFO in the input register
path, and delay-locked loop (DLL) delay chain with fine and coarse architecture.
Figure 1–2. PCIe Multifunction for Arria V Devices
Host CPU
Root
Complex
Memory
Controller
Local
Periph 1
Local
Periph 2
PCIe RP
PCIe Link
PCIe EP
FPGA
CAN
GbE
ATA
Bridge to
PCIe
SP1
GPIO
12C
USB
Chapter 1: Overview for the Arria V Device Family 1–11
External Memory
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
External Memory
Arria V devices support up to four hardened memory controllers for DDR3 and
DDR2 SDRAM. Each controller supports 8- to 32-bit components up to 4 gigabits (Gb)
in density with two-chip select and optional ECC. Arria V devices do not support
DDR3 SDRAM leveling.
Arria V devices also support soft memory controllers for DDR3, DDR2, LPDDR2, and
LPDDR SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM for maximum flexibility.
Table 1–7 lists the external memory interface block performance.
Table 1–7. External Memory Interface Performance for Arria V Devices
Interface Voltage (V) Hard Controller (MHz) Soft Controller (MHz)
DDR3 SDRAM
1.5 533 667
1.35 533 667
1.25 400 400
DDR2 SDRAM 1.8 400 400
1.5 400 400
RLDRAM II 1.8 (1) 400
QDR II+ SRAM 1.8 (1) 400
1.5 (1) 400
QDR II SRAM 1.8 (1) 400
1.5 (1) 400
DDR II+ SRAM (2) 1.8 (1) 400
1.5 (1) 400
LPDDR SDRAM (2) 1.8 (1) 200
LPDDR2 SDRAM (2) 1.2 (1) 400
Notes to Table 1–7:
(1) These memory interfaces are not supported in the hard memory controller.
(2) These memory interfaces are not available as Altera® IP.
1–12 Chapter 1: Overview for the Arria V Device Family
ALM
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
ALM
Arria V devices use a 28-nm ALM as the basic building block of the device fabric. The
ALM shown in Figure 1–3 uses an 8-input fracturable look-up table (LUT) with four
dedicated registers to help improve timing closure in register-rich designs and
achieve an even higher design packing capability than previous generations.
You can configure up to 25% of the ALMs in Arria V devices as distributed MLABs.
For more information, refer to “Embedded Memory” on page 1–14.
Variable-Precision DSP Block
Arria V devices feature a variable-precision DSP block that you can configure to
support signal processing with precision ranging from 9 x 9, 18 x 19, and 27 x 27 bits
natively.
You can independently configure each DSP block during compilation as a triple 9 x 9,
a dual 18 x 19 multiply, or a single 27 x 27. With a dedicated 64-bit cascade bus, you
can cascade multiple variable-precision DSP blocks to implement even higher
precision DSP functions efficiently.
The variable precision DSP block also supports these features:
■64-bit accumulator that is the largest in the industry,
■Double accumulator
■Hard pre-adder that is available in both 18- and 27-bit modes
■Cascaded output adders for efficient systolic FIR filters
■Dynamic coefficients
■18-bit internal coefficient register banks
■Enhanced independent multiplier operation
■Efficient support for single floating point arithmetic
■Inferability of all modes by the Altera Complete Design Suite
Figure 1–3. ALM for Arria V Devices
Adaptive
LUT
Full
Adder
Reg
Reg
Full
Adder
Reg
Reg
1
2
3
4
5
6
7
8
Chapter 1: Overview for the Arria V Device Family 1–13
Variable-Precision DSP Block
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Table 1–8 lists the accommodation of different configurations in a DSP block.
Table 1–9 lists the number of multipliers in Arria V devices.
Table 1–8. Variable-Precision DSP Block Configurations for Arria V Devices
Multiplier Size (Bit) DSP Block Resources Expected Usage
Three 9 x 9 1 variable-precision DSP block Low precision fixed point for video applications
Two18 x 19 1 of variable-precision DSP block Medium precision fixed point in FIR filters
Two 18 x 19 with
accumulate 1 variable-precision DSP block FIR filters
One 27 x 27 1 variable-precision DSP block Single precision floating point
Table 1–9. Number of Multipliers in Arria V Devices
Variants Devices
Variable
Precision
DSP Blocks
Independent Input and Output
Multiplications Operator 18 x 19
Multiplier
Adder Mode
18 x 18
Multiplier
Adder
Summed
with 36-bit
Input
9x9
Multipliers
18 x 19
Multipliers
27 x 27
Multipliers
Arria V GX
5AGXA1 240 720 480 240 240 240
5AGXA3 396 1,188 792 396 396 396
5AGXA5 600 1,800 1,200 600 600 600
5AGXA7 800 2,400 1,600 800 800 800
5AGXB1 920 2,760 1,840 920 920 920
5AGXB3 1,045 3,135 2,090 1,045 1,045 1,045
5AGXB5 1,092 3,276 2,184 1,092 1,092 1,092
5AGXB7 1,139 3,417 2,278 1,139 1,139 1,139
Arria V GT 5AGTD3 1,045 3,135 2,090 1,045 1,045 1,045
5AGTD7 1,139 3,417 2,278 1,139 1,139 1,139
Arria V SX 5ASXB3 809 2,427 1,618 809 809 809
5ASXB5 1,068 3,204 2,136 1068 1,068 1,068
Arria V ST 5ASTD3 809 2,427 1,618 809 809 809
5ASTD5 1,068 3,204 2,136 1068 1,068 1,068
1–14 Chapter 1: Overview for the Arria V Device Family
Embedded Memory
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Embedded Memory
The Arria V memory blocks are flexible and designed to provide an optimal amount
of small- and large-sized memory arrays. Arria V devices contain two types of
embedded memory blocks:
■640-bit MLAB blocks—for wide and shallow memories. You can use up to 25% of
the device LABs as MLAB. The MLAB operates at up to 500 MHz.
■10-Kb M10K blocks—for larger memory configurations. The M10K embedded
memory operates at up to 400 MHz.
Table 1–10 lists the supported memory configurations for Arria V devices.
Dynamic and Partial Reconfiguration
Dynamic reconfiguration enables transceiver data rates or encoding schemes to be
changed dynamically while maintaining data transfer on adjacent transceiver
channels in Arria V devices. Dynamic reconfiguration is ideal for applications
requiring on-the-fly multi-protocol or multi-rate support. You can reconfigure the
PMA, PCS, and PCIe hard IP blocks with dynamic reconfiguration.
Partial reconfiguration allows you to reconfigure part of the device while other
sections remain running. Partial reconfiguration is required in systems where the
uptime is critical because it allows you to make updates or adjust functionality
without disrupting other services. While lowering power and cost, partial
reconfiguration also increases the effective logic density by removing the necessity to
place the device functions that do not operate simultaneously. Instead, you can store
these functions in external memory and load them as required. This reduces the size
of the required device by allowing multiple applications on a single device, which
saves board space and reduces power consumption.
Altera simplifies the time-intensive task of partial reconfiguration by building the
partial reconfiguration capability on top of the proven incremental compile and
design flow in the Quartus®II software. With this Altera solution, you do not need to
know all the intricate device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You
can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to
enable partial reconfiguration of both the core and transceiver simultaneously.
Table 1–10. Embedded Memory Block Configuration for Arria V Devices
Memory Block Depth (bits) Programmable Widths
MLAB 32 x16, x18, or x20
M10K
256 x40 or x32
512 x20 or x16
1K x10 or x8
2K x5 or x4
4K x2
8K x1
Chapter 1: Overview for the Arria V Device Family 1–15
Clock Networks and PLL Clock Sources
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Clock Networks and PLL Clock Sources
The Arria V clock network architecture is based on Altera’s proven global, quadrant,
and peripheral clock structure, which is supported by dedicated clock input pins and
fractional PLLs. Arria V devices have 16 global clock networks capable of up to
625 MHz operation. The Quartus II software identifies all unused sections of the clock
network and powers them down, which reduces power consumption.
Arria V devices have up to 16 PLLs with 18 output counters per PLL. One fractional
PLL can use up to 18 output counters and two adjacent fractional PLLs share the 18
output counters. You can use fractional PLLs to reduce the number of oscillators
required on your board, as well as reduce the clock pins used in the device by
synthesizing multiple clock frequencies from a single reference clock source. You can
use the PLLs for frequency synthesis, on-chip clock deskew, jitter attenuation,
dynamic phase-shift, zero delay buffers, counters reconfiguration, bandwidth
reconfiguration, programmable output clock duty cycles, PLL cascading, and
reference clock switchover.
Arria V devices use a fractional PLL architecture in addition to the historical integer
PLL. When you use fractional PLL mode, you can use the PLLs for precision
fractional-N frequency synthesis—removing the need for an off-chip reference clock.
Transceiver fractional PLLs, when not used by the Transceiver I/O, can be used as
general-purpose fractional PLLs by the FPGA fabric.
1–16 Chapter 1: Overview for the Arria V Device Family
Enhanced Configuration and Configuration via Protocol
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Enhanced Configuration and Configuration via Protocol
Arria V devices support 3.3-V programming voltage and the following configuration
modes:
■active serial (AS)
■passive serial (PS)
■fast passive parallel (FPP)
■CvP
■Configuration via HPS
■configuration through JTAG
You can configure Arria V devices through PCIe using CvP instead of an external
flash or ROM. The CvP mode offers the fastest configuration rate and flexibility with
the easy-to-use PCIe hard IP block interface. The Arria V CvP implementation
conforms to the PCIe 100-ms power-up-to-active time requirement.
fFor more information regarding CvP, refer to the Configuration via Protocol (CvP)
Implementation in Altera FPGAs User Guide.
Table 1–11 lists the configuration modes that Arria V devices support.
Power Management
Arria V devices leverage FPGA architectural features and process technology
advancements to reduce the total device core power consumption by as much as 50%
when compared with Stratix IV devices at the same performance level.
Additionally, Arria V devices have a number of hard IP blocks that not only reduce
logic resources but also deliver substantial power savings when compared with soft
implementations. The list includes PCIe Gen1 and Gen2, XAUI, GbE, SRIO, GPON
and CPRI protocols. The hard IP blocks consume up to 25% less power than
equivalent soft implementations.
Table 1–11. Configuration Modes and Features for Arria V Devices
Mode Data Width (Bit)
Maximum
Clock Rate
(MHz)
Maximum
Data Rate
(Mbps)
Decompression Design
Security
Remote
System
Update
Partial
Reconfiguration
AS 1, 4 100 — vvv —
PS 1 125 125 vv——
FPP 8, 16 125 — vv
Parallel
flash loader 16-bit only
CvP x1, x2, x4, x8 (1) ——vvv v
HPS 32 125 — vv
Parallel
flash loader v
JTAG 1 33 33 — — — —
Note to Table 1–11:
(1) Number of lanes instead of bits.
Chapter 1: Overview for the Arria V Device Family 1–17
SoC FPGA with HPS
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Arria V transceivers are also designed for power efficiency. As a result, the transceiver
channels consume 50% less power than the previous generation of Arria devices.
SoC FPGA with HPS
Each SoC FPGA device combines an FPGA fabric and an HPS in a single device. This
combination delivers the flexibility of programmable logic with the power and cost
savings of hard IP in the following ways:
■Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
■Allows you to differentiate the end product in both the hardware and software,
and to support virtually any interface standard
■Extends the product life and revenue through in-field hardware and software
updates
Features of the HPS
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of
peripherals, and a shared multiport SDRAM memory controller, as shown in
Figure 1–4..
Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor
FPGA Fabric
HPS
HPS-to-FPGA
Lightweight
HPS-to-FPGA
FPGA-to-HPS FPGA-to-HPS SDRAM
Configuration
Controller
FPGA
Manager
64 KB
On-Chip
RAM
64 KB
Boot
ROM
Level 3
Interconnect
Ethernet
MAC (2x)
USB
OTG (2x)
NAND Flash
Controller
SD/MMC/SDIO
Controller
DMA
Controller
ETR
(Trace)
Debug
Access Port
ARM Cortex-A9 MPCore
CPU0
(ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management Unit)
CPU1
(ARM Cortex-A9
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management Unit)
SCU
ACP
L2 Cache (512 KB)
Multiport
DDR SDRAM
Controller
with
Optional ECC
Low Speed Peripherals
(Timers, GPIOs, UART, SPI, I2C, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)
1–18 Chapter 1: Overview for the Arria V Device Family
SoC FPGA with HPS
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
System Peripherals
The Ethernet MAC, USB OTG controller, NAND flash controller and SD/MMC/SDIO
controller modules have an integrated DMA controller. For modules without an
integrated DMA controller, an additional DMA controller module provides up to
eight channels for high-bandwidth data transfers. The debug access port provides
interfaces to industry standard JTAG debug probes and supports ARM CoreSight
debug and core traces to facilitate software development.
HPS-FPGA AXI Bridges
The HPS–FPGA bridges, which support the Advanced Microcontroller Bus
Architecture (AMBA®) Advanced eXtensible Interface (AXI™) specifications, consist
of the following bridges:
■FPGA-to-HPS AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the FPGA fabric to master transactions to the slaves
in the HPS
■HPS-to-FPGA AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the HPS to master transactions to the slaves in the
FPGA fabric.
■Lightweight HPS-to-FPGA AXI bridge—a lower performance 32-bit width bus
that allows the HPS to master transactions to the slaves in the FPGA fabric.
The HPS–FPGA AXI bridges also allow the FPGA fabric to access the memory shared
by one or both microprocessors, and provide asynchronous clock crossing with the
clock from the FPGA fabric.
HPS SDRAM Controller Subsystem
The HPS SDRAM controller subsystem contains a multiport SDRAM controller and
DDR PHY that is shared between the FPGA fabric (through the
FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system
interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon®
Memory-Mapped (Avalon-MM) interface standards, and provides up to four ports
with separate read and write directions.
To maximize memory performance, the HPS SDRAM controller subsystem supports
command and data reordering, deficit round-robin arbitration with aging, and
high-priority bypass features. The HPS SDRAM controller subsystem supports DDR2,
DDR3, LPDDR, or LPDDR2 devices up to 4 Gb and runs up to 533 MHz (1066 Mbps
data rate).
For easy migration, the FPGA-to-HPS SDRAM interface is compatible with the
interface of the soft SDRAM memory controller IPs and hard SDRAM memory
controllers in the FPGA fabric.
FPGA Configuration and Processor Booting
The FPGA fabric and HPS in the SoC FPGA are powered independently. You can
reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut
down the entire FPGA fabric to reduce total system power.
You can configure the FPGA fabric and boot the HPS independently, in any order,
providing you with more design flexibility:
Chapter 1: Overview for the Arria V Device Family 1–19
SoC FPGA with HPS
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
■You can boot the HPS before you power up and configure the FPGA fabric. After
the system is running, the HPS reconfigures the FPGA fabric at any time under
program control or through the FPGA configuration controller.
■You can power up both the HPS and the FPGA fabric together, configure the FPGA
fabric first, and then upload the boot code to the HPS from the FPGA fabric.
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in
the FPGA fabric to the HPS interfaces using the Qsys system integration tool in the
Quartus II software.
For software development, the ARM-based SoC FPGA devices inherit the rich
software development ecosystem available for the ARM Cortex-A9 MPCore
processor. The software development process for Altera SoC FPGAs follows the same
steps as those for other SoC devices. Altera also provides support for the Linux and
VxWorks® operating systems.
You can begin device-specific firmware and software development on the Altera
SoC FPGA Virtual Target. The Virtual Target is a PC-based fast-functional simulation
of a target development system—a model of a complete development board that runs
on a PC. The Virtual Target enables the development of device-specific production
software that can run unmodified on actual hardware.
1–20 Chapter 1: Overview for the Arria V Device Family
Ordering Information
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Ordering Information
This section describes the ordering information for Arria V devices.
Figure 1–5 and Figure 1–6 show the ordering codes for Arria V devices.
Figure 1–5. Ordering Information for Arria V GX and GT Devices
GX Variant
A1: 75K logic elements
A3: 149K logic elements
A5: 190K logic elements
A7: 243K logic elements
B1: 300K logic elements
B3: 362K logic elements
B5: 420K logic elements
B7: 503K logic elements
GT Variant
D3: 362K logic elements
D7: 503K logic elements
Family Signature
Embedded Hard IPs Transceiver Count
Transceiver Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
GX : 6-Gbps transceivers
GT : 10-Gbps transceivers
B : No hard PCIe or hard
memory controller
M : 1 hard PCIe and 2 hard
memory controller
F : Maximum 2 hard PCIe and
4 hard memory controllers
5A : Arria V
D : 9
E : 12
G : 18
H : 24
K : 36
F : FineLine BGA (FBGA)
FBGA Package Type
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
40 : 1,517 pins
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
N : Lead-free packaging
ES : Engineering sample
5A GX M A5 G 4 F 31 C 4 N
Member Code
Family Variant
GX Variant
4 : 6-Gbps
6 : 3-Gbps
GT Variant
3 : 10-Gbps
GX Variant
4 (fastest)
5
6
GT Variant
5
Chapter 1: Overview for the Arria V Device Family 1–21
Document Revision History
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Document Revision History
Table 1–12 lists the revision history for this chapter.
Figure 1–6. Ordering Information for Arria V SX and ST Devices
Family Signature
Embedded Hard IPs
Transceiver Count
Transceiver Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
SX : 6-Gbps transceivers
ST : 10-Gbps transceivers
B : No hard PCIe or hard
memory controller
M : 1 hard PCIe and 2 hard
memory controller
F : Maximum 2 hard PCIe and
3 hard memory controllers
(These numbers do not include the
hard memory controllers in the HPS)
SX Variant
B3 : 350K logic elements
B5 : 460K logic elements
ST Variant
D3 : 350K logic elements
D5 : 460K logic elements
5A : Arria V
SX Variant
(6-Gbps)
D : 9
E : 12
G : 18
H : 24
ST Variant
(6-Gbps, 10-Gbps)
E : 6, 2
G : 18, 2
K : 12, 6
SX Variant
4 : 6-Gbps
6 : 3-Gbps
ST Variant
3 : 10-Gbps
F : FineLine BGA (FBGA)
FBGA Package Type
31 : 896 pins
35 : 1,152 pins
40 : 1,517 pins
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
SX Variant
4 (fastest)
5
6
ST Variant
5
N : Lead-free packaging
ES : Engineering sample
5A ST FD5 K 4 F40 I5
N
Member Code
Family Variant
Table 1–12. Document Revision History
Date Version Changes
February 2012 1.3
■Updated Table 1–2 and Table 1–3.
■Updated Figure 1–5 and Figure 1–6.
■Minor text edits.
December 2011 1.2 ■Minor text edits.
November 2011 1.1
■Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–6, Table 1–7, Table 1–9, and
Table 1–10.
■Added “SoC FPGA with HPS” section.
■Updated “Clock Networks and PLL Clock Sources” and “Ordering Information” sections.
■Updated Figure 1–5.
■Added Figure 1–6.
■Minor text edits.
August 2011 1.0 Initial release.
1–22 Chapter 1: Overview for the Arria V Device Family
Document Revision History
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
AV-51002-1.3
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
Subscribe
ISO
9001:2008
Registered
2. Device Datasheet for Arria V Devices
This chapter describes the electrical characteristics, switching characteristics, and
configuration specifications for Arria® V devices. Electrical characteristics include
operating conditions and power consumption. Switching characteristics include
transceiver specifications, and core and periphery performance. Configuration
specifications include power-on reset (POR) specification, initialization clock source
option and timing, various configuration mode timing parameters, remote system
upgrades timing, and user watchdog internal oscillator frequency specification. This
chapter also describes I/O timing, including programmable I/O element (IOE) delay
and programmable output buffer delay.
fFor more information about the densities and packages of devices in the Arria V
family, refer to the Overview for Arria V Device Family chapter.
Electrical Characteristics
The following sections describe the electrical characteristics of Arria V devices.
Operating Conditions
When you use Arria V devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of the
Arria V devices, you must consider the operating requirements described in this
chapter.
Arria V devices are offered in commercial and industrial grades. Commercial devices
are offered in –4 (fastest), –5, and –6 speed grades. Industrial grade devices are offered
in the –5 speed grade.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Arria V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
February 2012
AV-51002-1.3
2–2 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
cConditions other than those listed in Table 2–1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 2–1. Absolute Maximum Ratings for Arria V Devices—Preliminary
Symbol Description Minimum Maximum Unit
VCC Core voltage power supply –0.5 1.35 V
VCCP
Periphery circuitry, PCIe® hard IP block, and transceiver physical
coding sublayer (PCS) power supply –0.5 1.35 V
VCCPGM Configuration pins power supply –0.5 3.75 V
VCCAUX Auxiliary supply –0.5 3.75 V
VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.75 V
VCCPD I/O pre-driver power supply –0.5 3.75 V
VCCIO I/O power supply –0.5 3.9 V
VCCD_FPLL Phase-locked loop (PLL) digital power supply –0.5 1.8 V
VCCA_FPLL PLL analog power supply –0.5 3.75 V
VCCA_GXB Transceiver high voltage power –0.5 3.75 V
VCCH_GXB Transmitter output buffer power –0.5 1.8 V
VCCR_GXB Receiver power –0.5 1.21 V
VCCT_GXB Transmitter power –0.5 1.21 V
VCCL_GXB Clock network power –0.5 1.21 V
VIDC input voltage –0.5 4 V
IOUT DC output current per pin –25 40 mA
TJOperating junction temperature –55 125 °C
TSTG Storage temperature (No bias) –65 150 °C
VCC_HPS Core voltage power supply –0.5 1.35 V
VCCPD_HPS I/O pre-driver power supply –0.5 3.75 V
VCCIO_HPS I/O power supply –0.5 3.9 V
VCCRSTCLK_HPS Configuration pins power supply –0.5 3.75 V
VCCPLL_HPS PLL analog power supply –0.5 3.75 V
Chapter 2: Device Datasheet for Arria V Devices 2–3
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2–2 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% duty cycle. For example, a signal that
overshoots to 3.95 V can only be at 3.95 V for ~5% over the lifetime of the device; for a
device lifetime of 10 years, this amounts to half a year.
Table 2–2. Maximum Allowed Overshoot During Transitions for Arria V Devices—Preliminary
Symbol Description Condition (V) Overshoot Duration as %
of High Time Unit
Vi (AC) AC input voltage
3.7 100 %
3.75 59.79 %
3.8 33.08 %
3.85 18.45 %
3.9 10.36 %
3.95 5.87 %
43.34%
4.05 1.92 %
4.1 1.11 %
2–4 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for
Arria V devices. Table 2–3 lists the steady-state voltage values expected from Arria V
devices. Power supply ramps must all be strictly monotonic, without plateaus.
Table 2–3. Recommended Operating Conditions for Arria V Devices—Preliminary
Symbol Description Condition Minimum Typical Maximum Unit
VCC Core voltage power supply — 1.07 1.1 1.13 V
VCCP
Periphery circuitry, PCIe hard IP block, and
transceiver PCS power supply — 1.07 1.1 1.13 V
VCCAUX Auxiliary supply — 2.375 2.5 2.625 V
VCCPD (1)
I/O pre-driver (3.3 V) power supply — 3.135 3.3 3.465 V
I/O pre-driver (3.0 V) power supply — 2.85 3.0 3.15 V
I/O pre-driver (2.5 V) power supply — 2.375 2.5 2.625 V
VCCIO
I/O buffers (3.3 V) power supply — 3.135 3.3 3.465 V
I/O buffers (3.0 V) power supply — 2.85 3.0 3.15 V
I/O buffers (2.5 V) power supply — 2.375 2.5 2.625 V
I/O buffers (1.8 V) power supply — 1.71 1.8 1.89 V
I/O buffers (1.5 V) power supply — 1.425 1.5 1.575 V
I/O buffers (1.35 V) power supply — 1.283 1.35 1.418 V
I/O buffers (1.25 V) power supply — 1.19 1.25 1.31 V
I/O buffers (1.2 V) power supply — 1.14 1.2 1.26 V
VCCPGM
Configuration pins (3.3 V) power supply — 3.135 3.3 3.465 V
Configuration pins (3.0 V) power supply — 2.85 3.0 3.15 V
Configuration pins (2.5 V) power supply — 2.375 2.5 2.625 V
Configuration pins (1.8 V) power supply — 1.71 1.8 1.89 V
VCCA_FPLL PLL analog voltage regulator power supply — 2.375 2.5 2.625 V
VCCD_FPLL PLL digital voltage regulator power supply — 1.425 1.5 1.575 V
VCCBAT (2) Battery back-up power supply
(For design security volatile key register) — 1.2—3.0V
VIDC input voltage — –0.5 — 3.6 V
VOOutput voltage — 0 — VCCIO V
TJ Operating junction temperature Commercial 0 — 85 °C
Industrial –40 — 100 °C
tRAMP (3) Power supply ramp time
Slow POR
(PORSEL=0) 200 µs — 100 ms —
Fast POR
(PORSEL=1) 200 µs — 4 ms —
Notes to Table 2–3:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(2) If you do not use the design security feature in Arria V devices, connect VCCBAT to a 1.5-V, 2.5-V or 3.0-V power supply. Arria V POR circuitry
monitors VCCBAT
. Arria V devices do not exit POR if VCCBAT stays low.
(3) When power is applied to an Arria V device, a POR occurs if the power supply reaches the recommended operating range in the maximum
power supply ramp.
Chapter 2: Device Datasheet for Arria V Devices 2–5
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Table 2–4 lists the transceiver power supply recommended operating conditions for
Arria V devices.
Table 2–5 lists the steady-state voltage and current values expected from Arria V
system-on-a-chip (SoC) FPGA with ARM®-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus.
Table 2–4. Transceiver Power Supply Operating Conditions for Arria V GX and GT Devices—Preliminary
Symbol Description Minimum Typical Maximum Unit
VCCA_GXBL Transceiver high voltage power (left side) 2.375 2.5 2.625 V
VCCA_GXBR Transceiver high voltage power (right side)
VCCR_GXBL Receiver power (left side) 1.07 1.1 1.13 V
VCCR_GXBR Receiver power (right side)
VCCT_GXBL Transmitter power (left side) 1.07 1.1 1.13 V
VCCT_GXBR Transmitter power (right side)
VCCH_GXBL Transmitter output buffer power (left side) 1.425 1.5 1.575 V
VCCH_GXBR Transmitter output buffer power (right side)
VCCL_GXBL Clock network power (left side) 1.07 1.1 1.13 V
VCCL_GXBR Clock network power (right side) 1.07 1.1 1.13 V
Table 2–5. HPS Power Supply Operating Conditions for Arria V SX and ST Devices—Preliminary
Symbol Description Minimum Typical Maximum Unit
VCC_HPS HPS Core voltage and periphery circuitry power supply 1.07 1.1 1.13 V
VCCPD_HPS
HPS I/O pre-driver (3.3 V) power supply 3.135 3.3 3.465 V
HPS I/O pre-driver (3.0 V) power supply 2.85 3.0 3.15 V
HPS I/O pre-driver (2.5 V) power supply 2.375 2.5 2.625 V
VCCIO_HPS
HPS I/O buffers (3.3 V) power supply 3.135 3.3 3.465 V
HPS I/O buffers (3.0 V) power supply 2.85 3.0 3.15 V
HPS I/O buffers (2.5 V) power supply 2.375 2.5 2.625 V
HPS I/O buffers (1.8 V) power supply 1.71 1.8 1.89 V
HPS I/O buffers (1.5 V) power supply 1.425 1.5 1.575 V
HPS I/O buffers (1.2 V) power supply 1.14 1.2 1.26 V
VCCRSTCLK_HPS
HPS reset and clock input pins (3.3 V) power supply 3.135 3.3 3.465 V
HPS reset and clock input pins (3.0 V) power supply 2.85 3.0 3.15 V
HPS reset and clock input pins (2.5 V) power supply 2.375 2.5 2.625 V
HPS reset and clock input pins (1.8 V) power supply 1.71 1.8 1.89 V
VCCPLL_HPS HPS PLL analog voltage regulator power supply 2.375 2.5 2.625 V
2–6 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to estimate supply
current for your design because these currents vary greatly with the resources you
use.
fFor more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
I/O Pin Leakage Current
Table 2–6 lists the Arria V I/O pin leakage current specifications.
Bus Hold Specifications
Table 2–7 lists the Arria V device bus hold specifications.
Table 2–6. I/O Pin Leakage Current for Arria V Devices—Preliminary
Symbol Description Conditions Min Typ Max Unit
IIInput pin VI = 0 V to VCCIOMAX –30 — 30 µA
IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA
Table 2–7. Bus Hold Parameters for Arria V Devices—Preliminary (1) (Part 1 of 2)
Parameter Symbol Conditions
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold,
low,
sustaining
current
ISUSL
VIN > VIL
(max.) 8 — 12 — 30—50—70—70—µA
Bus-hold,
high,
sustaining
current
ISUSH
VIN < VIH
(min.) –8 — –12 — –30 — –50 — –70 — -70 — µA
Bus-hold,
low,
overdrive
current
IODL
0V < VIN <
VCCIO
— 125 — 175 — 200 — 300 — 500 — 500 µA
Chapter 2: Device Datasheet for Arria V Devices 2–7
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
(OCT) Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically
performed at power up for I/Os connected to the calibration block. Table 2–8 lists the
Arria V OCT termination calibration accuracy specifications.
Bus-hold,
high,
overdrive
current
IODH
0V < VIN <
VCCIO
— -125 — -175 — -200 — -300 — -500 — -500 µA
Bus-hold
trip point VTRIP — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
Note to Table 2–7:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Table 2–7. Bus Hold Parameters for Arria V Devices—Preliminary (1) (Part 2 of 2)
Parameter Symbol Conditions
VCCIO (V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Table 2–8. OCT Calibration Accuracy Specifications for Arria V Devices—Preliminary (1) (Part 1 of 2)
Symbol Description Conditions (V)
Calibration Accuracy
Unit
C4 C5, I5 C6
25- RS
Internal series termination
with calibration
(25- setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 ±15 ±15 ±15 %
50- RS
Internal series termination
with calibration
(50- setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 ±15 ±15 ±15 %
34- and 40- RS
Internal series termination
with calibration
(34- and 40- setting)
VCCIO = 1.5, 1.35,
1.25, 1.2 ±15 ±15 ±15 %
48-60-and
80- RS
Internal series termination
with calibration
(48-, 60-, and 80-
setting)
VCCIO = 1.2 ±15 ±15 ±15 %
50- RT
Internal parallel
termination with
calibration (50- setting)
VCCIO = 2.5, 1.8, 1.5,
1.2 –10 to +40 –10 to +40 –10 to +40 %
20-, 30-,
40-,60-and
120- RT
Internal parallel
termination with
calibration
(20-, 30-, 40-,
60-, and 120- setting)
VCCIO = 1.5, 1.35, 1.25 –10 to +40 –10 to +40 –10 to +40 %
2–8 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and
on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration,
the tolerance may change.
Table 2–9 lists the Arria V OCT without calibration resistance tolerance to PVT
changes.
60- and 120-RT
Internal parallel
termination with
calibration
(60- and 120- setting)
VCCIO = 1.2 –10 to +40 –10 to +40 –10 to +40 %
25- RS_left_shift
Internal left shift series
termination with
calibration
(25- RS_left_shift setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 ±15 ±15 ±15 %
Note to Table 2–8:
(1) OCT calibration accuracy is valid at the time of calibration only.
Table 2–8. OCT Calibration Accuracy Specifications for Arria V Devices—Preliminary (1) (Part 2 of 2)
Symbol Description Conditions (V)
Calibration Accuracy
Unit
C4 C5, I5 C6
Table 2–9. OCT Without Calibration Resistance Tolerance Specifications for Arria V Devices—Preliminary
Symbol Description Conditions (V)
Resistance Tolerance
Unit
C4 C5, I5 C6
25- RS
Internal series termination
without calibration
(25- setting)
VCCIO = 3.0 and 2.5 ±30 ±40 ±40 %
25- RS
Internal series termination
without calibration
(25- setting)
VCCIO = 1.8 and 1.5 ±30 ±40 ±40 %
25-RS
Internal series termination
without calibration
(25- setting)
VCCIO = 1.2 ±35 ±50 ±50 %
50- RS
Internal series termination
without calibration (50-
setting)
VCCIO = 3.0 and 2.5 ±30 ±40 ±40 %
50- RS
Internal series termination
without calibration
(50- setting)
VCCIO = 1.8 and 1.5 ±30 ±40 ±40 %
50- RS
Internal series termination
without calibration
(50- setting)
VCCIO = 1.2 ±35 ±50 ±50 %
100- RD
Internal differential
termination (100- setting) VCCIO = 2.5 ±25 TBD TBD %
Chapter 2: Device Datasheet for Arria V Devices 2–9
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
OCT calibration is automatically performed at power up for OCT-enabled I/Os.
Table 2–10 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 2–10 to determine the OCT variation after power-up calibration
and Equation 2–1 to determine the OCT variation without recalibration.
Table 2–10 lists the OCT variation after the power-up calibration.
Pin Capacitance
Table 2–11 lists the Arria V pin capacitance.
Equation 2–1. OCT Variation Without Recalibration—Preliminary (1), (2), (3), (4), (5), (6)
Notes to Equation 2–1:
(1) The ROCT value calculated from Equation 2–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power up.
(4) V is the variation of voltage with respect to the VCCIO at power up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 2–10. OCT Variation after Power-Up Calibration for Arria V Devices—Preliminary (1)
Symbol Description VCCIO (V) Value Unit
dR/dV OCT variation of voltage without
recalibration
3.0 0.0297
%/mV
2.5 0.0344
1.8 0.0499
1.5 0.0744
1.2 0.1241
dR/dT OCT variation of temperature without
recalibration
3.0 0.189
%/°C
2.5 0.208
1.8 0.266
1.5 0.273
1.2 0.317
Note to Table 2–10:
(1) Valid for a VCCIO range of ±5% and temperature range of 0° to 85°C.
Table 2–11. Pin Capacitance for Arria V Devices
Symbol Description Value Unit
CIOTB Input capacitance on top/bottom I/O pins 5.5 pF
CIOLR Input capacitance on left/right I/O pins 5.5 pF
COUTFB Input capacitance on dual-purpose clock output/feedback pins 5.5 pF
ROCT RSCAL 1dR
dT
-------T
dR
dV
------- V+


=
2–10 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Hot Socketing
Table 2–12 lists the hot socketing specifications for Arria V devices.
Internal Weak Pull-Up Resistor
Table 2–13 lists the weak pull-up resistor values for Arria V devices.
Table 2–12. Hot Socketing Specifications for Arria V Devices—Preliminary
Symbol Description Maximum
IIOPIN (DC) DC current per I/O pin 300 A
IIOPIN (AC) AC current per I/O pin 8 mA (1)
IXCVR-TX (DC)
DC current per transceiver transmitter (TX)
pin 100 mA
IXCVR-RX (DC) DC current per transceiver receiver (RX) pin 50 mA
Note to Table 2–12:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Table 2–13. Internal Weak Pull-Up Resistor Values for Arria V Devices—Preliminary (1), (2)
Symbol Description Conditions (V) (3) Value (4) Unit
RPU
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
VCCIO = 3.3 ±5% 25 k
VCCIO = 3.0 ±5% 25 k
VCCIO = 2.5 ±5% 25 k
VCCIO = 1.8 ±5% 25 k
VCCIO = 1.5 ±5% 25 k
VCCIO = 1.35 ±5% 25 k
VCCIO = 1.25 ±5% 25 k
VCCIO = 1.2 ±5% 25 k
Notes to Table 2–13:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG
TCK
pin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(4) Valid with ±10% tolerances to cover changes over PVT.
Chapter 2: Device Datasheet for Arria V Devices 2–11
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
I/O Standard Specifications
Table 2–14 through Table 2–19 list the input voltage (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Arria V devices. The I/O standards tables also list the Arria V
device family I/O standard specifications. The VOL and VOH values are valid at the
corresponding IOH and IOL, respectively.
For an explanation of terms used in Table 2–14 through Table 2–19, refer to “Glossary”
on page 2–48.
Table 2–14. Single-Ended I/O Standards for Arria V Devices—Preliminary
I/O Standard
VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL
(mA)
IOH
(mA)
Min Typ Max Min Max Min Max Max Min
3.3-V LVTTL 3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.45 2.4 4 –4
3.3-V
LVCMOS 3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2
3.0-V LVTTL 2.85 3 3.15 –0.3 0.8 1.7 3.6 0.4 2.4 2 –2
3.0-V
LVCMOS 2.85 3 3.15 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 0.1 –0.1
3.0-V PCI 2.85 3 3.15 — 0.3 x VCCIO 0.5 x VCCIO
VCCIO +
0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 –0.5
3.0-V PCI-X 2.85 3 3.15 — 0.35 x VCCIO 0.5 x VCCIO
VCCIO +
0.3 0.1 x VCCIO 0.9 x VCCIO 1.5 –0.5
2.5 V 2.375 2.5 2.625 –0.3 0.7 1.7 3.6 0.4 2 1 –1
1.8 V 1.71 1.8 1.89 –0.3 0.35 x VCCIO
0.65 x
VCCIO
VCCIO +
0.3 0.45 VCCIO – 0.45 2 –2
1.5 V 1.425 1.5 1.575 –0.3 0.35 x VCCIO
0.65 x
VCCIO
VCCIO +
0.3 0.25 x VCCIO 0.75 x VCCIO 2–2
1.2 V 1.14 1.2 1.26 –0.3 0.35 x VCCIO
0.65 x
VCCIO
VCCIO +
0.3 0.25 x VCCIO 0.75 x VCCIO 2–2
Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria V Devices—Preliminary (Part 1
of 2)
I/O Standard
VCCIO(V) VREF(V) VTT(V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2
Class I, II 2.375 2.5 2.625 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO VREF – 0.04 VREF VREF + 0.04
SSTL-18
Class I, II 1.71 1.8 1.89 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15
Class I, II 1.425 1.5 1.575 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
SSTL 135
Class I, II 1.283 1.35 1.418 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
SSTL 125
Class I, II 1.19 1.25 1.26 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO
2–12 Chapter 2: Device Datasheet for Arria V Devices
Electrical Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
HSTL-18
Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 — VCCIO/2 —
HSTL-15
Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 — VCCIO/2 —
HSTL-12
Class I, II 1.14 1.2 1.26 0.47 x VCCIO 0.5 x VCCIO 0.53 x VCCIO —V
CCIO/2 —
HSUL-12 1.14 1.2 1.3 0.49 x VCCIO 0.5 x VCCIO 0.51 x VCCIO ———
Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria V Devices—Preliminary (Part 2
of 2)
I/O Standard
VCCIO(V) VREF(V) VTT(V)
Min Typ Max Min Typ Max Min Typ Max
Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria V Devices—Preliminary (Part 1
of 2)
I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
Iol (mA) Ioh (mA)
Min Max Min Max Max Min Max Min
SSTL-2
Class I –0.3 VREF
–0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31 VREF + 0.31 VTT – 0.608 VTT + 0.608 8.1 –8.1
SSTL-2
Class II –0.3 VREF
–0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31 VREF + 0.31 VTT – 0.81 VTT + 0.81 16.2 –16.2
SSTL-18
Class I –0.3 VREF
–0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25 VREF + 0.25 VTT – 0.603 VTT + 0.603 6.7 –6.7
SSTL-18
Class II –0.3 VREF
–0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25 VREF + 0.25 0.28 VCCIO –0.28 13.4 –13.4
SSTL-15
Class I —VREF –
0.1
VREF +
0.1 —VREF –
0.175
VREF +
0.175 0.2 x VCCIO 0.8 x VCCIO 8–8
SSTL-15
Class II —VREF –
0.1
VREF +
0.1 —VREF –
0.175
VREF +
0.175 0.2 x VCCIO 0.8 x VCCIO 16 –16
SSTL 135 —VREF –
0.09
VREF +
0.09 —VREF –
0.16 VREF + 0.16 TBD (1) TBD (1) TBD (1) TBD (1)
SSTL 125 —VREF –
0.85
VREF +
0.85 —VREF –
0.15 VREF + 0.15 TBD (1) TBD (1) TBD (1) TBD (1)
HSTL-18
Class I —VREF
–0.1
VREF +
0.1 —VREF –
0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-18
Class II —VREF –
0.1
VREF +
0.1 —VREF –
0.2 VREF + 0.2 0.4 VCCIO – 0.4 16 –16
HSTL-15
Class I —VREF –
0.1
VREF +
0.1 —VREF –
0.2 VREF + 0.2 0.4 VCCIO – 0.4 8 –8
HSTL-15
Class II —VREF –
0.1
VREF +
0.1 —VREF –
0.2 VREF + 0.2 0.4 VCCIO –0.4 16 –16
HSTL-12
Class I –0.15 VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 8–8
HSTL-12
Class II –0.15 VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15 VREF + 0.15 0.25 x VCCIO 0.75 x VCCIO 16 –16
Chapter 2: Device Datasheet for Arria V Devices 2–13
Electrical Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
HSUL-12 —VREF –
0.13
VREF +
0.13 —VREF –
0.22 VREF + 0.22 0.1 x VCCIO 0.9 x VCCIO TBD (1) TBD (1)
Note to Table 2–16:
(1) Pending silicon characterization.
Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria V Devices—Preliminary (Part 2
of 2)
I/O Standard
VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V)
Iol (mA) Ioh (mA)
Min Max Min Max Max Min Max Min
Table 2–17. Differential SSTL I/O Standards for Arria V Devices—Preliminary
I/O
Standard
VCCIO (V) VSWING(DC) (V) VX(AC) (V) VSWING(AC) (V) VOX(AC) (V)
Min Typ Max Min Max Min Typ Max Min Max Min Typ Max
SSTL-2
Class I, II 2.375 2.5 2.625 0.3 VCCIO +
0.6
VCCIO/2
– 0.2 —VCCIO/2
+ 0.2 0.62 VCCIO
+ 0.6
VCCIO/2 –
0.15 —VCCIO/2 +
0.15
SSTL-18
Class I, II 1.71 1.8 1.89 0.25 VCCIO
+
0.6
VCCIO/2
– 0.175 —VCCIO/2
+ 0.175 0.5 VCCIO
+ 0.6
VCCIO/2 –
0.125 —VCCIO/2 +
0.125
SSTL-15
Class I, II 1.425 1.5 1.575 0.2 –0.2 –0.15 — 0.15 –0.35 0.35 — VCCIO/2 —
SSTL 135 1.283 1.35 1.45 0.2 –0.2 VREF
– 0.135 VCCIO/2 VREF +
0.135
TBD
(1)
TBD
(1)
VREF
–0.15 —VREF
+ 0.15
SSTL 125 1.19 1.25 1.31 TBD
(1) —TBD
(1) VCCIO/2 TBD
(1)
TBD
(1) —TBD
(1) TBD
(1) TBD (1)
Note to Table 2–17:
(1) Pending silicon characterization.
Table 2–18. Differential HSTL I/O Standards for Arria V Devices—Preliminary
I/O
Standard
VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min Max
HSTL-18
Class I, II 1.71 1.8 1.89 0.2 — 0.78 — 1.12 0.78 — 1.12 0.4 —
HSTL-15
Class I, II 1.425 1.5 1.575 0.2 — 0.68 — 0.9 0.68 — 0.9 0.4 —
HSTL-12
Class I, II 1.14 1.2 1.26 0.16 VCCIO
+ 0.3 —0.5 x
VCCIO
—0.4 x V
CCIO
0.5 x V
CCIO
0.6 x
VCCIO
0.3 VCCIO
+ 0.48
HSUL-12 1.14 1.2 1.3 0.26 0.26 0.5 x VCCIO
– 0.12
0.5 x
VCCIO
0.5 x
VCCIO
+0.12
0.4 x V
CCIO
0.5 x V
CCIO
0.6 x
VCCIO
0.44 0.44
Table 2–19. Differential I/O Standard Specifications for Arria V Devices—Preliminary (1) (Part 1 of 2)
I/O Standard
VCCIO (V) VID (mV) VICM(DC) (V) VOD (V) (2) VOCM (V) (2)
Min Typ Max Min Condition Max Min Max Min Typ Max Min Typ Max
PCML (3)
2–14 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.
1You typically use the interactive Excel-based EPE before designing the FPGA to get a
magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer
provides better quality estimates based on the specifics of the design after you
complete place-and-route. The PowerPlay Power Analyzer can apply a combination
of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yields very accurate power estimates.
fFor more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Arria V core and periphery
blocks for commercial grade devices.
These characteristics can be designated as Preliminary or Final.
■Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
■Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no preliminary
designations on finalized tables.
2.5 V LVDS 2.375 2.5 2.625 100 VCM =
1.25 V
— 0.05 1.8 0.247 — 0.6 1.125 1.25 1.375
— 1.05 1.55 0.247 — 0.6 1.125 1.25 1.375
RSDS (HIO) 2.375 2.5 2.625 100 VCM =
1.25 V — 0.3 1.4 0.1 0.2 0.6 0.5 1.2 1.4
Mini-LVDS
(HIO) 2.375 2.5 2.625 200 — 600 0.4 1.325 0.25 — 0.6 1 1.2 1.4
LVPECL 2.375 2.5 2.625 300 — — 0.6 1.8 — — — — — —
Notes to Table 2–19:
(1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 2–15.
(2) RL range: 90 RL 110 .
(3) Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and
reference clock I/O pin specifications, refer to Table 2–20 and Table 2–21.
Table 2–19. Differential I/O Standard Specifications for Arria V Devices—Preliminary (1) (Part 2 of 2)
I/O Standard
VCCIO (V) VID (mV) VICM(DC) (V) VOD (V) (2) VOCM (V) (2)
Min Typ Max Min Condition Max Min Max Min Typ Max Min Typ Max
Chapter 2: Device Datasheet for Arria V Devices 2–15
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 2–20 and Table 2–21 list the Arria V transceiver specifications.
Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary (1) (Part 1 of 3)
Symbol/
Description Conditions
–4
Commercial
Speed Grade
–5
Commercial/Industrial
Speed Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards 1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2), HCSL, and LVDS
Input frequency from
REFCLK
input pins — 27 — 710 27 — 710 27 — 710 MHz
Duty cycle — 45 — 55 45 — 55 45 — 55 %
Peak-to-peak
differential input voltage — 200 — 2000 200 — 2000 200 — 2000 mV
Spread-spectrum
modulating clock
frequency
PCI Express®
(PCIe®)30 — 33 30 — 33 30 — 33 kHz
Spread-spectrum
downspread PCIe — 0 to
–0.5% ——
0 to
–0.5% ——
0 to
–0.5% ——
On-chip termination
resistors — — 100 — — 100 — — 100 —
VICM (AC coupled) — 1.1 (3) 1.1 (3) 1.1 (3) V
VICM (DC coupled)
HCSL I/O
standard for the
PCIe reference
clock
250 — 550 250 — 550 250 — 550 mV
RREF ——
2000
±1% ——
2000
±1% ——
2000
±1% —
Transceiver Clocks
fixedclk
clock
frequency
PCIe
Receiver Detect — 125 — — 125 — — 125 — MHz
Avalon®-Memory-
Mapped (Avalon-MM)
PHY management clock
frequency
< 150 MHz
2–16 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Receiver
Supported I/O
Standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate — 611 — 6553 611 — 6553 611 — 3125 Mbps
Absolute VMAX for a
receiver pin (4) — — — 1.2 — — 1.2 — — 1.2 V
Absolute VMIN for a
receiver pin — –0.4 — — –0.4 — — –0.4 — — V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before
device configuration
— — — 1.6 — — 1.6 — — 1.6 V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after
device configuration
— — — 2.2 — — 2.2 — — 2.2 V
Minimum differential
eye opening at the
receiver serial input
pins (5)
—85——85——85——mV
Differential on-chip
termination resistors
85- setting — 85 — — 85 — — 85 —
100- setting — 100 — — 100 — — 100 —
120- setting — 120 — — 120 — — 120 —
150- setting — 150 — — 150 — — 150 —
Differential and
common mode return
loss
PCIe (Gen1 and
Gen2), GIGE,
XAUI, SDI,
CPRI, OBSAI
Compliant —
Programmable ppm
detector (6) — ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
Run Length — — — 200 — — 200 — — 200 UI
Programmable
equalization ———4——4——4dB
Programmable DC gain
DC Gain Setting
= 0 —0 ——0 ——0 —dB
DC Gain Setting
= 1 —3 ——3 ——3 —dB
Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary (1) (Part 2 of 3)
Symbol/
Description Conditions
–4
Commercial
Speed Grade
–5
Commercial/Industrial
Speed Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Chapter 2: Device Datasheet for Arria V Devices 2–17
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Transmitter
Supported I/O
Standards 1.5 V PCML
Data rate — 611 — 6553 611 — 6553 611 — 3125
Mbps
VOCM — — 650 — — 650 — — 650 — mV
Differential on-chip
termination resistors
85- setting — 85 — — 85 — — 85 —
100- setting — 100 — — 100 — — 100 —
120- setting — 120 — — 120 — — 120 —
150- setting — 150 — — 150 — — 150 —
Rise time (7) — 30 — 160 30 — 160 30 — 160 ps
Fall time (7) — 30 — 160 30 — 160 30 — 160 ps
CMU PLL
Supported data range — 611 — 6553 611 — 6553 611 — 3125 Mbps
Transceiver-FPGA Fabric Interface
Interface speed
(single-width mode) — 25 — 187.50 25 — 163.84 25 — 156.25 MHz
Interface speed
(double-width mode) — 25 — 163.84 25 — 163.84 25 — 156.25 MHz
Notes to Table 2–20:
(1) Speed grades shown in Table 2–20 refer to the Transceiver Speed Grade in the device ordering code. For more information about device ordering codes, refer
to the Overview for Arria V Device Family chapter.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(6) The rate match FIFO supports only up to ±300 parts per million (ppm).
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Table 2–20. Transceiver Specifications for Arria V GX Devices—Preliminary (1) (Part 3 of 3)
Symbol/
Description Conditions
–4
Commercial
Speed Grade
–5
Commercial/Industrial
Speed Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
2–18 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary (1) (Part 1 of 2)
Symbol/
Description Conditions
–5
Industrial
Speed Grade Unit
Min Typ Max
Reference Clock
Supported I/O Standards 1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2),
HCSL, and LVDS
Input frequency from
REFCLK
input pins — 27 — 710 MHz
Duty cycle — 45 — 55 %
Peak-to-peak differential input voltage — 200 — 2000 mV
Spread-spectrum modulating clock
frequency PCI Express® (PCIe®) 30 — 33 kHz
Spread-spectrum downspread PCIe — 0 to
–0.5% ——
On-chip termination resistors — — 100 —
VICM (AC coupled) — 1.1 (3) V
VICM (DC coupled) HCSL I/O standard for
the PCIe reference clock 250 — 550 mV
RREF — — 2000 ±1% —
Transceiver Clocks
fixedclk
clock frequency PCIe
Receiver Detect — 125 — MHz
Avalon-MM PHY management clock
frequency < 150 MHz
Receiver
Supported I/O Standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate (6-Gbps Transceiver) — 611 — 6375 Mbps
Data rate (10-Gbps transceiver) — 6.376 9.8304 10.3125 Gbps
Absolute VMAX for a receiver pin (4) ———1.2V
Absolute VMIN for a receiver pin — –0.4 — — V
Maximum peak-to-peak differential input
voltage VID (diff p-p) before device
configuration
———1.6V
Maximum peak-to-peak differential input
voltage VID (diff p-p) after device
configuration
———2.2V
Minimum differential eye opening at the
receiver serial input pins (5) —85——mV
Differential on-chip termination resistors
85- setting 85
100- setting 100
120- setting 120
150- setting 150
Chapter 2: Device Datasheet for Arria V Devices 2–19
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Differential and common mode return loss
PCIe (Gen1 and Gen2),
GIGE, XAUI, SDI, CPRI,
OBSAI, SFI
Compliant —
Programmable ppm detector (6) —±62.5, 100, 125, 200, 250, 300, 500,
and 1000 ppm
Run Length — — — 200 UI
Programmable equalization — — — 4 dB
Programmable DC gain DC Gain Setting = 0 — 0 — dB
DC Gain Setting = 1 — 3 — dB
Transmitter
Supported I/O Standards 1.5 V PCML
Data rate (6-Gbps transceiver) — 611 — 6375 Mbps
Data rate (10-Gbps transceiver) — 6.376 9.8304 10.3125 Gbps
VOCM — — 650 — mV
Differential on-chip termination resistors
85- setting — 85 —
100- setting — 100 —
120- setting — 120 —
150- setting — 150 —
Rise time (7) — 30 — 160 ps
Fall time (7) — 30 — 160 ps
CMU PLL
Supported data range — 0.611 — 10.3125 Gbps
Transceiver-FPGA Fabric Interface
Interface speed (80-bit mode) — 25 — 159.375 MHz
Interface speed
(single-width mode) — 25 — 156.25 MHz
Interface speed (double-width mode) — 25 — 159.375 MHz
Notes to Table 2–21:
(1) Speed grades shown in Table 2–21 refer to the Transceiver Speed Grade in the device ordering code. For more information about device
ordering codes, refer to the Overview for Arria V Device Family chapter.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you
enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(6) The rate match FIFO supports only up to ±300 ppm.
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary (1) (Part 2 of 2)
Symbol/
Description Conditions
–5
Industrial
Speed Grade Unit
Min Typ Max
2–20 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–22 and Table 2–23 list the transceiver block jitter specification for Arria V
devices.
Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 1 of 4)
Symbol/
Description Conditions
–4
Commercial Speed
Grade
–5
Commercial/
Industrial Speed
Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
CPRI Transmit Jitter Generation (1)
Total Jitter
E.6.HV, E.12.HV
Pattern = CJPAT — — 0.279 — — 0.279 — — 0.279 UI
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
— — 0.35 — — 0.35 — — 0.35 UI
Deterministic
Jitter
E.6.HV, E.12.HV
Pattern = CJPAT — — 0.14 — — 0.14 — — 0.14 UI
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
— — 0.17 — — 0.17 — — 0.17 UI
CPRI Receiver Jitter Tolerance (1)
Total jitter
tolerance
E.6.HV, E.12.HV
Pattern = CJPAT > 0.66 > 0.66 > 0.66 UI
Deterministic
jitter tolerance
E.6.HV, E.12.HV
Pattern = CJPAT > 0.4 > 0.4 > 0.4 UI
Total jitter
tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.65 > 0.65 > 0.65 UI
Deterministic
jitter tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.37 > 0.37 > 0.37 UI
Combined
deterministic
and random
jitter tolerance
E.6.LV, E.12.LV, E.24.LV,
E.30.LV
Pattern = CJTPAT
> 0.55 > 0.55 > 0.55 UI
OBSAI Transmit Jitter Generation (2)
Total jitter at
768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6 MHz
Pattern = CJPAT — — 0.35 — — 0.35 — — 0.35 UI
Deterministic
jitter at
768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6 MHz
Pattern = CJPAT — — 0.17 — — 0.17 — — 0.17 UI
Chapter 2: Device Datasheet for Arria V Devices 2–21
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
OBSAI Receiver Jitter Tolerance (2)
Deterministic
jitter tolerance
at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT > 0.37 > 0.37 > 0.37 UI
Combined
deterministic
and random
jitter tolerance
at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT > 0.55 > 0.55 > 0.55 UI
Sinusoidal Jitter
tolerance at
768 Mbps
Jitter Frequency =
5.4 KHz
Pattern = CJPAT
> 8.5 > 8.5 > 8.5 UI
Jitter Frequency =
460 MHz to 20 MHz
Pattern = CJPAT
> 0.1 > 0.1 > 0.1 UI
Sinusoidal Jitter
tolerance at
1536 Mbps
Jitter Frequency =
10.9 KHz
Pattern = CJPAT
> 8.5 > 8.5 > 8.5 UI
Jitter Frequency =
921.6 MHz to 20 MHz
Pattern = CJPAT
> 0.1 > 0.1 > 0.1 UI
Sinusoidal Jitter
tolerance at
3072 Mbps
Jitter Frequency =
21.8 KHz
Pattern = CJPAT
> 8.5 > 8.5 > 8.5 UI
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
> 0.1 > 0.1 > 0.1 UI
Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 2 of 4)
Symbol/
Description Conditions
–4
Commercial Speed
Grade
–5
Commercial/
Industrial Speed
Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
2–22 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Serial RapidIO® (SRIO) Transmit Jitter Generation (3)
Deterministic
jitter
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
— — 0.17 — — 0.17 — — 0.17 UI
Total jitter
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
— — 0.35 — — 0.35 — — 0.35 UI
SRIO Receiver Jitter Tolerance (3)
Deterministic
jitter tolerance
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.37 > 0.37 > 0.37 UI
Combined
deterministic
and random
jitter tolerance
(peak-to-peak)
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.55 > 0.55 > 0.55 UI
Sinusoidal jitter
tolerance
(peak-to-peak)
Jitter Frequency =
22.1 KHz Data Rate =
1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 8.5 > 8.5 > 8.5 UI
Jitter Frequency =
1.875 MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.1 > 0.1 > 0.1 UI
Jitter Frequency =
20 MHz
Data Rate = 1.25, 2.5,
3.125 Gbps
Pattern = CJPAT
> 0.1 > 0.1 > 0.1 UI
GIGE Transmit Jitter Generation (4)
Deterministic
jitter
(peak-to-peak)
Pattern = CRPAT — — 0.14 — — 0.14 — — 0.14 UI
Total jitter
(peak-to-peak) Pattern = CRPAT — — 0.279 — — 0.279 — — 0.279 UI
Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 3 of 4)
Symbol/
Description Conditions
–4
Commercial Speed
Grade
–5
Commercial/
Industrial Speed
Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Chapter 2: Device Datasheet for Arria V Devices 2–23
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
GIGE Receiver Jitter Tolerance (4)
Deterministic
jitter tolerance
(peak-to-peak)
Pattern = CJPAT > 0.4 > 0.4 > 0.4 UI
Combined
deterministic
and random
jitter tolerance
(peak-to-peak)
Pattern = CJPAT > 0.66 > 0.66 > 0.66 UI
HiGig Transmit Jitter Generation (5)
Deterministic
jitter
(peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT — — 0.17 — — — — — — UI
Total jitter
(peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT — — 0.35 — — — — — — UI
Notes to Table 2–22:
(1) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(2) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
(3) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(5) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
Table 2–22. Transceiver Block Jitter Specification for Arria V GX Devices—Preliminary (Part 4 of 4)
Symbol/
Description Conditions
–4
Commercial Speed
Grade
–5
Commercial/
Industrial Speed
Grade
–6
Commercial Speed
Grade Unit
Min Typ Max Min Typ Max Min Typ Max
2–24 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 1 of 3)
Symbol/
Description Conditions
–5
Industrial Speed Grade Unit
Min Typ Max
SFI Transmit Jitter Generation (1)
Deterministic Jitter Data Rate = 9.8304, 10.3125 Gbps
Pattern = PRBS31
— — 0.1 UI
Total Jitter — — 0.28 UI
SFI Receive Jitter Tolerance (1)
99% Jitter Tolerance Data Rate = 9.8304, 10.3125 Gbps
Pattern = PRBS31
>0.42 UI
Total Jitter >0.70 UI
CPRI Transmit Jitter Generation (2)
Total Jitter
E.6.HV, E.12.HV
Pattern = CJPAT ——0.279—
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJTPAT — — 0.35 —
Deterministic Jitter
E.6.HV, E.12.HV
Pattern = CJPAT — — 0.14 —
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJTPAT — — 0.17 —
CPRI Receive Jitter Generation (2)
Total jitter tolerance E.6.HV, E.12.HV
Pattern = CJPAT > 0.66 > 0.66
Deterministic jitter
tolerance
E.6.HV, E.12.HV
Pattern = CJPAT > 0.4 > 0.4
Total jitter tolerance E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJTPAT > 0.65 > 0.65
Deterministic jitter
tolerance
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJTPAT > 0.37 > 0.37
Combined deterministic
and random jitter tolerance
E.6.LV, E.12.LV, E.24.LV, E.30.LV
Pattern = CJTPAT > 0.55 > 0.55
OBSAI Transmit Jitter Generation (3)
Total jitter at 768 Mbps,
1536 Mbps, and
3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT — — 0.35 —
Deterministic jitter at
768 Mbps, 1536 Mbps,
and 3072 Mbps
REFCLK = 153.6MHz
Pattern = CJPAT — — 0.17 —
Chapter 2: Device Datasheet for Arria V Devices 2–25
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
OBSAI Receiver Jitter Tolerance (3)
Deterministic jitter
tolerance at 768 Mbps,
1536 Mbps, and
3072 Mbps
Pattern = CJPAT > 0.37 > 0.37
Combined deterministic
and random jitter tolerance
at 768 Mbps, 1536 Mbps,
and 3072 Mbps
Pattern = CJPAT > 0.55 > 0.55
Sinusoidal Jitter tolerance
at 768 Mbps
Jitter Frequency = 5.4 KHz
Pattern = CJPAT > 8.5 > 8.5
Jitter Frequency = 460 MHz to 20 MHz
Pattern = CJPAT > 0.1 > 0.1
Sinusoidal Jitter tolerance
at 1536 Mbps
Jitter Frequency = 10.9 KHz
Pattern = CJPAT > 8.5 > 8.5
Jitter Frequency = 921.6 MHz to 20 MHz
Pattern = CJPAT > 0.1 > 0.1
Sinusoidal Jitter tolerance
at 3072 Mbps
Jitter Frequency = 21.8 KHz
Pattern = CJPAT > 8.5 > 8.5
Jitter Frequency = 1843.2 MHz to
20 MHz
Pattern = CJPAT
> 0.1 > 0.1
SRIO Transmit Jitter Generation (4)
Deterministic jitter
(peak-to-peak)
Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT — — 0.17 UI
Total jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT — — 0.35 UI
Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 2 of 3)
Symbol/
Description Conditions
–5
Industrial Speed Grade Unit
Min Typ Max
2–26 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
SRIO Receiver Jitter Tolerance (4)
Deterministic jitter
tolerance (peak-to-peak)
Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT > 0.37 UI
Combined deterministic
and random jitter tolerance
(peak-to-peak)
Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT > 0.55 UI
Sinusoidal jitter tolerance
(peak-to-peak)
Jitter Frequency = 22.1 KHz Data Rate =
1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 8.5 UI
Jitter Frequency = 1.875 MHz
Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.1 UI
Jitter Frequency = 20 MHz
Data Rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.1 UI
GIGE Transmit Jitter Generation (5)
Deterministic jitter
(peak-to-peak) Pattern = CRPAT — — 0.14 UI
Total jitter (peak-to-peak) Pattern = CRPAT — — 0.279 UI
GIGE Receiver Jitter Tolerance (5)
Deterministic jitter
tolerance (peak-to-peak) Pattern = CJPAT > 0.4 UI
Combined deterministic
and random jitter tolerance
(peak-to-peak)
Pattern = CJPAT > 0.66 UI
HiGig Transmit Jitter Generation (6)
Deterministic jitter
(peak-to-peak)
Data Rate = 3.75 Gbps
Pattern = CJPAT — — 0.17 UI
Total jitter (peak-to-peak) Data Rate = 3.75 Gbps
Pattern = CJPAT — — 0.35 UI
Notes to Table 2–23:
(1) The jitter numbers for SFI are compliant to SFF-8431 Specification.
(2) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(3) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
(4) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(5) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(6) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
Table 2–23. Transceiver Block Jitter Specification for Arria V GT Devices—Preliminary (Part 3 of 3)
Symbol/
Description Conditions
–5
Industrial Speed Grade Unit
Min Typ Max
Chapter 2: Device Datasheet for Arria V Devices 2–27
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks and temperature sensing diode specifications.
Clock Tree Specifications
Table 2–24 lists the clock tree specifications for Arria V devices.
PLL Specifications
Table 2–25 lists the Arria V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 2–24. Clock Tree Performance for Arria V Devices—Preliminary
Performance
Unit
Symbol –C4 Speed Grade –C5, I5 Speed Grade –C6 Speed Grade
Global clock and Regional clock 625 625 525 MHz
Peripheral clock 450 400 350 MHz
Table 2–25. PLL Specifications for Arria V Devices—Preliminary (1) (Part 1 of 3)
Symbol Parameter Min Typ Max Unit
fIN
Input clock frequency (–4 speed grade) 5 — 670 (2) MHz
Input clock frequency (–5 speed grade) 5 — 622 (2) MHz
Input clock frequency (–6 speed grade) 5 — 500 (2) MHz
fINPFD Integer input clock frequency to the PFD 5 — 325 MHz
fFINPFD Fractional input clock frequency to the PFD 50 — TBD (1) MHz
fVCO
PLL VCO operating range (–4 speed grade) 600 — 1600 MHz
PLL VCO operating range (–5 speed grade) 600 — 1400 MHz
PLL VCO operating range (–6 speed grade) 600 — 1300 MHz
tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 %
fOUT
Output frequency for internal global or regional clock
(–4 speed grade) — — 500 (3) MHz
Output frequency for internal global or regional clock
(–5 speed grade) — — 500 (3) MHz
Output frequency for internal global or regional clock
(–6 speed grade) — — 400 (3) MHz
fOUT_EXT
Output frequency for external clock output (–4 speed grade) — — 670 (3) MHz
Output frequency for external clock output (–5 speed grade) — — 622 (3) MHz
Output frequency for external clock output (–6 speed grade) — — 500 (3) MHz
tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 %
tFCOMP External feedback clock compensation time — — 10 ns
tCONFIGPHASE Time required to reconfigure phase shift — — TBD (1) —
tDYCONFIGCLK Dynamic Configuration Clock — — 100 MHz
2–28 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
tLOCK
Time required to lock from end-of-device configuration or
deassertion of
areset
—— 1 ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays) —— 1 ms
fCLBW
PLL closed-loop low bandwidth — 0.3 — MHz
PLL closed-loop medium bandwidth — 1.5 — MHz
PLL closed-loop high bandwidth (8) —4 —MHz
tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps
tARESET Minimum pulse width on the
areset
signal 10 — — ns
tINCCJ (4), (5) Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz) — — 0.15 UI (p-p)
Input clock cycle-to-cycle jitter (FREF < 100 MHz) — — +750 ps (p-p)
tOUTPJ_DC (6) Period jitter for dedicated clock output (FOUT ≥ 100 MHz) — — TBD (1) ps (p-p)
Period jitter for dedicated clock output (FOUT < 100 MHz) — — TBD (1) mUI (p-p)
tOUTCCJ_DC (6)
Cycle-to-cycle jitter for dedicated clock output
(FOUT ≥100 MHz) ——TBD
(1) ps (p-p)
Cycle-to-cycle jitter for dedicated clock output
(FOUT < 100 MHz) ——TBD
(1) mUI (p-p)
tOUTPJ_IO (6),
(9)
Period Jitter for clock output on the regular I/O
(FOUT ≥100 MHz) ——TBD
(1) ps (p-p)
Period Jitter for clock output on the regular I/O
(FOUT < 100 MHz) ——TBD
(1) mUI (p-p)
tOUTCCJ_IO (6),
(9)
Cycle-to-cycle jitter for clock output on the regular I/O
(FOUT ≥100 MHz) ——TBD
(1) ps (p-p)
Cycle-to-cycle jitter for clock output on the regular I/O
(FOUT < 100 MHz) ——TBD
(1) mUI (p-p)
tOUTPJ_DC_F Period jitter for dedicated clock output in fractional mode — — TBD (1) —
tOUTCCJ_DC_F
Cycle-to-cycle jitter for dedicated clock output in fractional
mode — — TBD (1) —
tOUTPJ_IO_F
Period Jitter for clock output on the regular I/O in fractional
mode — — TBD (1) —
tOUTCCJ_IO_F
Cycle-to-cycle jitter for clock output on the regular I/O in
fractional mode — — TBD (1) —
tCASC_OUTPJ_DC
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100 MHz) ——TBD
(1) ps (p-p)
Period jitter for dedicated clock output in cascaded PLLs
(FOUT < 100 MHz) ——TBD
(1) mUI (p-p)
tDRIFT
Frequency drift after PFDENA is disabled for a duration of
100 µs — — ±10 %
Table 2–25. PLL Specifications for Arria V Devices—Preliminary (1) (Part 2 of 3)
Symbol Parameter Min Typ Max Unit
Chapter 2: Device Datasheet for Arria V Devices 2–29
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
DSP Block Specifications
Table 2–26 lists the Arria V DSP block performance specifications.
dKBIT Bit number of Delta Sigma Modulator (DSM) — 24 — bits
kVALUE Numerator of Fraction TBD (1) 8388608 TBD (1) —
fRES Resolution of VCO frequency (fINPFD =100 MHz) — 5.96 — Hz
Notes to Table 2–25:
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404 % confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 2–33 on page 2–35.
(7) The cascaded PLL specification is only applicable with the following conditions:
a. Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which are available in Table 2–33 on page 2–35.
Table 2–25. PLL Specifications for Arria V Devices—Preliminary (1) (Part 3 of 3)
Symbol Parameter Min Typ Max Unit
Table 2–26. DSP Block Performance Specifications for Arria V Devices—Preliminary
Mode
Performance
Unit
–C4
Speed
Grade
–C5, I5
Speed
Grade
–C6
Speed
Grade
Modes using One DSP Block
Independent 9 x 9 Multiplication 370 310 220 MHz
Independent 18 x 19 Multiplication 370 310 220 MHz
Independent 18 x 18 Multiplication 370 310 220 MHz
Independent 27 x 27 Multiplication 310 250 200 MHz
Independent 18 x 25 Multiplication 370 310 220 MHz
Independent 20 x 24 Multiplication 370 310 220 MHz
Two 18 x 19 Multiplier Adder Mode 370 310 220 MHz
18 x 18 Multiplier Added Summed with 36-bit Input 370 310 220 MHz
Modes using Two DSP Blocks
Complex 18 x 19 multiplication 370 310 220 MHz
Two 27 x 27 Multiplier Adder 310 250 200 MHz
Four 18 x 19 Multiplier Adder 370 310 220 MHz
2–30 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Memory Block Specifications
Table 2–27 lists the Arria V memory block specifications.
Temperature Sensing Diode Specifications
Table 2–28 lists the specifications for the Arria V internal temperature sensing diode.
Table 2–27. Memory Block Performance Specifications for Arria V Devices—Preliminary (1),(2)
Memory Mode
Resources Used Performance
Unit
ALUTs Memory C4
Speed Grade
C5,I5
Speed Grade
C6
Speed Grade
MLAB
Single port, all supported widths 0 1 500 450 400 MHz
Simple dual-port, all supported
widths 0 1 500 450 400 MHz
Simple dual-port with read and
write at the same address 0 1 400 350 300 MHz
ROM, all supported width — — 500 450 400 MHz
M10K
Block
Single-port, all supported widths 0 1 400 350 285 MHz
Simple dual-port, all supported
widths 0 1 400 350 285 MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
0 1 315 275 240 MHz
True dual port, all supported
widths 0 1 400 350 285 MHz
ROM, all supported widths 0 1 400 350 285 MHz
Min Pulse Width (clock high time) — — 1,275 1,360 1,445 ps
Min Pulse Width (clock low time) — — 850 1,060 1,175 ps
Notes to Table 2–27:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Table 2–28. Internal Temperature Sensing Diode Specifications for Arria V Devices—Preliminary
Temperature
Range Accuracy
Offset
Calibrated
Option
Sampling Rate Conversion
Time Resolution Minimum Resolution with no
Missing Codes
–40 to 100°C ±8°C No Frequency:
1MHz < 100 ms 8 bits 8 bits
Chapter 2: Device Datasheet for Arria V Devices 2–31
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. GPIO
standards such as 3.3-, 2.5-, 1.8-, and 1.5-V LV T T L / LV C M OS are capable of a typical
167 MHz and 1.2 LV C M O S at 100 MHz interfacing frequency with a 10 pF load.
1Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 2–29 lists high-speed I/O timing for Arria V devices.
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 1 of 3)
Symbol Conditions
–4 Speed Grade –5 Speed Grade –6 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK_in (input
clock
frequency)
True
Differential
I/O Standards
Clock boost factor W = 1 to 40 (5) 5 — 625 5 — 625 5 — TBD MHz
fHSCLK_in (input
clock
frequency)
Single Ended
I/O Standards
(4)
Clock boost factor W = 1 to 40 (5) 5 — 625 5 — 625 5 — TBD MHz
fHSCLK_in (input
clock
frequency)
Single Ended
I/O Standards
(3)
Clock boost factor W = 1 to 40 (5) 5— TBD 5— TBD 5—TBDMHz
fHSCLK_OUT
(output clock
frequency)
—5—625
(6) 5 — 625 (6) 5—TBD
(6) MHz
2–32 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Transmitter
True
Differential
I/O Standards
- fHSDR (data
rate)
SERDES factor J = 3 to 10 (7) — 1250 (7) —1250 (7) — 1050 Mbps
SERDES factor J = 1 to 2, Uses
DDR Registers
(7) —(7) (7) —(7) (7) —(7) Mbps
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Networks -
fHSDR (data
rate) (8)
SERDES factor J = 4 to 10 (7) —TBD (7) —TBD (7) —TBDMbps
tx Jitter - True
Differential
I/O Standards
Total Jitter for Data Rate,
600 Mbps - 1.25 Gbps — — 160 — — 160 — — 160 ps
Total Jitter for Data Rate,
< 600 Mbps — — 0.1 — — 0.1 — — 0.1 UI
tx Jitter -
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Network
Total Jitter for Data Rate,
600 Mbps – 1.25 Gbps — — TBD — — TBD — — TBD ps
Total Jitter for Data Rate
< 600 Mbps — — TBD — — TBD — — TBD UI
tDUTY
TX output clock duty cycle for both
True and Emulated Differential I/O
Standards
45 50 55 45 50 55 45 50 55 %
tRISE & tFALL
True Differential I/O Standards — — 200 — — 200 — — 200 ps
Emulated Differential I/O
Standards with Three External
Output Resistor Networks
— — 250 — — 250 — — 300 ps
TCCS
True Differential I/O Standards — — 150 — — 150 — — 150 ps
Emulated Differential I/O
Standards — — 300 — — 300 — — 300 ps
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 2 of 3)
Symbol Conditions
–4 Speed Grade –5 Speed Grade –6 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Chapter 2: Device Datasheet for Arria V Devices 2–33
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Figure 2–1 shows the DPA lock time specifications with the DPA PLL calibration
option enabled.
Receiver
True
Differential
I/O Standards
- fHSDRDPA
(data rate)
SERDES factor J = 3 to 10 — — 1250 — — 1250 — — 1050 Mbps
fHSDR (data
rate)
SERDES factor J = 3 to 10 (7) —(9) (7) —(9) (7) —(9) Mbps
SERDES factor J = 1 to 2, Uses
DDR Registers
(7) —(7) (7) —(7) (7) —(7) Mbps
DPA Mode
DPA run
length — — — 10000 — — 10000 — — 10000 UI
Soft CDR mode
Soft-CDR
ppm tolerance — — — 300 — — 300 — — 300 ±
ppm
Non DPA Mode
Sampling
Window — — — 300 — — 300 — — 300 ps
Notes to Table 2–29:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This applies to LVDS source synchronous mode only.
(4) This applies to DPA and soft-CDR modes only.
(5) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(6) This is achieved by using the LVDS clock network.
(7) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that
you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(8) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(9) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin,
transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary (1), (2), (3) (Part 3 of 3)
Symbol Conditions
–4 Speed Grade –5 Speed Grade –6 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Figure 2–1. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 data
transitions 96 slow
clock cycles 256 data
transitions 256 data
transitions
96 slow
clock cycles
2–34 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–30 lists the DPA lock time specifications for Arria V devices.
Figure 2–2 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate equal to 1.25 Gbps.
Table 2–31 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to 1.25 Gbps.
Table 2–30. DPA Lock Time Specifications for Arria V Devices—Preliminary (1), (2), (3)
Standard Training Pattern
Number of Data
Transitions in One
Repetition of the
Training Pattern
Number of
Repetitions per 256
Data Transitions (4)
Maximum
SPI-4 00000000001111111111 2 128 640 data transitions
Parallel Rapid I/O 00001111 2 128 640 data transitions
10010000 4 64 640 data transitions
Miscellaneous 10101010 8 32 640 data transitions
01010101 8 32 640 data transitions
Notes to Table 2–30:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grades.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 2–2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
F1 F2 F3 F4
Jitter Frequency (Hz)
Jitter Amphlitude (UI)
0.1
0.35
8.5
25
Table 2–31. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps—Preliminary
Jitter Frequency (Hz) Sinusoidal Jitter (UI)
F1 10,000 25.000
F2 17,565 25.000
F3 1,493,000 0.350
F4 50,000,000 0.350
Chapter 2: Device Datasheet for Arria V Devices 2–35
Switching Characteristics
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Figure 2–3 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
DQS Logic Block and Memory Output Clock Jitter Specifications
Table 2–32 lists the DQS phase shift error for Arria V devices.
Table 2–33 lists the memory output clock jitter specifications for Arria V devices.
Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
0.1 UI P-P
baud/1667 20 MHz
Frequency
Sinusoidal Jitter Amplitude
20db/dec
Table 2–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V
Devices—Preliminary (1),(2)
Number of DQS Delay
Buffer
–C4
Speed Grade
–C5, I5
Speed Grade
–C6
Speed Grade Unit
2575874ps
Notes to Table 2–32:
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers
in a –4 speed grade is 58 ps or ±29 ps.
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary (1) (Part 1 of 2)
Parameter Clock
Network Symbol
–4
Speed Grade
–5
Speed Grade
–6
Speed Grade Unit
Min Max Min Max Min Max
Clock period jitter Regional tJIT(per) –50 50 –55 55 –55 55 ps
Cycle-to-cycle period jitter Regional tJIT(cc) –100 100 –110 110 –110 110 ps
Duty cycle jitter Regional tJIT(duty) –50 50 –82.5 82.5 –82.5 82.5 ps
Clock period jitter Global tJIT(per) –75 75 –82.5 82.5 –82.5 82.5 ps
Cycle-to-cycle period jitter Global tJIT(cc) –150 150 –165 165 –165 165 ps
2–36 Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
OCT Calibration Block Specifications
Table 2–34 lists the OCT calibration block specifications for Arria V devices.
Figure 2–4 shows the TRS_RT for
dyn_term_ctrl
and
oe
signals.
Duty Cycle Distortion (DCD) Specifications
Table 2–35 lists the worst-case DCD for Arria V devices.
Duty cycle jitter Global tJIT(duty) –75 75 –90 90 –90 90 ps
Note to Table 2–33:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary (1) (Part 2 of 2)
Parameter Clock
Network Symbol
–4
Speed Grade
–5
Speed Grade
–6
Speed Grade Unit
Min Max Min Max Min Max
Table 2–34. OCT Calibration Block Specifications for Arria V Devices—Preliminary
Symbol Description Min Typ Max Unit
OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration — 1000 — Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out — 32 — Cycles
TRS_RT
Time required between the
dyn_term_ctrl
and
oe
signal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
—2.5— ns
Figure 2–4. Timing Diagram for dyn_term_ctrl and oe Signals
Table 2–35. Worst-Case DCD on Arria V I/O Pins—Preliminary
Symbol
–C4 Speed Grade –C5,I5 Speed
Grade
–C6 Speed
Grade Unit
Min Max Min Max Min Max
Output Duty Cycle 45 55 45 55 45 55 %
T
RS_RT
T
RS_RT
dyn_term_ctrl
oe
Tristate
RX RX
Tristate
Chapter 2: Device Datasheet for Arria V Devices 2–37
Configuration Specification
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Configuration Specification
This section provides configuration specifications and timing for Arria V devices.
These characteristics can be designated as Preliminary or Final.
■Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
■Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
POR Specifications
Table 2–36 lists the specifications for fast and standard POR for Arria V devices.
JTAG Configuration Timing
Table 2–37 lists the JTAG timing parameters and values for Arria V devices.
Table 2–36. Fast and Standard POR Delay Specification for Arria V Devices (1)
POR Delay Minimum (ms) Maximum (ms)
Fast (2) 412
Standard (3) 100 300
Notes to Table 2–36:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices”
table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.
(2) When the
PORSEL
signal is high, the device is in fast POR delay.
(3) When the
PORSEL
signal is low, the device is in standard POR delay.
Table 2–37. JTAG Timing Parameters and Values for Arria V Devices—Preliminary
Symbol Description Min Max Unit
tJCP TCK clock period 30 — ns
tJCH TCK clock high time 14 — ns
tJCL TCK clock low time 14 — ns
tJPSU (TDI) TDI JTAG port setup time 1 — ns
tJPSU (TMS) TMS JTAG port setup time 3 — ns
tJPH JTAG port hold time 5 — ns
tJPCO JTAG port clock to output — 11 (1) ns
tJPZX JTAG port high impedance to valid output — 14 (1) ns
tJPXZ JTAG port valid output to high impedance — 14 (1) ns
Note to Table 2–37:
(1) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
2–38 Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Arria V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different
DCLK
-to-
DATA[]
ratio when you turn on
encryption or the compression feature.
Table 2–38 lists the
DCLK
-to-
DATA[]
ratio for each combination.
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 2–5 shows the timing waveform for a FPP configuration when using a MAX®II
device as an external host. This timing waveform shows timing when the
DCLK
-to-
DATA[]
ratio is 1.
1When you enable decompression or the design security feature, the
DCLK
-to-
DATA[]
ratio varies for FPP x8 and FPP x16. For the respective
DCLK
-to-
DATA[]
ratio, refer to
Table 2–38.
Table 2–38. DCLK-to-DATA[] Ratio for Arria V Devices (1)
Configuration Scheme Encryption Compression DCLK-to-DATA[] ratio (r)
FPP (8-bit wide)
Off Off 1
On Off 1
Off On 2
On On 2
FPP (16-bit wide)
Off Off 1
On Off 2
Off On 4
On On 4
Note to Table 2–38:
(1) Depending on the
DCLK
-to-
DATA[]
ratio, the host must send a
DCLK
frequency that is r times the
DATA[]
rate in
byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the
DCLK
frequency
must be 2 times the
DATA[]
rate in Wps.
Chapter 2: Device Datasheet for Arria V Devices 2–39
Configuration Specification
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Figure 2–5. DCLK-to-DATA[] FPP Configuration Timing Waveform When the Ratio is 1 (1)
Notes to Figure 2–5:
(1) The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG
,
nSTATUS
, and
CONF_DONE
are at logic-high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds
nSTATUS
low for the time of the POR delay.
(3) After power up, before and during configuration,
CONF_DONE
is low.
(4) Do not leave
DCLK
floating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use
DATA[15..0]
. For FPP x8, use
DATA[7..0]
.
DATA[15..0]
are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device.
CONF_DONE
is released high when the Arria V device
receives all the configuration data successfully. After
CONF_DONE
goes high, send two additional falling edges on
DCLK
to begin initialization and
enter user mode.
(7) After the option bit to enable the
INIT_DONE
pin is configured into the device, the
INIT_DONE
goes low.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[15..0]
User I/O
INIT_DONE
Word 0 Word 1 Word 2 Word 3
t
CD2UM
t
CF2ST1
t
CF2CD
t
CFG
t
CH
t
CL
t
DH
t
DSU
t
CF2CK
t
STATUS
t
CLK
t
CF2ST0
t
ST2CK
High-Z User Mode
(5)
(7)
(4)
User Mode
Word n-2 Word n-1
Word n
(6)
2–40 Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–39 lists the timing parameters for Arria V devices for FPP configuration when
the
DCLK
-to-
DATA[]
ratio is 1.
Table 2–39. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is 1—Preliminary (1)
Symbol Parameter Minimum Maximum Unit
tCF2CD
nCONFIG
low to
CONF_DONE
low — 600 ns
tCF2ST0
nCONFIG
low to
nSTATUS
low — 600 ns
tCFG
nCONFIG
low pulse width 2 — µs
tSTATUS
nSTATUS
low pulse width 268 1506 (2) µs
tCF2ST1
nCONFIG
high to
nSTATUS
high — 1506 (3) µs
tCF2CK
nCONFIG
high to first rising edge on
DCLK
1506 — µs
tST2CK
nSTATUS
high to first rising edge of
DCLK
2—µs
tDSU
DATA[]
setup time before rising edge on
DCLK
5.5 — ns
tDH
DATA[]
hold time after rising edge on
DCLK
0—ns
tCH
DCLK
high time 0.45 x 1/fMAX —ns
tCL
DCLK
low time 0.45 x 1/fMAX —ns
tCLK
DCLK
period 1/fMAX —ns
fMAX
DCLK
frequency (FPP x8/ x16) — 125 MHz
tRInput rise time — 40 ns
tFInput fall time — 40 ns
tCD2UM
CONF_DONE
high to user mode (4) 175 437 µs
tCD2CU
CONF_DONE
high to
CLKUSR
enabled 4 × maximum
DCLK
period — —
tCD2UMC
CONF_DONE
high to user mode with
CLKUSR
option on
tCD2CU + (Tinit x
CLKUSR
period) ——
Tinit Number of clock cycles required for device
initialization 17,408 — Cycles
Notes to Table 2–39:
(1) Use these timing parameters when the
DCLK
-to-
DATA[]
ratio is 1. To find the
DCLK
-to-
DATA[]
ratio for your system, refer Table 2–38 on
page 2–38.
(2) You can obtain this value if you do not delay configuration by extending the
nCONFIG
or the
nSTATUS
low pulse width.
(3) You can obtain this value if you do not delay configuration by externally holding the
nSTATUS
low.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Chapter 2: Device Datasheet for Arria V Devices 2–41
Configuration Specification
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 2–6 shows the timing waveform for a FPP configuration when using a MAX II
device or microprocessor as an external host. This waveform shows timing when the
DCLK-to-DATA[]ratio is more than 1.
Figure 2–6. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 (1),(2)
Notes to Figure 2–6:
(1) To find the DCLK-to-DATA[] ratio for your system, refer Table 2–38 on page 2–38.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power up, the Arria V device holds nSTATUS low for the time as specified by the POR delay.
(4) After power up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
settings, refer to Table 2–38 on page 2–38.
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[15..0] pins prior to sending
the first DCLK rising edge.
(8) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONE is released high after the Arria V device
receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(9) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
nCONFIG
nSTATUS (3)
CONF_DONE (4)
DCLK (6)
DATA[15..0] (8)
User I/O
INIT_DONE
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCF2CK
t
tCF2ST0
tST2CK
High-Z User Mode
12 r 12 r 12
Word 0 Word 1 Word 3
1
tDSU tDH
STATUS
tDH
tCH
tCL
tCLK
Word (n-1)
(7)
(8)
(9)
(5)
User Mode
r
Word n
2–42 Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–40 lists the timing parameters for Arria V devices when the
DCLK
-to-
DATA[]
ratio is more than 1.
Table 2–40. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is >1—Preliminary (1)
Symbol Parameter Minimum Maximum Unit
tCF2CD
nCONFIG
low to
CONF_DONE
low — 600 ns
tCF2ST0
nCONFIG
low to
nSTATUS
low — 600 ns
tCFG
nCONFIG
low pulse width 2 — µs
tSTATUS
nSTATUS
low pulse width 268 1506 (2) µs
tCF2ST1
nCONFIG
high to
nSTATUS
high — 1506 (3) µs
tCF2CK
nCONFIG
high to first rising edge on
DCLK
1506 — µs
tST2CK
nSTATUS
high to first rising edge of
DCLK
2—µs
tDSU
DATA[]
setup time before rising edge on
DCLK
5.5 — ns
tDH
DATA[]
hold time after rising edge on
DCLK
3 x 1/fDCLK —ns
tCH
DCLK
high time 0.45 x 1/fMAX —ns
tCL
DCLK
low time 0.45 x 1/fMAX —ns
tCLK
DCLK
period 1/fMAX —ns
fMAX
DCLK
frequency (FPP x8/ x16) — 125 MHz
tRInput rise time — 40 ns
tFInput fall time — 40 ns
tCD2UM
CONF_DONE
high to user mode (4) 175 437 µs
tCD2CU
CONF_DONE
high to
CLKUSR
enabled 4 × maximum
DCLK
period — —
tCD2UMC
CONF_DONE
high to user mode with
CLKUSR
option on
tCD2CU + (Tinit x
CLKUSR
period) ——
Tinit Number of clock cycles required for device
initialization 17,408 — Cycles
Notes to Table 2–40:
(1) Use these timing parameters when you use decompression and the design security features.
(2) This value can be obtained if you do not delay configuration by extending the
nCONFIG
or
nSTATUS
low pulse width.
(3) This value can be obtained if you do not delay configuration by externally holding
nSTATUS
low.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Chapter 2: Device Datasheet for Arria V Devices 2–43
Configuration Specification
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
AS Configuration Timing
Figure 2–7 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Table 2–41 lists the timing parameters for AS x1 and AS x4 configurations in Arria V
devices.
Figure 2–7. AS Configuration Timing
Notes to Figure 2–7:
(1) The AS scheme supports standard and fast POR delay (tPOR). For tPOR delay information, refer to the “POR Delay Specification” section in the
Configuration, Design Security, and remote System Upgrades in Arria V Devices chapter.
(2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(3) The initialization clock can be from the internal oscillator or CLKUSR pin.
(4) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Table 2–41. AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices—Preliminary (1),(2)
Symbol Parameter Minimum Maximum Unit
tCO DCLK falling edge to the
AS_DATA0
/
ASDO
output — 4 µs
tSU Data setup time before the rising edge on
DCLK
1.5 — ns
tHData hold time after the rising edge on
DCLK
0—ns
tCD2UM
CONF_DONE
high to user mode 175 437 µs
tCD2CU
CONF_DONE
high to
CLKUSR
enabled 4 x maximum
DCLK
period — —
tCD2UMC
CONF_DONE
high to user mode with
CLKUSR
option on
tCD2CU + (Tinit x
CLKUSR
period) ——
Tinit Number of clock cycles required for device
initialization 17,408 — Cycles
Notes to Table 2–41:
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(2) The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 2–43 on
page 2–45.
2–44 Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–42 lists the internal clock frequency specification for the AS configuration
scheme.
PS Configuration Timing
Figure 2–8 shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device or microprocessor as an external host.
Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary (1),(2)
Minimum Typical Maximum Unit
5.3 7.9 12.5 MHz
10.6 15.7 25.0 MHz
21.3 31.4 50.0 MHz
42.6 62.9 100.0 MHz
Notes to Table 2–42:
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.
(2) The AS multi-device configuration scheme does not support
DCLK
frequency of 100 MHz.
Figure 2–8. PS Configuration Timing Waveform (1)
Notes to Figure 2–8:
(1) The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG
,
nSTATUS
, and
CONF_DONE
are at logic high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds
nSTATUS
low for the time of the POR delay.
(3) After power up, before and during configuration,
CONF_DONE
is low.
(4) Do not leave
DCLK
floating after configuration. You can drive it high or low, whichever is more convenient.
(5)
DATA0
is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONE is released high after the Arria V device
receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(7) After the option bit to enable the
INIT_DONE
pin is configured into the device, the
INIT_DONE
goes low.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA0
User I/O
INIT_DONE (7)
Bit 0 Bit 1 Bit 2 Bit 3 Bit n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z User Mode
(5)
(4)
(6)
Chapter 2: Device Datasheet for Arria V Devices 2–45
Configuration Specification
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Table 2–43 lists the PS timing parameter for Arria V devices.
Table 2–43. PS Timing Parameters for Arria V Devices—Preliminary
Symbol Parameter Minimum Maximum Unit
tCF2CD
nCONFIG
low to
CONF_DONE
low — 600 ns
tCF2ST0
nCONFIG
low to
nSTATUS
low — 600 ns
tCFG
nCONFIG
low pulse width 2 — µs
tSTATUS
nSTATUS
low pulse width 268 1506 (1) µs
tCF2ST1
nCONFIG
high to
nSTATUS
high — 1506 (2) µs
tCF2CK
nCONFIG
high to first rising edge on
DCLK
1506 — µs
tST2CK
nSTATUS
high to first rising edge of
DCLK
2—µs
tDSU
DATA[]
setup time before rising edge on
DCLK
5.5 — ns
tDH
DATA[]
hold time after rising edge on
DCLK
0—ns
tCH
DCLK
high time 0.45 x 1/fMAX —ns
tCL
DCLK
low time 0.45 x 1/fMAX —ns
tCLK
DCLK
period 1/fMAX —ns
fMAX
DCLK
frequency — 125 MHz
tRInput rise time — 40 ns
tFInput fall time — 40 ns
tCD2UM
CONF_DONE
high to user mode (3) 175 437 µs
tCD2CU
CONF_DONE
high to
CLKUSR
enabled 4 x maximum
DCLK
period — —
tCD2UMC
CONF_DONE
high to user mode with
CLKUSR
option on tCD2CU + (Tinit x
CLKUSR
period) ——
Tinit Number of clock cycles required for device
initialization 17,408 — Cycles
Notes to Table 2–43:
(1) You can obtain this value if you do not delay configuration by extending the
nCONFIG
or
nSTATUS
low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding
nSTATUS
low.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
2–46 Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Remote System Upgrades Circuitry Timing Specification
Table 2–44 lists the timing parameter specifications for the remote system upgrade
circuitry.
User Watchdog Internal Oscillator Frequency Specification
Table 2–45 lists the frequency specifications for the user watchdog internal oscillator.
Table 2–44. Remote System Upgrade Circuitry Timing Specification
Parameter Minimum Maximum Unit
tMAX_RU_CLK (1) —40MHz
tRU_nCONFIG (2) 250 — ns
tRU_nRSTIMER (3) 250 — ns
Notes to Table 2–44:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “Remote System Upgrade State Machine”
section in the Device Interfaces and Integration Basics for Arria V Devices chapter.
(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the Device
Interfaces and Integration Basics for Arria V Devices chapter.
Table 2–45. User Watchdog Internal Oscillator Frequency Specifications—Preliminary
Minimum Typical Maximum Unit
5.3 7.9 12.5 MHz
Chapter 2: Device Datasheet for Arria V Devices 2–47
I/O Timing
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
fYou can download the Excel-based I/O Timing spreadsheet from the Arria V Devices
Literature webpage.
Programmable IOE Delay
Table 2–46 lists the Arria V IOE programmable delay settings.
Programmable Output Buffer Delay
Table 2–47 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
Table 2–46. IOE Programmable Delay for Arria V Devices (1)
Parameter Available
Settings
Minimum
Offset
Fast Model Slow Model
Unit
Industrial Commercial C4 C5, I5 C6
TBD TBD TBD TBD TBD TBD TBD TBD ns
TBD TBD TBD TBD TBD TBD TBD TBD ns
TBD TBD TBD TBD TBD TBD TBD TBD ns
TBD TBD TBD TBD TBD TBD TBD TBD ns
TBD TBD TBD TBD TBD TBD TBD TBD ns
Note to Table 2–46:
(1) Pending the Quartus II software extraction.
Table 2–47. Programmable Output Buffer Delay—Preliminary (1),(2)
Symbol Parameter Typical Unit
DOUTBUF
Rising and/or falling edge
delay
0 (default) ps
50 ps
100 ps
150 ps
Notes to Table 2–47:
(1) Pending the Quartus II software extraction.
(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
2–48 Chapter 2: Device Datasheet for Arria V Devices
Glossary
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Glossary
Table 2–48 lists the glossary for this chapter.
Table 2–48. Glossary Table (Part 1 of 4)
Letter Subject Definitions
A
B
C
——
DDifferential I/O
Standards
Receiver Input Waveforms
Transmitter Output Waveforms
E——
F
fHSCLK Left/right PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
G
H
I
——
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
V
ID
p - n = 0 V
V
CM
Single-Ended Waveform
Differential Waveform
Positive Channel (p) = VOH
Negative Channel (n) = VOL
Ground
VOD
VOD
VOD
p - n = 0 V
VCM
Chapter 2: Device Datasheet for Arria V Devices 2–49
Glossary
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
J
J High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing
Specifications
JTAG Timing Specifications:
K
L
M
N
O
——
PPLL
Specifications
Diagram of PLL Specifications (1)
Note:
(1)
Core Clock
can only be fed by dedicated clock input pins or PLL outputs.
Q——
RR
LReceiver differential input discrete resistor (external to the Arria V device).
Table 2–48. Glossary Table (Part 2 of 4)
Letter Subject Definitions
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Core Clock
External Feedback
Reconfigurable in User Mode
Key
CLK
N
PFD
Switchover
Delta Sigma
Modulator
VCO
CP LF
CLKOUT Pins
GCLK
RCLK
f
INPFD
f
IN
f
VCO
f
OUT
f
OUT_EXT
Counters
C0..C17
4
2–50 Chapter 2: Device Datasheet for Arria V Devices
Glossary
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
S
Sampling
window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position in the sampling
window, as shown:
Single-ended
voltage
referenced I/O
standard
The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
T
tCHigh-speed receiver/transmitter input and output clock period.
TCCS (channel-
to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL Signal high-to-low transition time (80–20%)
tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO Period jitter on the GPIO driven by a PLL
tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL
tRISE Signal low-to-high transition time (20–80%)
U——
Table 2–48. Glossary Table (Part 3 of 4)
Letter Subject Definitions
Bit Time
0.5 x TCCS RSKM Sampling Window
(SW)
RSKM 0.5 x TCCS
V
IH(AC)
V
IH(DC)
V
REF
V
IL(DC)
V
IL(AC)
V
OH
V
OL
V
CCIO
V
SS
Chapter 2: Device Datasheet for Arria V Devices 2–51
Document Revision History
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Document Revision History
Table 2–49 lists the revision history for this chapter.
V
VCM(DC) DC Common mode input voltage.
VICM Input Common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH(AC) High-level AC input voltage
VIH(DC) High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL(AC) Low-level AC input voltage
VIL(DC) Low-level DC input voltage
VOCM
Output Common mode voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING Differential input voltage
VXInput differential cross point voltage
VOX Output differential cross point voltage
WW High-speed I/O block—Clock Boost Factor
X,
Y,
Z
——
Table 2–48. Glossary Table (Part 4 of 4)
Letter Subject Definitions
Table 2–49. Document Revision History
Date Version Changes
February 2012 1.3
■Updated Table 2–1.
■Updated Transceiver-FPGA Fabric Interface rows in Table 2–20.
■Updated VCCP description.
December 2011 1.2 Updated Table 2–1, and Table 2–3.
November 2011 1.1
■Updated Table 2–1, Table 2–19, Table 2–26, and Table 2–36.
■Added Table 2–5.
■Added Figure 2–4.
August 2011 1.0 Initial release.
2–52 Chapter 2: Device Datasheet for Arria V Devices
Document Revision History
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation Arria V Device Handbook
Volume 1: Device Overview and Datasheet
Additional Information
This chapter provides additional information about the document and Altera.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Typographic Conventions
The following table shows the typographic conventions this document uses.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email custrain@altera.com
Product literature Website www.altera.com/literature
Nontechnical support (general) Email nacomp@altera.com
(software licensing) Email authorization@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
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Bold Type with Initial Capital
Letters
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
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Variable names are enclosed in angle brackets (< >). For example, <file name> and
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Typographic Conventions
Arria V Device Handbook February 2012 Altera Corporation
Volume 1: Device Overview and Datasheet
Courier type
Indicates signal, port, register, bit, block, and primitive names. For example,
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tdi
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c:\qdesigns\tutorial\chiptrip.gdf
.
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1., 2., 3., and
a., b., c., and so on
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