IL-E2-0512 - Dalsa, Inc. - Product.Network

HIGH SENSITIVITY LINE SCAN

DALSA IL-E2 TDI

Image Sensors

With speed, user-selectable sensitivity (up to 96 TDI

stages), and a single output for ease of interface, the IL-E2

sensor is ideal for light-starved linescan applications.

Features

2048, 1024, & 512 pixels with 96 TDI stages

Configurable as 96,48, 24, 12, or 6 stage TDI (Time

Delay and Integration)

13µm(H) x 13µm(V) pixel size

Vertically and horizontally summed signals for higher

sensitivity

Proprietary technology for enhanced blue responsivity

Replacement for linescan sensor in low light applica-

tions

Overview

Physical Characteristics IL-E2

Pixel dimensions 13

m x 13

Active pixels per line 512 / 1024 / 2048

Active area diagonal (96 stages) 6.8 / 13.4 / 26.7mm

Active TDI stages 6, 12, 24, 48, or 96

Isolation pixels per line 5

Light-shielded pixels per line 4

The IL-E2 TDI series image sensors use DALSA’s proprie-

tary technology to achieve high output data rates of 20MHz.

The device employs buried channel CCD shift registers to

maximize output speed and reduce noise. The dynamic

range of the sensor is 1600:1. The 96 TDI stages increase

the exposure time of a single line by a factor of 96 over a

comparable line scan sensor. The IL-E2 sensors can also act

as full-frame imaging arrays although they are tested to TDI

specifications only. All sensors in the IL-E2 series are pin-,

bias-, and timing-compatible.

Applications

The IL-E2 series is ideally suited for high-speed applications

under low light conditions.

high sensitivity scanning

process monitoring and manufacturing inspection

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PIN SYMBOL NAME

1,12 CI4 Image Region Clock, Phase 4

2,11 CI3 Image Region Clock, Phase 3

13,24 CI1 Image Region Clock, Phase 1

14,23 CI2 Image Region Clock, Phase 2

3 TCK Transfer Clock

4 CR1 Readout Clock, Phase 1

5 CR2 Readout Clock, Phase 2

6 VSS Ground Reference

7 VSET Output Node Set Voltage

8 OS Output Signal

9 VDD Amplifier Supply Voltage

10 RST Output Reset Clock

15-18 CSS# Stage Select Clock 48,24,12,6

19 VBB Substrate Bias Voltage

20,21 NC No Connection

22 VOV TDI Region Overflow Gate Bias

Table 1. IL-E2 Pin Functional Description

CI4

CI3

TCK

CR1

CR2

VSS

VSET

VDD

RST

CI3

CI4

CI1

CI2

VOV

VBB

CSS6

CSS12

CSS24

CSS48

CI2

CI1

Functional Description

Detection

The imaging region consist of 96 stages of 2048, 1024, or

512 photoelements, each with a photosensitive area of 169

square micrometers and center to center spacing of 13

in both the

and

directions. A proprietary pixel architec-

ture provides improved blue light responsivity.

Transfer

TDI operation requires that the motion of a passing image

be synchronized with the imager clocks (CI1-CI4). The TDI

stage transfer is achieved by clocking the imaging clocks in

phase, i.e. CI1, CI2, CI3, CI4 (see Figure 6). Synchronization

is vital in collecting a clear image, but significant velocity mis-

match (+2%) can be tolerated before the image quality is af-

fected. When the image passes from one vertical line to the

next, the signal charge generated at the imager is passed to

the next line as well. The signal is then summed over all ac-

tive TDI stages (up to 96) before being transferred to the

readout shift register. There are two isolation, and two light

shielded columns at each end of the imaging region, as well

as an isolation row at the top and bottom of the array.

Four stage select clocks (CSS6, CSS12, CSS24, CSS48) pro-

vide the ability to reduce the number of active TDI stages.

For 96 stage operation all the CSS clocks are clocked identi-

cally to CI4. For

stage operation (

= 6, 12, 24, or 48), set

CSS

to -7.0V, and clock the remaining CSSs identically to

CI4.

The transfer gate controls the flow of light generated signal

charge from the photoelements into the HCCD shift regis-

ters. Specifically, TCK interfaces between CI4 of the imag-

ing region and CR1 of the readout shift register. Electrons

from the photoelement are transferred when a high poten-

tial (equal to the high clock voltage) is applied to the gate of

TCK. There is an isolation CCD cell at the beginning of the

readout shift register, and must be considered when clock-

ing the sensor.

Output

The readout CCD registers transfer the current line of data

serially from CR1 over the SET gate (VSET bias) onto a

floating sense diffusion. As the signal charge is received, the

potential on the diffusion is applied to the input of a two

stage source follower amplifier to produce output. The

floating sense diffusion is cleared of signal charge by the re-

set gate (RST) in preparation for the subsequent signal

charge packet.

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IL-E2

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CR1 CR2TCK VSS OS

VDDRST

VDD

VSET

VOV

2 Light-Shielded Columns

2 Isolation pixels or CCD cells

N = 512, 1024 or 2048

VBB

TDI Imaging Region

13 m x 13 m Pixels

96 TDI Rows

µµ

CSS48

CSS24

CSS12

CSS6

6TDI12 TDI

TDI Col.N

TDI Col. N-1

96 TDI

48 TDI

24 TDI

TDI Col.2

TDI Col.1

CI1

CI2

CI3

CI4

1 Isolation Row

CCD Readout Shift Register

1 Isolation Row

Relative

position

package

Pin 1

Figure 1. IL-E2 Image Sensor Block Diagram

Parameter Unit Min. Max.

Storage Temp °C -20 80

Operating Temp (ambient) °C -20 60

Voltage drop between any pin and VBB V 16

WARNING: Exceeding these values will void product warranty and may damage the device.

Table 2. IL-E2 Absolute Maximum Ratings

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IL-E2

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Symbol and Description

Unit Min. Rec. Max.

CI Image Clocks offset* V 0 0 0.5

swing* V 10 10 15

CR Readout Register Clocks offset V 0 0 0.5

swing V 10 10 15

RST Reset Clock offset V 0 0 0.5

swing V 10 10 15

TCK Transfer Clock offset V 0 0 0.5

swing V 10 10 15

ƒDATA Data rate MHz 15 20

ƒLINE Line rate 0512 kHz 31.0 38.4

1024 17.0 19.4

2048 8.0 9.7

Note: When the sensor is operated at the “Recommended” operating conditions, you may expect the “Typical”

performance specifications listed in this data sheet.

Table 3. IL-E2 AC Operating Conditions

Offset

Swing

Symbol Name Unit Min. Rec. Max.

VDD Amplifier supply voltage V 13.0 13.5 15.0

VOV Overflow gate voltage V 0.0 0.0 0.5

VSET Output node set gate voltage V 4.0 6.5 8.0

VBB Substrate bias V -3.0 0.0 0.0

VSS Ground reference V 0

CSSx 1Select clock bias V -10.0 -7.0 -5.0

Notes:

1. When clocked, use CI conditions from Table 3.

When the sensor is operated at the “Recommended” operating conditions, you may expect the “Typical” perform-

ance specifications listed in this data sheet.

Table 4. IL-E2 DC Operating Characteristics

Input Characteristics:

Capacitance to VBB 1Unit 0512 1024 2048

from CRx pF 110 220 360

from TCK pF 21 42 70

from RST pF 3 3 3

from VSET pF 7 7 7

from CIx pF 290 580 970

from CSSx pF 9 18 30

Output Characteristics:

DC Output Impedance (ROUT)

300 300 300

Amplifier Supply Current (IDD)mA101010

DC Output Offset (VOFFSET) V 8.5 8.5 8.5

Notes:

1. Using 1V pk-pk 1MHz signal with +10V DC offset.

Table 5. IL-E2 Input/Output Characteristics

CAUTION! These devices are sensitive to damage from electrostatic discharge (ESD). The leads

should be shorted together during storage or handling to prevent damage to the device.

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IL-E2

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Specification Unit Min. Typ. Max.

Saturation Output Voltage (VSAT) mV 250 300

RMS noise mV 0.19 0.25

Wavelength of peak responsivity nm 800

Peak responsivity V/(µJ/cm2) 300 400 475

Dynamic range ratio 1000:1 1600:1

Noise Equivalent Exposure (NEE) pJ/cm20.48 0.83

Saturation Equivalent Exposure (SEE) nJ/cm20.63 0.75

Fixed Pattern Noise (FPN) mV 3 15

Photoresponse Non-Uniformity (PRNU) % OS 4 20

Horizontal Charge Transfer Efficiency (CTE) 0.99995 0.99999

Vertical Charge Transfer Efficiency (CTE) 0.9999 0.99995

Dark Signal @ 25°C mV 2 12.5

Notes:

For explanations of specifications, refer to the Sensor Measurement Definitions document (doc# 03-36-00149).

Test Conditions

All measurements exclude the first and last pixel.

ƒRST = 15MHz, ƒDATA = 15MHz, ƒTCK = 3500Hz.

Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter.

Table 6. IL-E2 Performance Specifications

2.5 W/cmµ2

0.25 W/cmµ2

0.56 W/cmµ2

100

x 100 %

Signal Output

Saturation Output

Integration Time (ms)

1.00.80.6

0.4

0.2

Output vs. IntegrationTime

(@800nm)

Responsivity [V/( J/cm )]µ

Wavelength (nm)

1000

800600400 500 700 900

100

150

250

400

300

350

450

200

Responsivity

Figure 2. IL-E2 Performance Measurements

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IL-E2

For product information and updates visit www.dalsa.com High Sensitivity Line Scan

TCK

RST

CR2

CR1

Notes:

CI1

CI2

CI3

CI4 &

Note 1

t4t5

CSS6,24,48

Note 1

The line and pixel timing diagrams show the clocking when

12 stages have been selected (ie. CSS6,24 and 48 are clocked

identically to CI4 and CSS12 is set to -7.0VDC).

Figure 3. Overall Timing Diagram

Symbol Description Unit Min. Rec. Max.

t1Adjacent CI HIGH overlap

s1.0

t2Integration time

t3CI HIGH duration

s3.0

t4TCK rising edge to CI3 falling edge ns 0

t5TCK falling edge to CI4 rising edge ns 0

t6CI4 rising edge to CR1 falling edge ns 100

t7TCK falling edge to CR1 falling edge ns 100

t8CR1 rising edge to RST rising edge ns 0

t9RST falling edge to CR1 falling edge ns 0

t10 RST HIGH duration ns 15

t11 CR1 rising edge to CI3 falling edge ns 100

Table 7. IL-E2 Timing Parameters

Life Support Applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such

improper use or sale.

ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard.

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IL-E2

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Notes:

TCK

CR1

CI2

CI1

(CSS6,24,48)

CI3

t10

Sample video 3-5ns before RST goes HIGH.

The arrow indicates approximately where this

is in relation to the video.

I1 Pixel

CR2

RST

Pixel

1Pixel

(N-1)

S1 S2 S4

t11

CI4

(LOW)

(HIGH)

Note 1

Start reading

out the shift

readout register

The line and pixel timing diagrams show the clocking when

12 stages have been selected (ie. CSS6,24 and 48 are clocked

identically to CI4 and CSS12 is set to -7.0VDC).

S Light-Shielded Pixel

Isolation Pixel

Figure 4. Detailed Timing Diagram

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IL-E2

For product information and updates visit www.dalsa.com High Sensitivity Line Scan

High Speed

LowVoltage

Clock Drivers

DC Bias

With

Adjust.

Regulat.

Fixed

DC Bias

Arbitrary

Fixed

DC Bias

Possible

Interface

Circuitry

IL-E2

High Speed

High Voltage

Clock Drivers

Low Speed

High Voltage

Clock Driv.

CR1

CR2

CR1

CR2

Buffer

(If selected)

RST

None RST

CI1

CI2

VSET

VDD

VSET

VSS

VBB

VOV

CI3

CI1

CI2

CI3

CI4 CI4

TCK TCK

CSSx

VDD

VSS

VBB

VOV

CSSxCSSx

96 stages.

If using all

Figure 5. IL-E2 Operation Connections

Four Stage Select clocks (CSS6, CSS12,

CSS24 & CSS48) provide the ability to

reduce the number of active TDI stages.

For 96 stage operation, all the CSS clocks

are clocked identically to CI4. For M

stage operation (M = 6, 12, 24 or 48) set

CSSM to -7.0V, and clock the remaining

CSSs identically to CI4.

Image Stage M

Image Stage M-1

Image Stage 1

Isolation Stage 1

Isolation Stage 2

HCCD Data Pixel 1

HCCD Isolation Pixel

Light Shielded Pixel 1

Light Shielded Pixel 2

Light Shielded Pixel 3

Light Shielded Pixel 4

Isolation Pixel 1

Isolation Pixel 3

Isolation Pixel 4

Isolation Pixel 2

HCCD Data Pixel N

VSET

CR1

CR2

CR1

RST

VDD

VSS

TCK TCKTCK TCKTCK TCKTCK TCKTCK TCKTCK

VOV

VDD

CI3

CI1

CI3

CI4

CI2

CI4

Figure 6. IL-E2 Gate Structure

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IL-E2

High Sensitivity Line Scan For product information and updates visit www.dalsa.com

Pin 1 Pin 12

Pin 24 Pin 13

0.284±0.010 [7.2±0.3]

0.834±0.010 [21.2±0.3]

0.148±0.010 [3.7±0.3]

0.300±0.010 [7.6±0.3]

0.295±0.005 [7.5±0.1]

1.669±0.012 [42.4±0.3]

0.025±0.003 [0.6±0.1] 0.040±0.004 [1.0±0.1]

0.085±0.007 [2.2±0.2]

0.040±0.002 [1.0±0.1]

0.016±0.002 [0.4±0.1]

0.106±0.002 [2.7±0.1]

Pin 1 Pin 12

Pin 24 Pin 13

0.284±0.010 [7.2±0.3]

0.834±0.010[21.2±0.3]

0.148±0.010 [3.7±0.3]

0.300±0.010 [7.6±0.3]

0.100±0.005 [2.5±0.1] 1.100±0.005 [27.9±0.1]

0.295±0.005 [7.5±0.1]

0.050±0.010 [1.3±0.3]

0.190±0.020 [4.8±0.5]

1.669±0.012 [42.4±0.3]

0.018±0.002 [0.5±0.1]

0.025±0.003 [0.6±0.1] 0.040±0.004 [1.0±0.1]

0.085±0.007 [2.2±0.2]

0.040±0.002 [1.0±0.1]

0.016±0.002 [0.4±0.1]

0.106±0.002[2.7±0.1]

NOTES: 1) THE DIE IS PLACED IN THE MIDDLE OFTHE PACKAGE ±0.010[±0.3] UNITS: IN.[mm]

Pin 1 Pin 12

Pin 24 Pin 13

0.284±0.010 [7.2±0.3]

0.834±0.010 [21.2±0.3]

0.148±0.010 [3.7±0.3]

0.300±0.010 [7.6±0.3]

0.295±0.005 [7.5±0.1]

1.669±0.012 [42.4±0.3]

0.025±0.003 [0.6±0.1] 0.040±0.004 [1.0±0.1]

0.085±0.007 [2.2±0.2]

0.040±0.002 [1.0±0.1]

0.016±0.002 [0.4±0.1]

0.106±0.002 [2.7±0.1]

Figure 7. IL-E2 Package Dimensions

512 Resolution

1024 Resolution

2048 Resolution