© 2008-2012 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
This document provides an overview of t he MPC8378E
PowerQUICC II Pro processor features, including a block
diagram show ing the major functional components. This
chip is a cost-ef fective, low-power, highly integrated host
processor that addresses the requirements of several
printing and imaging, consum er, and industrial
applications, including m ain CPUs and I/O processors in
printing systems, networking switches and line cards,
wireless LANs (WLANs), network access servers (NAS),
VPN routers, intelligent NIC, and industrial controllers.
This chip extends the PowerQUICC family, adding higher
CPU performance, additional functionality, and faster
interfac es while addressing the requirements relate d to
time-to-market, price, power consumption, and package
size.
1Overview
This chip incorporates the e300c4s core, which includes
32 KB of L1 instruction and data caches and on-chip
memory management units (MMUs). The device offer s
two enhanced three-speed 10, 100, 1000 Mbps Ethernet
interfac es, a DDR1/DDR2 SDRAM me mory contr olle r, a
flexible, a 32-bit local bus controller, a 32-bit PCI
controller, an optional dedicate d security engine, a USB
2.0 dual-role controller, a programmable interrupt
Document Number: MPC8378EEC
Rev. 8, 05/2012
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15
6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. Enhanced Secure Digital Host Controller (eSDHC) 49
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 79
21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 89
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
24. System Design Information . . . . . . . . . . . . . . . . . . 121
25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 123
26. Document Revision History . . . . . . . . . . . . . . . . . . 125
MPC8378E
PowerQUICC II Pro Processor
Hardware Specifications
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
2Freescale Semiconductor
controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,
and a general-purpose I/O port. This figure shows the block diagram of the chip.
Figure 1. MPC8378E Block Diagram and Features
The following feature s are supported in the chip:
• e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB
data cache, a floating point unit, and two integer units
• DDR1/DDR2 memory controller supporting a 32/64-bit interface
• Peripheral i nterfaces , such as a 32-bit PCI inter fac e with up to 66-MH z operatio n
• 32-bit local bus interface running up to 133-MHz
• USB 2.0 (full/high speed) support
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation Powe rQUICC processor-based
designs for backward compatibility and easier software migration
• Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
MPC8378E
DMA PCI
Security Enhanced
e300 Core
32 KB
I-Cache
32 KB
D-Cache
DUART
Dual I2C
Timers
GPIO
SPI
Interrupt
Controller
DDR1/DDR2
SDRAM
Controller
Local Bus
SD/MMC
Controller
USB 2.0
Hi-Speed
Host Device
eTSEC
SGMII,
RGMII, RMII,
RTBI, MII
eTSEC
SGMII,
RGMII, RMII,
RTBI, MII
PCI
Express
x1 x2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 3
In addition to the secur ity engine, new high-speed inte rfaces , such as SGMII inter fa ce on enhanced
Ethernet and PCI Express, are included. This table compares the dif ferences between MPC837xE
derivatives and provides the number of ports available for each interface.
1.1 DDR Memory Controller
The DDR1/DDR2 memory controller include s the following features:
• Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 400-MHz data rate
• Support up to 4 chip selects
• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with ×8/×16/×32 data ports (no
direct ×4 support)
• Support for up to 32 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatibl e I/O
1.2 USB Dual-Role Controller
The USB controller includes the following feature s:
• Supports USB on-the-go mode , including both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
• Complies with USB Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interfa ce (EHCI ) compatible
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;
low-speed operation is supported only in host mode
• Supports UTMI + low pin interface (ULPI)
Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E
Descriptions MPC8377E MPC8378E MPC8379E
SGMII 020
PCI Express® 2 2 0
SATA 204
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
4Freescale Semiconductor
1.3 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
• Two enhanced Ethernet interfaces can be used for RGMII/ MI I/RMI I/RT BI/S GMI I
• Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards
• Support for W ake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status
1.4 Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redir ected to an external interrupt controller.
1.5 Power Management Controller (PMC)
The power management controller includes the following features:
• Provides power management when the device is used in both host and agent mode s
• Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
• Support for PME generation in PCI agent mode, PME detection in PCI host mode
• Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
• Supports MPC8349E backward-compatibility mode
1.6 Serial Peripheral Interface (SPI)
The serial per ipheral int erface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs , real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(rec eiv e, transmit, clock, and slave sele ct). The SPI block consist s of transmitter a nd receiver sections, an
independent baud-rate generator, and a control unit.
1.7 DMA Controller, Dual I2C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
• Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(acces si ble by local ma st er s)
• Supports misaligned transfers
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 5
There are two I2C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the tra nsmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling e ight memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EP ROM , NAND Flash,
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with
data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such
as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle
is terminated withi n a user-specified period. The local bus can operate at up to 133 MHz.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
1.8 Security Engine
The optional security engine is opt imize d to handle all the algorithm s associated with IPSec,
IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are as follows:
• Data encryption standard execution unit (DEU), supporting DES and 3D ES
• Advanced encryption standard unit (AESU), supporting AES
• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
• One crypto-channel supporting multi-command descriptor chains
1.9 PCI Controller
The PCI controller includes the following features:
•PCI Specification Revision 2.3 compatible
• Single 32-bit data PCI interfac e operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting 5 external masters on PCI
• Selectable hardware-enfor ced coherency
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
6Freescale Semiconductor
1.10 PCI Express Controller
The PCI Express controller includes the following features:
• PCI Express 1.0a compatible
•Two ×1 links or one ×2 link width
• Auto-detection of number of connected lanes
• Selectable operation as root complex or endpoint
• Both 32- and 64-bit addressing
• 128-byte maximum payload size
• Support for MSI and INTx interrupt messages
• Virtual channel 0 only
• Select able Traffic Class
• Full 64-bit decode with 32-bit wide windows
• Dedicated four channel descriptor -based DMA engine per interface
1.11 Enhanced Secured Digital Host Controller (eSDHC)
The enhanced SD host controller (eSDHC) has the following features:
• Conforms to S D Host Controller Standard Specification, Rev 2.0 with Test Event register support.
• Compatible wi th the MMC System Specification, Rev 4.0
• Compatible wi th the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD
memory cards
• Compatible wi th the SDIO Card Specification Rev, 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSD IO, SD Co mbo, MMC,
MMCplus, MMC 4x, and RS-MMC cards
• SD bus clock frequency up to 50 MHz
• Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes
• Supports internal DMA capabilities
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the chip. The
device is currently targeted to these specifications. Some of these specifications are independent of the I/O
cell, but are included for a more complete reference. These are not purely I/O buff er design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 7
2.1.1 Absolute Maximum Ratings
This table provides the absolute maximum ratings.
Table 2. Absolute Maximum Ratings1
Characteristic Symbol Max Value Unit Note
Core supply voltage VDD –0.3 to 1.1 V —
PLL supply voltage (e300 core, eLBC, and system) AVDD –0.3 to 1.1 V —
DDR1 and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75
–0.3 to 1.98
V—
Three-speed Ethernet I/O, MII management voltage LVDD[1,2] –0.3 to 3.63 V —
PCI, DUART, system control and power management, I2C, and
JTAG I/O voltage
OVDD –0.3 to 3.63 V —
Local bus LBVDD –0.3 to 3.63 V —
SerDes L[1,2]_
n
VDD –0.3 to 1.1 V 6
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 4
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 4
Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V —
PCI, DUART, CLKIN, system control and power
management, I2C, and JTAG signals
OVIN –0.3 to (OVDD + 0.3) V 3, 4, 5
Local Bus LBIN –0.3 to (LBVDD + 0.3) V —
Storage temperature range TSTG –55 to 150 °C—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
5. Overshoot/undershoot by OVIN on the PCI interface does not comply to the
PCI Electrical Specification
for 3.3-V operation,
as shown in Figure 2.
6. L[1,2]_
n
VDD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
8Freescale Semiconductor
2.1.2 Power Supply Voltage Specification
This table provides recommended operating conditions for the device. Note that the values in this table are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 3. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit Note
Core supply voltage up to 667 MHz VDD 1.0 ± 50 mV V 1
800 MHz 1.05 ± 50 mV V 1
PLL supply voltage (e300 core, eLBC and
system)
up to 667 MHz AVDD 1.0 ± 50 mV V 1, 2
800 MHz 1.05 ± 50 mV V 1, 2
DDR1 and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V1
Three-speed Ethernet I/O, MII management voltage LVDD[1,2] 3.3 V ± 165 mV
2.5 V ± 125 mV
V—
PCI, local bus, DUART, system control and power management, I2C, and
JTAG I/O voltage
OVDD 3.3 V ± 165 mV V 1
Local Bus LBVDD 1.8 V ± 90 mV
2.5 V ± 125 mV
3.3 V ± 165 mV
V—
SerDes up to 667 MHz L[1,2]_
n
VDD 1.0 ± 50 mV V 1, 3
800 MHz 1.05 V ± 50 mV V 1, 3
Operating temperature range commerical Ta
Tj
Ta=0 (min)—
Tj=125 (max)
°C—
extended temperature Ta
Tj
Ta=–40 (min)—
Tj=125 (max)
°C—
Notes:
1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
direction.
2. AVDD is the input to the filter discussed in Section 24.1, “PLL Power Supply Filtering,” and is not necessarily the voltage at
the AVDD pin.
3. L[1,2]_
n
VDD, SDAVDD_0, XCOREVDD, and XPADVDD power inputs.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 9
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
Figure 2. Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD
2.1.3 chipOutput Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are
prelimina ry estimates .
Table 4. Output Drive Capability
Driver Type1Output Impedance (Ω) Supply Voltage
Local bus interface utilities signals 45 LBVDD = 2.5 V, 3.3 V
40 LBVDD = 1.8 V
PCI signals 25 OVDD = 3.3 V
DDR1 signal 18 GVDD = 2.5 V
DDR2 signal 18 GVDD = 1.8 V
eTSEC 10/100/1000 signals 45 LVDD = 2.5 V, 3.3 V
DUART, system control, I2C, JTAG, SPI, and USB 45 OVDD = 3.3 V
GPIO signals 45 OVDD = 3.3 V
Note:
1. Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as SGMII and
PCI Express)
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/O/LBVDD + 20%
G/L/O/LBVDD
G/L/O/LBVDD + 5%
of tinterface1
1. Note that tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
2. Note that with the PCI overshoot allowed (as specified above), the device does
not fully comply with the maximum AC ratings and device protection guideline outlined in
the
PCI Rev. 2.3 Specification
(Section 4.2.2.3).
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
10 Freescale Semiconductor
2.2 Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time t hat all input and out put pins will actively
be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to
elimin ate exces sive curre nt dra w, apply the core voltages (VDD and AVDD) before the I/O voltages and
as sert POR ESE T before the power supplies fully ramp up. VDD and AVDD must reach 90% of their
nominal value before GVDD, LV DD, and OVDD reach 10% of the ir value, see the following figure. I/O
voltage supplies—GVDD, LVDD, and OVDD—do not have any ordering requirements wit h res pect to one
another.
Figure 3. Power-Up Sequencing Example
Note that the SerDes power supply (L[1,2]_nVDD) should follow the same timing as the core supply
(VDD).
The device does not require the core supply voltage and I/O supply voltages to be powered down in any
particular orde r.
3 Power Characteristics
The estimated typical power dissipation for the chip device is shown in this table.
Table 5. Power Dissipation 1
Core Frequency
(MHz)
CSB/DDR Frequency
(MHz)
Sleep Power
at Tj=65°C (W) 2Typical Application
at Tj=65°C (W) 2Typical Application
at Tj=125°C (W) 3Max Application
at Tj=125°C (W) 4
333
333 1.45 1.9 3.2 3.8
167 1.45 1.8 3.0 3.6
400
400 1.45 2.0 3.3 4.0
266 1.45 1.9 3.1 3.8
t
90%
V
Core Voltage (VDD, AVDD)
I/O Voltage (GVDD, LVDD, and OVDD)
0
0.7 V
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 11
450
300 1.45 2.0 3.2 3.8
225 1.45 1.9 3.1 3.7
500
333 1.45 2.0 3.3 3.9
250 1.45 1.9 3.2 3.8
533
355 1.45 2.0 3.3 4.0
266 1.45 2.0 3.2 3.9
600
400 1.45 2.1 3.4 4.1
300 1.45 2.0 3.3 4.0
667
333 1.45 2.1 3.3 4.1
266 1.45 2.0 3.3 3.9
800 400 1.45 2.5 3.8 4.3
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Ta bl e 6 .
2. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies of
800 MHz, and running a Dhrystone benchmark application.
3. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies of
800 MHz, and running a Dhrystone benchmark application.
4. Maximum power is based on a voltage of VDD = 1.0 V for core frequencies ≤667 MHz or VDD = 1.05 V for core frequencies
of 800 MHz, worst case process, and running an artificial smoke test.
Table 5. Power Dissipation 1 (continued)
Core Frequency
(MHz)
CSB/DDR Frequency
(MHz)
Sleep Power
at Tj=65°C (W) 2
Typical Application
at Tj=65°C (W) 2
Typical Application
at Tj=125°C (W) 3
Max Application
at Tj=125°C (W) 4
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
12 Freescale Semiconductor
This table shows the estimated typical I/O power dissipation for the device.
Table 6. Typical I/O Power Dissipation
Interface Parameter GVDD
(1.8 V)
GVDD/LBVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
L[1,2]_
n
VDD
(1.0 V) Unit Comments
DDR I/O
65%
utilization
2 pair of
clocks
200 MHz data
rate, 32-bit
0.28 0.35 — — — — W —
200 MHz data
rate, 64-bit
0.41 0.49 — — — — W
266 MHz data
rate, 32-bit
0.31 0.4 — — — — W
266 MHz data
rate, 64-bit
0.46 0.56 — — — — W
300 MHz data
rate, 32-bit
0.33 0.43 — — — — W
300 MHz data
rate, 64-bit
0.48 0.6 — — — — W
333 MHz data
rate, 32-bit
0.35 0.45 — — — — W
333 MHz data
rate, 64-bit
0.51 0.64 — — — — W
400 MHz
data rate,
32-bit
0.38 — — — — — W
400 MHz
data rate,
64-bit
0.56 — — — — — W
PCI I/O
Load =
30 pf
33 MHz,
32-bit
— — 0.04 — — — W —
66 MHz,
32-bit
— — 0.07 — — — W
Local Bus
I/O
Load =
25 pf
167 MHz,
32-bit
0.09 0.17 0.29 — — — W —
133 MHz,
32-bit
0.07 0.14 0.24 — — — W
83 MHz,
32-bit
0.05 0.09 0.15 — — — W
66 MHz,
32-bit
0.04 0.07 0.13 — — — W
50 MHz,
32-bit
0.03 0.06 0.1 — — — W
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 13
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the chip. Note that the
PCI_CLK/PCI_SYNC_IN signal or CLK IN signal is used as the PCI input clock depending on whether
the device is configured as a host or agent device. CLKIN is used when the device is in host mode.
4.1 DC Electrical Characteristics
This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
eTSEC I/O
Load =
25 pf
MII or RMII — — — 0.02 — — W Multiply by
number of
interfaces used.
SGMII — — — — — 0.029 W —
RGMII or
RTBI
— — — — 0.05 — W —
USB
(60MHz
Clock)
12 Mbps — — 0.01 — — — W —
480 Mbps — — 0.2 — — — W
SerDes per lane — — — — 0.029 W —
Other I/O — — — 0.01 — — — W —
Note: The values given are for typical, and not worst case, switching.
Table 7. CLKIN DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit Note
Input high voltage — VIH 2.7 OVDD + 0.3 V 1
Input low voltage — VIL –0.3 0.4 V 1
CLKIN Input current 0 V ≤VIN ≤ OVDD IIN —± 10μA—
PCI_CLK Input current 0 V ≤VIN ≤ 0.5 V or
OVDD – 0.5 V ≤VIN ≤ OVDD
IIN —± 30μA—
Note:
1. In PCI agent mode, this specification does not comply with
PCI 2.3 Specification
.
Table 6. Typical I/O Power Dissipation (continued)
Interface Parameter GVDD
(1.8 V)
GVDD/LBVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
L[1,2]_
n
VDD
(1.0 V) Unit Comments
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
14 Freescale Semiconductor
4.2 AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, de pending on
whether the device is configured in PCI host or PCI agent mode. This table provides the clock input
(CLKIN/PCI_CLK) AC timing spec ifications for the device.
4.3 eTSEC Gigabit Reference Clock Timing
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 8. CLKIN AC Timing Specifications
Parameter Symbol Min Typical Max Unit Note
CLKIN/PCI_CLK frequency fCLKIN 25 — 66.666 MHz 1, 6
CLKIN/PCI_CLK cycle time tCLKIN 15 — 40 ns —
CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2
CLKIN/PCI_CLK duty cycle tKHK/tCLKIN 40 — 60 % 3
CLKIN/PCI_CLK jitter — — — ± 150 ps 4, 5
Notes:
1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter-short term and long term-and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low
to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
Table 9. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter/Condition Symbol Min Typical Max Unit Note
EC_GTX_CLK125 frequency tG125 — 125 — MHz —
EC_GTX_CLK125 cycle time tG125 —8—ns—
EC_GTX_CLK rise and fall time
LV DD = 2.5 V
LV DD = 3.3 V
tG125R/tG125F ——
0.75
1.0
ns 1
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII, RTBI
tG125H/tG125
47
—
53
%2
EC_GTX_CLK125 jitter — — — ±150 ps 2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The
EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See Section 8.3.4, “RGMII and RTBI AC Timing Specifications,” for the duty cycle for
10Base-T and 100Base-T reference clock.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 15
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electri cal requir ement s of the chip.
5.1 RESET DC Electrical Characteristics
This table provides the DC electri cal chara cteri stics for the RESET pins of the device.
5.2 RESET AC Electrical Characteristics
This table provides the reset initia lization AC timing specifications of the device.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Input high voltage VIH —2.0OV
DD + 0.3 V
Input low voltage VIL — –0.3 0.8 V
Input current IIN ——± 30μA
Output high voltage VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Notes:
• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
• HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Note
Required assertion time of HRESET to activate reset flow 32 — tPCI_SYNC_IN 1
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32 — tCLKIN 2
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32 — tPCI_SYNC_IN 1
HRESET assertion (output) 512 — tPCI_SYNC_IN 1
HRESET negation to negation (output) 16 — tPCI_SYNC_IN 1
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4— t
CLKIN 2
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—t
PCI_SYNC_IN 1
Input hold time for POR config signals with respect to negation of HRESET 0— ns —
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
16 Freescale Semiconductor
Table 12 provides the PLL l ock times .
6 DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.
Note that DDR1 SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—4 ns 3
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1—t
PCI_SYNC_IN 1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E Integrated Host Processor Reference Manual
for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual
for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 12. PLL Lock Times
Parameter Min Max Unit Note
PLL lock times — 100 μs—
Note:
• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 22, “Clocking,” for more information.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter Symbol Min Max Unit Note
I/O supply voltage GVDD 1.71 1.89 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2, 5
I/O termination voltage VTT MVREF –0.04 MV
REF +0.04 V 3
Input high voltage VIH MVREF + 0.140 GVDD +0.3 V —
Input low voltage VIL –0.3 MVREF – 0.140 V —
Output leakage current IOZ –50 50 μA4
Output high current (VOUT =1.40V) I
OH –13.4 — mA —
Table 11. RESET Initialization Timing Specifications (continued)
Parameter/Condition Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 17
Table 14 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Output low current (VOUT =0.3V) I
OL 13.4 — mA —
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 ×GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
. This rail should track variations in the DC level of MVREF
.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 14. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter Symbol Min Max Unit Note
Input/output capacitance: DQ, DQS, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter Symbol Min Max Unit Note
I/O supply voltage GVDD 2.375 2.625 V 1
I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2, 5
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.18 GVDD + 0.3 V —
Input low voltage VIL –0.3 MVREF – 0.18 V —
Output leakage current IOZ –50 50 μA4
Output high current (VOUT = 1.9 V) IOH –15.2 — mA —
Output low current (VOUT = 0.38 V) IOL 15.2 — mA —
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD
, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
. This rail should track variations in the DC level of MVREF
.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
.
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Parameter Symbol Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
18 Freescale Semiconductor
Table 16 provides the DDR capacitance when GVDD(typ) = 2.5 V.
This table provides the current draw c haracteristics for MVREF.
6.2 DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electr ical characteristic s for the DDR S DRAM interfac e.
6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
This table provides the input AC timing specifications for the DDR1 SDRAM when GVDD(typ) = 2.5 V.
Table 16. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter Symbol Min Max Unit Note
Input/output capacitance: DQ, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA= 25°C, VOUT =GV
DD/2, VOUT (peak-to-peak) = 0.2 V.
Table 17. Current Draw Characteristics for MVREF
Parameter Symbol Min Typ Max Unit Note
Current draw for MVREF
DDR1
DDR2
IMVREF
—
—
250
150
600
400
μA1, 2
Note:
1. The voltage regulator for MVREF must be able to supply up to the stated maximum current.
2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.25 V
AC input high voltage VIH MVREF + 0.25 — V
Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.31 V
AC input high voltage VIH MVREF + 0.31 — V
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 19
This table provides the input AC timing specificati ons for the DDR1 and DDR2 SDRAM interface.
6.2.2 DDR1 and DDR2 SDRAM Output AC Timing Specifications
This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.
Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter Symbol Min Max Unit Note
Controller skew for MDQS-MDQ/MECC/MDM
400 MHz data rate
333 MHz data rate
266 MHz data rate
tCISKEW
–500
–750
–750
500
750
750
ps 1, 2
3
—
—
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS
n
and any corresponding bit that
will be captured with MDQS
n
. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the
absolute value of tCISKEW.
3. This specification applies only to DDR2 interface.
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications
Parameter Symbol1Min Max Unit Note
MCK
n
cycle time, MCK
n
/MCK
n
crossing tMCK 510ns2
ADDR/CMD output setup with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHAS
1.95
2.40
3.15
4.20
—
—
—
—
ns 3, 7
ADDR/CMD output hold with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHAX
1.95
2.40
3.15
4.20
—
—
—
—
ns 3, 7
MCS
n
output setup with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHCS
1.95
2.40
3.15
4.20
—
—
—
—
ns 3
MCS
n
output hold with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHCX
1.95
2.40
3.15
4.20
—
—
—
—
ns 3
MCK to MDQS skew tDDKHMH –0.6 0.6 ns 4, 8
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
20 Freescale Semiconductor
The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz
clock) for DDR1. This figure shows the DDR1 and DDR 2 SDRAM output timing for t he MCK to MDQS
skew measurement (tDDKHMH).
MDQ//MDM output setup with respect to MDQS
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHDS,
tDDKLDS 550
800
1100
1200
—
—
—
—
ps 5, 8
MDQ//MDM output hold with respect to MDQS
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHDX,
tDDKLDX 700
800
1100
1200
—
—
—
—
ps 5, 8
MDQS preamble start tDDKHMP –0.5 × tMCK –0.6 –0.5 × tMCK + 0.6 ns 6, 8
MDQS epilogue end tDDKHME –0.6 0.6 ns 6, 8
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set
to the same adjustment value. See the
MPC8379E PowerQUICC II Pro Host Processor Reference Manual
for a description
and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or
data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK
n
at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in Note 1.
7. Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.
8. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter Symbol1Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 21
Figure 4. DDR Timing Diagram for tDDKHMH
This figure shows the DDR1 and DDR2 SDRAM output timing diagram.
Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram
MDQS
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
tDDKHMH(min) = –0.6 ns
MDQS
ADDR/CMD
tDDKHAS ,tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n] tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX ,tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMP
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
22 Freescale Semiconductor
This figure provides AC test load for the DDR bus.
Figure 6. DDR AC Test Load
7DUART
This section describes the DC and AC electrical s pecif ications for the DUART inte rface of the chip.
7.1 DUART DC Electrical Characteristics
This table provides the DC electrical characteristics for the DUART interface of the device.
7.2 DUART AC Electrical Specifications
this table provides the AC timing parameters for the DUART interface of the device.
Table 22. DUART DC Electrical Characteristics
Parameter Symbol Min Max Unit
High-level input voltage VIH 2OV
DD + 0.3 V
Low-level input voltage OVDD VIL –0.3 0.8 V
High-level output voltage,
IOH = –100 μA
VOH OVDD – 0.2 — V
Low-level output voltage,
IOL = 100 μA
VOL —0.2 V
Input current,
(0 V ≤VIN ≤ OVDD)
IIN —±30μA
Note: The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2.
Table 23. DUART AC Timing Specifications
Parameter Value Unit Note
Minimum baud rate 256 baud —
Maximum baud rate > 1,000,000 baud 1
Oversample rate 16 — 2
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
Output Z0 = 50 Ω
RL = 50 Ω
GVDD/2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 23
8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet
controller.
8.1 SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes1 interface of the
MPC8378E as shown in Figure 7, where CTX is the external (on board) AC-coupled capacitor. Each output
pin of the SerDes transmit ter dif fere ntial pa ir fe ature s 50-Ω output impedance. Each input of the SerDes
receiver differential pair features 50-Ω on-die termination to SGND_SRDSn (xco re v s s). The refere n c e
circuit of the SerDes transm itter and receiver is shown in Figure 65.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. Also, when operating in SGMII mode, the eTSEC EC_GTX_CLK125
clock is not required for this port. Instead, the SerDes reference clock is required on L1_SD_REF_CLK
and L1_SD_REF_CLK pins.
Figure 7. 4-Wire AC-Coupled SGMII Serial Link Connection Example
8.2 Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—SGMII/MII/RGMII/RTBI/RMII DC Electrical
Characteristics
The electri cal chara ct er isti cs specified here apply to serial gigabit media independent interface (SGMII),
media independent interface (MII), reduced gigabit media independent interface (RGMII), reduced ten-bit
interface (RTBI), reduced media independent interface (RMII) signals, management data input/output
(MDIO) and management data clock (MDC).
SGMII SerDes
Interface
50 Ω
50 Ω
Transmitter
SD_TX
n
SD_RX
m
SD_TX
n
SD_RX
m
Receiver
CTX
CTX
50 Ω
50 Ω
SD_RX
n
SD_RX
n
Receiver Transmitter
SD_TX
m
SD_TX
m
CTX
CTX
50 Ω
50 Ω
50 Ω
50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
24 Freescale Semiconductor
The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated
at 2.5 V. The SGMII interf ace conforms to the Serial-GMII Specification Version 1.8 with some
exceptions. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface
(RGMI I) Spec ification Ver sion 1.3 . The RMI I interface fol l ows the RMI I Consortium RM II Spec ific ation
Version 1.2.
8.2.1 MII, RMII, RGMII, and RTBI DC Electrical Characteristics
MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 24 and
Table 25. The RGMII a n d RTBI sig na l s i n Table 25 are based on a 2.5 V CM OS interface voltage as
defined by JEDEC EIA/JESD8-5.
Table 24. MII and RMII DC Electrical Characteristics
Parameter Symbol Min Max Unit Note
Supply voltage 3.3 V LVDD1
LV DD2
3.13 3.47 V 1
Output high voltage
(LVDD1/LVDD2 = Min, IOH = –4.0 mA)
VOH 2.40 LVDD1/LVDD2 + 0.3 V —
Output low voltage
(LVDD1/LVDD2 = Min, IOL = 4.0 mA)
VOL GND 0.50 V —
Input high voltage VIH 2.0 LVDD1/LVDD2 + 0.3 V —
Input low voltage VIL –0.3 0.90 V —
Input high current
(VIN = LVDD1, VIN = LVDD2)
IIH —30μA1
Input low current
(VIN = GND)
IIL –600 — μA—
Notes:
1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.
Table 25. RGMII and RTBI DC Electrical Characteristics
Parameter Symbol Min Max Unit Note
Supply voltage 2.5 V LVDD1
LVDD2
2.37 2.63 V 1
Output high voltage
(LVDD1/LVDD2 = Min, IOH = –1.0 mA)
VOH 2.00 LVDD1/LVDD2 + 0.3 V —
Output low voltage
(LVDD1/LVDD2 = Min, IOL = 1.0 mA)
VOL GND – 0.3 0.40 V —
Input high voltage VIH 1.7 LVDD1/LVDD2 + 0.3 V —
Input low voltage VIL –0.3 0.70 V —
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 25
8.2.2 SGMII DC Electrical Characteristics
Table 26 and Table 27 describe the SGMII DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (L1_SD1_TXn and L1_SD1_TXn) as depicted in Figure 8.
NOTE
The voltage levels of th e transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for SGMII protocol (L1_nVDD =1.0V).
Input high current
(VIN = LVDD1, VIN = LVDD2)
IIH —–20μA1
Input low current
(VIN = GND)
IIL –20 — μA—
Notes:
1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.
Table 26. SGMII DC Transmitter Electrical Characteristics
Parameter Symbol Min Typ Max Unit Note
Supply voltage
(L1_SDAVDD_0,
L1_XCOREVDD)
XVDD_SRDS 0.95 1.0 1.05 V —
Output high voltage VOH ——XV
DD_SRDS-Typ/2
+ |VOD|-max/2
mV 1
Output low voltage VOL XVDD_SRDS-Typ/2
– |VOD|-max/2
——mV1
Output ringing VRING ——10%—
Table 25. RGMII and RTBI DC Electrical Characteristics (continued)
Parameter Symbol Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
26 Freescale Semiconductor
Output differential voltage 2, 3, 7 |VOD| 323 500 725 mV Equalization
setting: 1.0×
296 459 665 Equalization
setting: 1.09×
269 417 604 Equalization
setting: 1.2×
243 376 545 Equalization
setting: 1.33×
215 333 483 Equalization
setting: 1.5×
189 292 424 Equalization
setting: 1.71×
162 250 362 Equalization
setting: 2.0×
Output offset voltage VOS 425 500 575 mV 1, 6
Output impedance
(single-ended)
RO40 — 60 Ω—
Mismatch in a pair RO——10%—
Change in VOD between “0” and
“1”
|VOD|— — 25mV—
Change in VOS between “0” and
“1”
VOS ——25mV—
Output current on short to GND ISA, ISB ——40mA—
Notes:
1. This will not align to DC-coupled SGMII. XVDD_SRDS-Typ =1.0V.
2. |VOD|=|V
SD_TXn -V
SD_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p =2×|VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in SRDS
n
CR0[DDPA] and
SRDS
n
CR0[TXEQA] for lane A, and SRDS
n
CR0[DDPE] and SRDS
n
CR0[TXEQE] for lane E.
4. DPPA or DPPE bit is set to zero (selecting the full VDD-DIFF-p-p amplitude – power up default);
5. TXEQA or TXDQE is set based on the equalization setting shown in table.
6. VOS is also referred to as output common mode voltage.
7. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS-Typ = 1.0 V, no common mode offset
variation (VOS = 500 mV), SerDes1 transmitter is terminated with 100-Ω differential load between SD_TX
n
and SD_TX
n
.
Table 27. SGMII DC Receiver Electrical Characteristics
Parameter Symbol Min Typical Max Unit Note
Supply voltage
(L1_SDAVDD_0, L1_XCOREVDD)
XVDD_SRDS 0.95 1.0 1.05 V —
DC input voltage range — N/A — 1
Table 26. SGMII DC Transmitter Electrical Characteristics (continued)
Parameter Symbol Min Typ Max Unit Note
Δ
Δ
Δ
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 27
Figure 8. SGMII Transmitter DC Measurement Circuit
8.2.3 DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK_B
See Section 20.2.2, “DC Level Requirement for SerDes Reference Clocks.”
8.3 SGMII, MII, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for SGMII, MII, RGMII, RMII, and RT BI are presented in this section.
Input differential voltage
SEIC
x
= 01
SEIC
x
= 00
VRX_DIFFp-p
100
175
—1200mV2, 4
Loss of signal threshold
SEIC
x
= 01
SEIC
x
= 00
VLOS
30
65
—
100
175
mV 3, 4
Input AC common mode voltage VCM_ACp-p — 100 mV 5
Receiver differential input
impedance
ZRX_DIFF 80 100 120 Ω—
Receiver common mode input
impedance
ZRX_CM 20 — 35 Ω—
Common mode input voltage VCM —V
xcorevss —V6
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage.
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI
Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The SEIC
x
shown in the table refers to SRDS
n
CR[SEICA] for lane A and SRDS
n
CR[SEICE] for lane E.
5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage.
6. On-chip termination to SGND_SRDS
n
(xcorevss).
Table 27. SGMII DC Receiver Electrical Characteristics (continued)
Parameter Symbol Min Typical Max Unit Note
50
Ω
Transmitter
L1_SD_TX
n
L1_SD_TX
n
50
Ω
Vos VOD
MPC8378E SGMII
SerDes Interface
50
Ω
50
Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
28 Freescale Semiconductor
8.3.1 SGMII AC Timing Specifications
This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver
charac teris tic s are measure d at the trans mitte r outputs (L1_SD_T Xn and L1_SD_TXn) or at the receiver
inputs (L1_SD_RXn and L1_SD_RXn) as depicted i n Figure 9 respect i vel y.
Figure 9. SGMII AC Test/Measurement Load
8.3.1.1 SGMII Transmit AC Timing Specifications
This table provides the SGMII transmit AC timing targets. Source synchronous clocking is not supported.
Table 28. SGMII Transmit AC Timing Specifications
At recommended operating conditions with XVDD_SRDS = 1.0 V ± 5%.
Parameter Symbol Min Typical Max Unit Note
Deterministic Jitter JD— — 0.17 UIp-p —
Total Jitter JT— — 0.35 UIp-p —
Unit Interval UI 799.92 800 800.08 ps 1
VOD fall time (80%–20%) tfall 50 — 120 ps —
VOD rise time (20%–80%) trise 50 — 120 ps —
Note:
1. Each UI is 800 ps ± 100 ppm.
TX
C = CTX
Silicon
+ Package C = CTX
R = 50ΩR = 50Ω
D+ Package Pin
D– Package Pin
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 29
8.3.1.2 SGMII Receive AC Timing Specifications
This table provides the SGMII receive AC timing specifications. Source synchronous clocking is not
supported; the clock is recovered from the data.
This figure shows the SGMII receiver input compliance mask eye diagram.
Figure 10. SGMII Receiver Input Compliance Mask
Table 29. SGMII Receive AC Timing Specifications
At recommended operating conditions with XVDD_SRDS = 1.0 V ± 5%.
Parameter Symbol Min Typical Max Unit Note
Deterministic jitter tolerance JD0.37 — — UIp-p 1
Combined deterministic and random jitter tolerance JDR 0.55 — — UIp-p 1
Sinusoidal jitter tolerance JSIN 0.1 — — UIp-p 1
Total jitter tolerance JT0.65 — — UIp-p 1
Bit error ratio BER — — 10-12 ——
Unit interval UI 799.92 800 800.08 ps 2
AC-coupling capacitor CTX 5 — 200 nF 3
Notes:
1. Measured at the receiver.
2. Each UI is 800 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.
0.275 0.4 0.6 0.72501
VRX_DIFFp-p-max/2
VRX_DIFFp-p-min/2
0
–VRX_DIFFp-p-min/2
–VRX_DIFFp-p-max/2
Time (UI)
Receiver Differential Input Voltage
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
30 Freescale Semiconductor
8.3.2 AC Requirements for SGMII L1_SD_REF_CLK and L1_SD_REF_CLK
This table lists the AC timing specifications. Note that L1_SD_REF_CLK and L1_SD_REF_CLK are not
intended to be used with, and should not be clocked by, a spread spectrum clock source.
8.3.3 MII AC Timing Specifications
This section describes the MII transm it and receive AC timing specifications.
8.3.3.1 MII Transmit AC Timing Specifications
This table provides the MII trans mit AC timing specifica tions .
Table 30. L1_SD_REF_CLK and L1_SD_REF_CLK AC Requirements
Parameter/Condition Symbol Min Typical Max Unit Note
L1_SD_REF_CLK/_B reference clock cycle time
100 MHz
125 MHz
tCK_REF —
10
8
—ns1, 2
L1_SD_REF_CLK/_B rise/fall time (80%-20%) tCK_RISE/tCK_FALL ——1ns—
L1_SD_REF_CLK/_B duty cycle (@50% L1_
n
VDD)t
ck_dty 45% — 55% ps —
L1_SD_REF_CLK/_B cycle to cycle clock jitter (period
jitter)
tCKCJ — — 100 ps —
L1_SD_REF_CLK/_B phase jitter peak-to-peak.
Deviation in edge location with respect to mean edge
location.
tCKPJ –50 — 50 ps —
Notes:
1. Both options provide serial interface bit rate of 1.25 Gbps. 8 ns only applies when 125 MHz SerDes1 clock frequency is
selected during POR.
2. Tolerance of ±100 ppm.
Table 31. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
TX_CLK clock period 10 Mbps tMTX — 400 — ns
TX_CLK clock period 100 Mbps tMTX —40—ns
TX_CLK duty cycle tMTXH/tMTX 35 — 65 %
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 31
This figur e shows the MII transmit AC timing diagra m.
Figure 11. MII Transmit AC Timing Diagram
8.3.3.2 MII Receive AC Timing Specifications
This table provides the MII receive AC timing spec ifications.
TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns
TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Table 32. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
Input low voltage VIL ——0.7V
Input high voltage VIH 1.9 — — V
RX_CLK clock period 10 Mbps tMRX — 400 — ns
RX_CLK clock period 100 Mbps tMRX —40—ns
RX_CLK duty cycle tMRXH/tMRX 35 — 65 %
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns
Table 31. MII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
32 Freescale Semiconductor
This figure provides the AC test load for eTSEC.
Figure 12. eTSEC AC Test Load
This figure shows the MII receive AC timing diagr am.
Figure 13. MII Receive AC Timing Diagram
8.3.4 RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specif ication s.
RX_CLK clock rise time (20%–80%) tMRXR 1.0 — 4.0 ns
RX_CLK clock fall time (80%–20%) tMRXF 1.0 — 4.0 ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with
respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
Table 33. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter Symbol1Min Typical Max Unit Note
Data to clock output skew (at transmitter) tSKRGT –600 0 600 ps —
Data to clock input skew (at receiver) tSKRGT 1.0 — 2.8 ns 2
Clock period tRGT 7.2 8.0 8.8 ns 3
Table 32. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
Output Z0 = 50 ΩLVDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 33
This figure provides the AC test load for eTSEC.
Figure 14. eTSEC AC Test Load
Duty cycle for 1000Base-T tRGTH/tRGT 45 50 55 % 4
Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4
Rise time (20%–80%) tRGTR — — 0.75 ns —
Fall time (20%–80%) tRGTF — — 0.75 ns —
EC_GTX_CLK125 reference clock period tG12 —8.0—ns5
EC_GTX_CLK125 reference clock duty cycle
measured at 0.5 ×LV DD1
tG125H/tG125 47 — 53 % —
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being
represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between
5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.
Table 33. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter Symbol1Min Typical Max Unit Note
Output Z0 = 50 ΩLVDD/2
RL = 50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
34 Freescale Semiconductor
This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
Figure 15. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3.5 RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications .
8.3.5.1 RMII Transmit AC Timing Specifications
This table shows the RMII transmit AC timing specifications.
Table 34. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
REF_CLK clock period tRMT 15.020.025.0 ns
REF_CLK duty cycle tRMTH 35 50 65 %
REF_CLK peak-to-peak jitter tRMTJ — — 250 ps
Rise time REF_CLK (20%–80%) tRMTR 1.0 — 2.0 ns
GTX_CLK
tRGT
tRGTH
tSKRGT_TX
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
tSKRGT_RX
tSKRGT_RX
tSKRGT_TX
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 35
This figure shows the RMII transmit AC timing diagram.
Figure 16. RMII Transmit AC Timing Diagram
8.3.5.2 RMII Receive AC Timing Specifications
This table shows the RMII receive AC timing specifications.
Fall time REF_CLK (80%–20%) tRMTF 1.0 — 2.0 ns
REF_CLK to RMII data TXD[1:0], TX_EN delay tRMTDX 2.0 — 10.0 ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Table 35. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol1Min Typical Max Unit
Input low voltage at 3.3 LVDD VIL ——0.8V
Input high voltage at 3.3 LVDD VIH 2.0 — — V
REF_CLK clock period tRMR 15.0 20.0 25.0 ns
REF_CLK duty cycle tRMRH 35 50 65 %
REF_CLK peak-to-peak jitter tRMRJ — — 250 ps
Rise time REF_CLK (20%–80%) tRMRR 1.0 — 2.0 ns
Fall time REF_CLK (80%–20%) tRMRF 1.0 — 2.0 ns
Table 34. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter Symbol1Min Typical Max Unit
REF_CLK
TXD[1:0]
tRMTDX
tRMT
tRMTH
tRMTR
tRMTF
TX_EN
TX_ER
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
36 Freescale Semiconductor
This figure provides the AC test load for eTSEC.
Figure 17. eTSEC AC Test Load
This figure shows the RMII receive AC timing diagram.
Figure 18. RMII Receive AC Timing Diagram
8.4 Management Interface Electrical Characteristics
The electri cal char act er isti cs specified here apply to MII management interface signals MDIO
(management data input/outpu t) and MDC (management data clock).
This figure provides the AC test load for eTSEC.
Figure 19. eTSEC AC Test Load
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge tRMRDV 4.0 — — ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge tRMRDX 2.0 — — ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with
respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
Table 35. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol1Min Typical Max Unit
Output Z0 = 50 ΩLVDD/2
RL = 50 Ω
REF_CLK
RXD[1:0]
tRMRDX
tRMR
tRMRH
tRMRR
tRMRF
CRS_DV
RX_ER
tRMRDV
Valid Data
Output Z0 = 50 ΩLVDD/2
RL = 50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 37
8.4.1 MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 36 and Table 37.
8.4.2 MII Management AC Electrical Specifications
This table provides the MII manage ment AC timing specifications.
Table 36. MII Management DC Electrical Characteristics When Powered at 2.5 V
Parameter Conditions Symbol Min Max Unit
Supply voltage (2.5 V) — LVDD1 2.37 2.63 V
Output high voltage IOH = –1.0 mA LVDD1 = Min VOH 2.00 LVDD1 + 0.3 V
Output low voltage IOL = 1.0 mA LVDD1 = Min VOL GND – 0.3 0.40 V
Input high voltage — LVDD1 = Min VIH 1.7 — V
Input low voltage — LVDD1 = Min VIL –0.3 0.70 V
Input high current VIN = LVDD1 IIH —20μA
Input low current VIN = LVDD1 IIL –15 — μA
Table 37. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter Conditions Symbol Min Max Unit
Supply voltage (3.3 V) — LVDD1 3.135 3.465 V
Output high voltage IOH = –1.0 mA LVDD1 = Min VOH 2.10 LVDD1 +0.3 V
Output low voltage IOL = 1.0 mA LVDD1 = Min VOL GND 0.50 V
Input high voltage — VIH 2.00 — V
Input low voltage — VIL —0.80V
Input high current LVDD1 = Max VIN 1 = 2.1 V IIH —30μA
Input low current LVDD1 = Max VIN = 0.5 V IIL –600 — μA
Table 38. MII Management AC Timing Specifications
Parameter Symbol1Min Typical Max Unit Note
MDC frequency fMDC —2.5—MHz2
MDC period tMDC 80 — 400 ns —
MDC clock pulse width high tMDCH 32 — — ns —
MDC to MDIO valid tMDKHDV 2 × (tplb_clk × 8) — — ns 4
MDC to MDIO delay tMDKHDX 10 — 2 × (tplb_clk × 8) ns 2, 4
MDIO to MDC setup time tMDDVKH 5——ns—
MDIO to MDC hold time tMDDXKH 0——ns—
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
38 Freescale Semiconductor
This figure shows the MII management AC timing diagram.
Figure 20. MII Management Interface Timing Diagram
9USB
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
MDC rise time (20%–80%) tMDCR ——10ns3
MDC fall time (80%–20%) tMDCF ——10ns3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed.
3. Guaranteed by design.
4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
Table 38. MII Management AC Timing Specifications (continued)
Parameter Symbol1Min Typical Max Unit Note
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
MDIO
(Input)
(Output)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 39
9.1 USB DC Electrical Characteristics
This table provides the DC electri cal chara ct er istics for the ULPI interface at recommended
OVDD = 3.3 V ± 165 mV.
9.2 USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 39. USB DC Electrical Characteristics
Parameter Symbol Min Max Unit Note
High-level input voltage VIH 2OV
DD + 0.3 V 1
Low-level input voltage VIL –0.3 0.8 V 1
Input current IIN —±30μA2
High-level output voltage, IOH = –100 μAV
OH OVDD – 0.2 — V —
Low-level output voltage, IOL = 100 μAV
OL —0.2V—
Notes:
1. The minimum VIL and maximum VIH values are based on the respective minimum and maximum OVIN values found in
Table 3.
2. The symbol OVIN represents the input voltage of the supply and is referenced in Table 3.
Table 40. USB General Timing Parameters (ULPI Mode Only)
Parameter Symbol 1 Min Max Unit Note
USB clock cycle time tUSCK 15 — ns 2, 3, 4, 5
Input setup to USB clock—all inputs tUSIVKH 4 — ns 2, 3, 4, 5
Input hold to USB clock—all inputs tUSIXKH 1 — ns 2, 3, 4, 5
USB clock to output valid—all outputs tUSKHOV — 7 ns 2, 3, 4, 5
Output hold from USB clock—all outputs tUSKHOX 2 — ns 2, 3, 4, 5
Notes:
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US)
for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to the USB clock, USBDR_CLK.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 ×OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
40 Freescale Semiconductor
These two figures provide the AC test load and signals for the USB, respectively.
Figure 21. USB AC Test Load
Figure 22. USB Interface Timing Diagram
10 Local Bus
This section descr ibes t he DC and AC electrical specif i cati ons for the local bus interf ace of the chi p.
10.1 Local Bus DC Electrical Characteristics
This tables provide the DC electr ical chara ct er isti cs for the local bus interface.
Table 41. Local Bus DC Electrical Characteristics (LBVDD =3.3V)
At recommended operating conditions with LBVDD = 3.3 V.
Parameter Conditions Symbol Min Max Unit
Supply voltage 3.3 V — LBVDD 3.135 3.465 V
Output high voltage IOH = –4.0 mA LBVDD = Min VOH 2.40 — V
Output low voltage IOL = 4.0 mA LBVDD = Min VOL —0.50 V
Input high voltage — — VIH 2.0 LBVDD + 0.3 V
Input low voltage — — VIL –0.3 0.90 V
Input high current VIN 1 = LBVDD IIH —30μA
Input low current VIN 1 = GND IIL –30 — μA
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
Output Signals
tUSKHOV
USBDR_CLK
Input Signals
tUSIXKH
tUSIVKH
tUSKHOX
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 41
10.2 Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device when in PLL
enable mode.
Table 42. Local Bus DC Electrical Characteristics (LBVDD =2.5V)
At recommended operating conditions with LBVDD = 2.5 V.
Parameter Conditions Symbol Min Max Unit
Supply voltage 2.5 V — LBVDD 2.37 2.73 V
Output high voltage IOH = –1.0 mA LBVDD = Min VOH 2.00 — V
Output low voltage IOL = 1.0 mA LBVDD = Min VOL —0.40V
Input high voltage — LBVDD = Min VIH 1.7 LBVDD + 0.3 V
Input low voltage — LBVDD = Min VIL –0.3 0.70 V
Input high current VIN 1 = LBVDD IIH —20μA
Input low current VIN 1 = GND IIL –20 — μA
Table 43. Local Bus DC Electrical Characteristics (LBVDD =1.8V)
At recommended operating conditions with LBVDD = 1.8 V.
Parameter Conditions Symbol Min Max Unit
Supply voltage 1.8 V — LBVDD 1.71 1.89 V
Output high voltage IOH = –1.0 mA LBVDD = Min VOH LBVDD – 0.45 — V
Output low voltage IOL = 1.0 mA LBVDD = Min VOL —0.45V
Input high voltage — LBVDD = Min VIH 0.65 × LBVDD LBVDD + 0.3 V
Input low voltage — LBVDD = Min VIL –0.3 0.35 × LBVDD V
Input high current VIN 1 = LBVDD IIH —10μA
Input low current VIN 1 = GND IIL –10 — μA
Table 44. Local Bus General Timing Parameters—PLL Enable Mode
Parameter Symbol1Min Max Unit Note
Local bus cycle time tLBK 7.5 15 ns 2
Input setup to local bus clock (except LUPWAIT/LGTA)t
LBIVKH 1.5 — ns 3, 4
Input hold from local bus clock tLBIXKH 1.0 — ns 3, 4
LUPWAIT/LGTA input setup to local bus clock tLBIVKH1 1.5 — ns 3, 4
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 — ns 5
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3—ns6
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 — ns 7
Local bus clock to LALE rise tLBKHLR —4.5ns —
Local bus clock to output valid (except LALE) tLBKHOV —4.5ns 3
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
42 Freescale Semiconductor
Local bus clock to output high impedance for LAD/LDP tLBKHOZ — 3.8 ns 3, 8
Output hold from local bus clock for LAD/LDP tLBKHOX 1—ns3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN at LBVDD/2 and the 0.4 ×LBVDD of the signal in question.
3. All signals are measured from LBVDD/2 of the rising/falling edge of LSYNC_IN to 0.5 ×LBVDD of the signal in question.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load
on LAD output pins.
7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Table 44. Local Bus General Timing Parameters—PLL Enable Mode (continued)
Parameter Symbol1Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 43
This table describes the general timing parameters of the local bus interface of the device when in PLL
bypass mode.
This figure provides the AC test load for the local bus.
Figure 23. Local Bus AC Test Load
Table 45. Local Bus General Timing Parameters—PLL Bypass Mode
Parameter Symbol1Min Max Unit Note
Local bus cycle time tLBK 15 — ns 2
Input setup to local bus clock tLBIVKH 7.0 — ns 3, 4
Input hold from local bus clock tLBIXKH 1.0 — ns 3, 4
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT1 1.5 — ns 5
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT2 3.0 — ns 6
LALE output fall to LAD output transition (LATCH hold time) tLBOTOT3 2.5 — ns 7
Local bus clock to LALE rise tLBKHLR —4.5ns —
Local bus clock to output valid tLBKHOV —3.0ns 3
Local bus clock to output high impedance for LAD/LDP tLBKHOZ — 4.0 ns 3, 8
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from LBVDD/2 of the rising/falling edge of LCLK0 to 0.4 ×LBVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load
on LAD output pins.
7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
44 Freescale Semiconductor
This figures show the local bus signals.
Figure 24. Local Bus Signals, Non-special Signals Only (PLL Enable Mode)
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LSYNC_IN
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
LALE
tLBIXKH
tLBIVKH
tLBKHOX
tLBKHOZ
tLBKHLR tLBOTOT
tLBKHOX
tLBKHOV
tLBKHOX
tLBKHOZ
tLBKHOV
tLBKHOV
Input Signal:
LGTA
tLBIXKH
tLBIVKH
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 45
Figure 25. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode)
LCLK[n]
Input Signals:
LAD[0:31]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
tLBIVKH
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
LALE
tLBKHOZ
tLBKHLR tLBOTOT
tLBKHOZ
tLBKHOV
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
46 Freescale Semiconductor
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode)
LSYNC_IN
UPM Mode Input Signal:
LUPWAIT
T1
T3
Input Signals:
LAD[0:31]/LDP[0:3]
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBKHOV
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
tLBKHOX
tLBKHOV
tLBKHOV
tLBKHOX
tLBKHOZ
tLBKHOX
tLBKHOZ
tLBKHOX
tLBIXKH
tLBIVKH
tLBIVKH
tLBIXKH
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 47
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Bypass Mode)
LCLK
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
tLBIVKH
tLBIXKH
T1
T3
Input Signals:
LAD[0:31]/LDP[0:3]
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBKHOV
tLBKHOZ
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
tLBKHOZ
tLBKHOZ
tLBKHOV
tLBKHOV
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
48 Freescale Semiconductor
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode)
LSYNC_IN
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
tLBIVKH
tLBIXKH
T1
T3
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBKHOV
tLBKHOZ
T2
T4
Input Signals:
LAD[0:31]
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
tLBKHOX
tLBKHOZ
tLBKHOZ
tLBKHOX
tLBKHOV
tLBKHOV
tLBKHOX
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 49
Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Bypass Mode)
11 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the
chip.
The eSDHC controlle r always uses the falling edge of the SD_CLK in order to drive the
SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-
and high-speed modes.
Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed
mode, data is driven at the rising edge of the clock.
LCLK
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
tLBIVKH
tLBIXKH
T1
T3
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBKHOV
tLBKHOZ
T2
T4
Input Signals:
LAD[0:31]
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
tLBKHOZ
tLBKHOZ
tLBKHOV
tLBKHOV
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
50 Freescale Semiconductor
Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals
propagation delay on the user board. The constraints are for minimum and maximum delays, as wel l as
skew between the CLK and DAT/ CMD signals.
In full speed mode, there is no need to add special delay on the data or clock signals. The user should make
sure to meet the timing requirements as described further within this document.
If the system is designed to support both high-speed and full-speed cards, the high-speed constraints
should be fulfilled. If the systems is designed to operate up to 25 MHz only, full-speed mode is
recommended.
11.1 eSDHC DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.
11.2 eSDHC AC Timing Specifications (Full-Speed Mode)
This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.
This table provid es the eSDHC AC timing s pecifications for full -speed mode as defined in Figure 31 and
Figure 32.
Table 46. eSDHC interface DC Electrical Characteristics
Parameter Symbol Condition Min Max Unit
Input high voltage VIH — 0.625 × OVDD OVDD +0.3 V
Input low voltage VIL — –0.3 0.25 × OVDD V
Input current IIN ——±30μA
Output high voltage VOH IOH = –100 uA,
at OVDD(min)
0.75 × OVDD —V
Output low voltage VOL IOL = +100 uA,
at OVDD(min)
— 0.125 × OVDD V
Table 47. eSDHC AC Timing Specifications for Full-Speed Mode
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter Symbol1Min Max Unit Note
SD_CLK clock frequency—full speed mode fSFSCK 025MHz—
SD_CLK clock cycle tSFSCK 40 — ns —
SD_CLK clock frequency—identification mode fSIDCK 0400KHz—
SD_CLK clock low time tSFSCKL 15 — ns 2
SD_CLK clock high time tSFSCKH 15 — ns 2
SD_CLK clock rise and fall times tSFSCKR/
tSFSCKF
—5ns2
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSFSIVKH 5—ns2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 51
This figure provi des the eSDHC clock input timing diagram.
Figure 30. eSDHC Clock Input Timing Diagram
Input hold times: SD_CMD, SD_DAT
x
, SD_CD to
SD_CLK
tSFSIXKH 0—ns2
SD_CLK delay within device tINT_CLK_DLY 1.5 — ns 4
Output valid: SD_CLK to SD_CMD, SD_DAT
x
valid tSFSKHOV —4ns2
Output hold: SD_CLK to SD_CMD, SD_DAT
x
valid tSFSKHOX 0———
SD card input setup tISU 5—ns3
SD card input hold tIH 5—ns3
SD card output valid tODLY —14ns3
SD card output hold tOH 0—ns3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)
going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with
respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Measured at capacitive load of 40 pF.
3. For reference only, according to the SD card specifications.
4. Average, for reference only.
Table 47. eSDHC AC Timing Specifications for Full-Speed Mode (continued)
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter Symbol1Min Max Unit Note
eSDHC
tSFSCKR
External Clock VMVMVM
tSFSCK
tSFSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode tSFSCKL tSFSCKH
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
52 Freescale Semiconductor
11.2.1 Full-Speed Output Path (Write)
This figure provides the data and comm and output timing diagram.
Figure 31. Full Speed Output Path
11.2.1.1 Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
No clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL Eqn. 1
With clock delay:
tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY Eqn. 2
tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY
–
tISU
–
tSFSKHOV Eqn. 3
This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL =20ns:
tDATA_DELAY + 20 < 40 + tCLK_DELAY – 5 – 4
tDATA_DELAY < 11 + t CLK_DELAY
11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY
–
tIH Eqn. 4
Input at the
MPC8378E pins
SD CLK at the
MPC8378E pin
Output valid time: tSFSKHOV
Output hold time: tSFSKHOX
tIH (5 ns)
tCLK_DELAY
SD CLK at
Driving
Edge
Sampling
edge
the card pin
tISU (5 ns)
tDATA_DELAY
tSFSCKL
tSFSCK (clock cycle)
Output from the
MPC8378E Pins
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 53
tCLK_DELAY + tIH
–
tSFSKHOX < tSFSCKL+ tDATA_DELAY Eqn. 5
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
tSFSCLKL =20ns:
tCLK_DELAY + 5 – 0 < 20 + tDATA_DELAY
tCLK_DELAY < 15 + tDATA_DELAY
11.2.1.3 Full-Speed Write Combined Formula
The following equation is the combined formula to cal culate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tIH
–
tSFSKHOX < tSFSCKL + tDATA_DELAY < tSFSCK+ tCLK_DELAY
–
tISU
–
tSFSKHOV Eqn. 6
11.2.2 Full-Speed Input Path (Read)
This figure provi des the data and command input timing diagram.
Figure 32. Full Speed Input Path
11.2.2.1 Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSFSIVKH < tSFSCK Eqn. 7
tCLK_DELAY + tDATA_DELAY < tSFSCK
–
tODLY
–
tSFSIVKH
–
tINT_CLK_DLY Eqn. 8
tCLK_DELAY
Output from the
SD CLK at
the card pin
SD card pins
tSFSIVKH
tSFSIXKH
Driving
edge
Sampling
edge
tOH
tDATA_DELAY
tODLY
tSFSCK (clock cycle)
(MPC8378E input hold)
SD CLK at the
MPC8378E pin
Input at the
MPC8378E pins
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
54 Freescale Semiconductor
11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay)
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH Eqn. 9
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3 eSDHC AC Timing Specifications (High-Speed Mode)
This table provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 34 and
Figure 35.
Table 48. eSDHC AC Timing Specifications for High-Speed Mode
At recommended operating conditions OVDD = 3.3 V ± 165 mV.
Parameter Symbol1Min Max Unit Note
SD_CLK clock frequency—high speed mode fSHSCK 050MHz—
SD_CLK clock cycle tSHSCK 20 — ns —
SD_CLK clock frequency—identification mode fSIDCK 0400KHz—
SD_CLK clock low time tSHSCKL 7—ns2
SD_CLK clock high time tSHSCKH 7—ns2
SD_CLK clock rise and fall times tSHSCKR/
tSHSCKF
—3ns2
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH 5—ns2
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 0—ns2
Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV —4ns2
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid tSHSKHOX 0—ns2
SD_CLK delay within device tINT_CLK_DLY 1.5 — ns 4
SD Card Input Setup tISU 6—ns3
SD Card Input Hold tIH 2—ns3
SD Card Output Valid tODLY —14ns3
SD Card Output Hold tOH 2.5 — ns 3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)
going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with
respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Measured at capacitive load of 40 pF.
3. For reference only, according to the SD card specifications.
4. Average, for reference only.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 55
This figure provi des the eSDHC clock input timing diagram.
Figure 33. eSDHC Clock Input Timing Diagram
11.3.1 High-Speed Output Path (Write)
This figure provides the data and comm and output timing diagram.
Figure 34. High Speed Output Path
11.3.1.1 High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
Zero clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL Eqn. 10
With clock delay:
tSHSKHOV + tDATA_DELAY + tISU < tSHSCKL + tCLK_DELAY Eqn. 11
tDATA_DELAY
–
tCLK_DELAY < tSHSCKL
–
tISU
–
tSHSKHOV Eqn. 12
eSDHC
tSHSCKR
External Clock VMVMVM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode tSHSCKL tSHSCKH
Output valid time: tSHSKHOV
Output hold time: tSHSKHOX
tIH (2 ns)
tCLK_DELAY
Input at the
SD CLK at
Driving
Edge
Sampling
edge
the card Pin
SD card pins
tISU (6 ns)
tDATA_DELAY
tSHSCKL
tSHSCK (clock cycle)
SD CLK at the
MPC8378E pin
Output from the
MPC8378E pins
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
56 Freescale Semiconductor
This means that data delay should be equal or less than the clock delay in the ideal case where
tSHSCLKL =10ns:
tDATA_DELAY – tCLK_DELAY < 10 – 6 – 4
tDATA_DELAY – tCLK_DELAY < 0
11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
tCLK_DELAY < tSHSCKL + tSHSKHOX + tDATA_DELAY
–
tIH Eqn. 13
tCLK_DELAY
–
tDATA_DELAY < tSHSCKL + tSHSKHOX
–
tIH Eqn. 14
This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of
tSHSCLKL =10ns:
tCLK_DELAY – tDATA_DELAY < 10 + 0 – 2
tCLK_DELAY – tDATA_DELAY < 8
11.3.2 High-Speed Input Path (Read)
This figure provi des the data and command input timing diagram.
Figure 35. High-Speed Input Path
For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was
driven by the SD card. Since in this mode the SD card drives t he data at the rising edge of the clock, a
suf fi cient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal
tCLK_DELAY
Output from the
SD CLK at
the Card Pin
SD Card Pins
tSHSIVKH
Driving
Edge
Sampling
Edge
tOH tDATA_DELAY
tODLY
tSHSCK (Clock Cycle)
1/2 Cycle
tSHSIXKH
Right EdgeWrong Edge
(MPC8378E Input Hold)
(MPC8378E Input Setup)
Input at the
MPC8378E Pins
SD CLK at the
MPC8378E Pin
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 57
clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is us ed to sample
the data, and therefore used in the equations.
11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSHSIVKH < 1.5
×
tSHSCK Eqn. 15
tCLK_DELAY + tDATA_DELAY < 1.5
×
tSHSCK
–
tODLY
–
tSHSIVKH Eqn. 16
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cy cle:
tCLK_DELAY + tDATA_DELAY < 30 – 14 – 5
tCLK_DELAY + tDATA_DELAY < 11
11.3.2.2 High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5
×
tSHSCK < tCLK_DELAY + tDATA_DELAY + tOH
–
tSHSIXKH + tINT_CLK_DLY Eqn. 17
0.5
×
tSHSCK
–
tOH + tSHSIXKH
–
tINT_CLK_DLY < tCLK_DELAY + tDATA_DELAY Eqn. 18
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 – 2.5 + (–1.5) < t CLK_DELAY + tDATA_DELAY
6 < tCLK_DELAY + tDATA_DELAY
11.3.2.3 High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5
×
tSHSCK
–
tOH + tSHSIXKH < tCLK_DELAY + tDATA_DELAY < 1.5
×
tSHSCK
–
tODLY
–
tSHSIVKH Eqn. 19
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the chip.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
58 Freescale Semiconductor
12.1 JTAG DC Electrical Characteristics
This table provides the DC electrical c hara cteristics for the IEEE 1149.1 (JTAG) interfac e of the chip.
12.2 JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1 149.1 (JT AG) interface of the device.
This table provides the JTAG AC timing specifications as defined in Figure 37 through Figure 40.
Table 49. JTAG interface DC Electrical Characteristics
Parameter Symbol Condition Min Max Unit
Input high voltage VIH —2.5OV
DD +0.3 V
Input low voltage VIL —–0.30.8V
Input current IIN ——±30μA
Output high voltage VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Table 50. JTAG AC Timing Specifications (Independent of CLKIN) 1
Parameter Symbol2Min Max Unit Note
JTAG external clock frequency of operation fJTG 033.3MHz—
JTAG external clock cycle time t JTG 30 — ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —
JTAG external clock rise and fall times tJTGR & tJTGF 02ns—
TRST assert time tTRST 25 — ns 3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
ns
—
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
ns
—
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 59
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 36. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
Figure 37. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
Figure 38. TRST Timing Diagram
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
ns
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see
Figure 21). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect
to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
Table 50. JTAG AC Timing Specifications (Independent of CLKIN) 1 (continued)
Parameter Symbol2Min Max Unit Note
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
JTAG
tJTKHKL tJTGR
External Clock VMVMVM
tJTG tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM VM
tTRST
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
60 Freescale Semiconductor
This figure provides the boundary-scan timing diagram.
Figure 39. Boundary-Scan Timing Diagram
This figure provides the test access port timing diagram.
Figure 40. Test Access Port Timing Diagram
VM = Midpoint Voltage (OVDD/2)
VM VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDZ
tJTKLDV
Input
Data Valid
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
VM VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
TDO
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 61
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the chi p.
13.1 I2C DC Electrical Characteristics
This table provides the DC electr ical chara cter ist ics for the I2C inte rface of the chip.
13.2 I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C inter f ace of the device.
Table 51. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 165 mV.
Parameter Symbol Min Max Unit Note
Input high voltage level VIH 0.7 × OVDD OVDD + 0.3 V —
Input low voltage level VIL –0.3 0.3 × OVDD V—
Low level output voltage VOL 00.2 × OVDD V1
Output fall time from VIH(min) to VIL(max) with a bus capacitance
from 10 to 400 pF
tI2KLKV 20 + 0.1 × CB250 ns 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 050ns3
Capacitance for each I/O pin CI—10pF—
Input current
(0 V ≤ VIN ≤ OVDD)
IIN —± 30μA4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual
for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 52. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 51).
Parameter Symbol1Min Max Unit Note
SCL clock frequency fI2C 0 400 kHz —
Low period of the SCL clock tI2CL 1.3 — μs—
High period of the SCL clock tI2CH 0.6 — μs—
Setup time for a repeated START condition tI2SVKH 0.6 — μs—
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL 0.6 — μs—
Data setup time tI2DVKH 100 — ns —
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
62 Freescale Semiconductor
This figure provides the AC test load for the I2C.
Figure 41. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
Figure 42. I2C Bus AC Timing Diagram
Data hold time
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0
—
0.9
μs2, 3
Setup time for STOP condition tI2PVKH 0.6 — μs—
Bus free time between a STOP and START condition tI2KHDX 1.3 — μs—
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL 0.1 × OVDD —V—
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH 0.2 × OVDD —V—
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with
respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time.
Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid
state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 52. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 51).
Parameter Symbol1Min Max Unit Note
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
SrS
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 63
14 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the chip.
14.1 PCI DC Electrical Characteristics
This table provides the DC electri cal chara ct er istics for the PCI interf ace of the device. The DC
characteristics of the PORESET signal, which can be used as PCI RST in applicatio ns where the device is
a PCI agent, deviates from the standard PCI levels.
14.2 PCI AC Electrical Specifications
This section describes the general AC ti ming parameters of the PCI bus of the device. Note that the
PCI_CLK/PC I_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the chip
is configured as a host or agent device. CLKIN is used when the device is in host mode.
This table shows the PCI AC timing specifica tions at 66 MHz.
.
Table 53. PCI DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
High-level input voltage VOUT ≥ VOH (min) or VIH 2.0 OVDD + 0.5 V
Low-level input voltage VOUT ≤ VOL (max) VIL –0.5 0.3 × OVDD V
High-level output voltage IOH = –500 μAV
OH 0.9 × OVDD —V
Low-level output voltage IOL = 1500 μAV
OL —0.1 × OVDD V
Input current 0 V ≤ VIN ≤ OVDD IIN — ± 30 μA
Note:
• The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2.
Table 54. PCI AC Timing Specifications at 66 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 ×OVDD, VIH = 0.7 ×OVDD.
Parameter Symbol1Min Max Unit Note
Clock to output valid tPCKHOV —6.0ns2
Output hold from clock tPCKHOX 1—ns2
Clock to output high impedance tPCKHOZ —14ns2, 3
Input setup to clock tPCIVKH 3.0 — ns 2, 4
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
64 Freescale Semiconductor
This table shows the PCI AC timing specifications at 33 MHz.
Input hold from cock tPCIXKH 0.25 — ns 2, 4, 6
Output clock skew tPCKOSK —0.5ns5
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.3 Local Bus Specifications
.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the
PCI 2.3 Local Bus Specifications
.
Table 55. PCI AC Timing Specifications at 33 MHz
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OVDD, VIH = 0.7 ×OVDD.
Parameter Symbol1Min Max Unit Note
Clock to output valid tPCKHOV —11ns2
Output hold from clock tPCKHOX 2—ns2
Clock to output high impedance tPCKHOZ —14ns2, 3
Input setup to clock tPCIVKH 3.0 — ns 2, 4
Input hold from clock tPCIXKH 0.25 — ns 2, 4, 6
Output clock skew tPCKOSK —0.5ns5
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.3 Local Bus Specifications
.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the
PCI 2.3 Local Bus Specifications
.
Table 54. PCI AC Timing Specifications at 66 MHz (continued)
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 ×OVDD, VIH = 0.7 ×OVDD.
Parameter Symbol1Min Max Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 65
This figure provides the AC test load for PCI.
Figure 43. PCI AC Test Load
This figure shows the PCI input AC timing conditions.
Figure 44. PCI Input AC Timing Measurement Conditions
This figure shows the PCI output AC timing conditions.
Figure 45. PCI Output AC Timing Measurement Condition
15 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
15.1 DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
Fo r mo re in fo rm a t ion see Section 20, “High-Speed Serial Interfaces (HSSI).”
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
tPCIVKH
CLK
Input
tPCIXKH
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output
tPCKHOX
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
66 Freescale Semiconductor
15.2 AC Requirements for PCI Express SerDes Clocks
This table lists the PCI Express SerDes clock AC requirements.
15.3 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tole rance.
15.4 Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer, use the PCI Exp ress Ba se
Specification, Rev. 1.0a.
NOTE
The voltage levels of th e transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PC I Express protocol (that is, L1_nVDD = 1.0 V).
Table 56. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter Symbol Min Typical Max Unit Note
REFCLK cycle time tREF —10—ns—
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
tREFCJ — — 100 ps —
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
tREFPJ –50 — +50 ps —
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter) tCKCJ — — 100 ps —
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
tCKPJ –50 — +50 ps 2, 3
Notes:
1. All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10-12.
3. Total peak-to-peak Deterministic Jitter “JD” should be less than or equal to 50 ps.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 67
15.4.1 Differential Transmitter (Tx) Output
This table defines the specifications for the differential output at all transmitters. The parameters are
specified at the component pins.
Table 57. Differential Transmitter (Tx) Output Specifications
Parameter Conditions Symbol Min Typical Max Units Note
Unit interval Each UPETX is 400 ps ± 300
ppm. UPETX does not account
for Spread Spectrum Clock
dictated variations.
UI 399.88 400 400.12 ps 1
Differential
peak-to-peak output
voltage
VPEDPPTX = 2 × |VTX-D+ –
VTX-D-|
VTX-DIFFp-p 0.8 — 1.2 V 2
De-emphasized
differential output
voltage (ratio)
Ratio of the VPEDPPTX of the
second and following bits after
a transition divided by the
VPEDPPTX of the first bit after a
transition.
VTX-DE-RATIO –3.0 –3.5 –4.0 dB 2
Minimum Tx eye width The maximum transmitter
jitter can be derived as
TTX-MAX-JITTER = 1 –
UPEEWTX= 0.3 UI.
TTX-EYE 0.70 — — UI 2, 3
Maximum time between
the jitter median and
maximum deviation
from the median
Jitter is defined as the
measurement variation of the
crossing points (VPEDPPTX = 0
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is
measured using all edges of
the 250 consecutive UI in the
center of the 3500 UI used for
calculating the Tx UI.
TTX-EYE-MEDIAN-to-
MAX-JITTER
— — 0.15 UI 2, 3
D+/D– Tx output
rise/fall time
—T
TX-RISE, TTX-FALL 0.125 — — UI 2, 5
RMS AC peak common
mode output voltage
VPEACPCMTX = RMS(|VTXD+ –
VTXD-|/2 – VTX-CM-DC)
VTX-CM-DC = DC(avg) of
|VTX-D+ – VTX-D-|/2
VTX-CM-ACp ——20mV2
Absolute delta of DC
common mode voltage
during LO and electrical
idle
|VTX-CM-DC (during LO) –
VTX-CM-Idle-DC (During Electrical
Idle)|<=100 mV
VTX-CM-DC = DC(avg) of
|VTX-D+ – VTX-D-|/2 [LO]
VTX-CM-Idle-DC = DC(avg) of
|VTX-D+ – VTX-D-|/2 [Electrical
Idle]
VTX-CM-DC- ACTIVE-
IDLE-DELTA
0—100mV2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
68 Freescale Semiconductor
Absolute delta of DC
common mode
between D+ and D–
|VTX-CM-DC-D+ – VTX-CM-DC-D-|
≤ 25 mV
VTX-CM-DC-D+ = DC(avg) of
|VTX-D+|
VTX-CM-DC-D- = DC(avg) of
|VTX-D-|
VTX-CM-DC-LINE-
DELTA
0—25mV2
Electrical idle
differential peak output
voltage
VPEEIDPTX = |VTX-IDLE-D+
-VTX-IDLE-D-| ≤ 20 mV
VTX-IDLE-DIFFp 0—20mV2
Amount of voltage
change allowed during
receiver detection
The total amount of voltage
change that a transmitter can
apply to sense whether a low
impedance receiver is
present.
VTX-RCV-DETECT —XPADV
DD/2 600 mV 6
Tx DC common mode
voltage
The allowed DC common
mode voltage under any
conditions.
VTX-DC-CM 0XPADV
DD/2 — V 6
Tx short circuit current
limit
The total current the
transmitter can provide when
shorted to its ground
ITX-SHORT ——90mA—
Minimum time spent in
electrical idle
Minimum time a transmitter
must be in electrical idle.
Utilized by the receiver to start
looking for an electrical idle
exit after successfully
receiving an electrical idle
ordered set.
TTX-IDLE-MIN 50 — — UI —
Maximum time to
transition to a valid
electrical idle after
sending an electrical
idle ordered set
After sending an electrical idle
ordered set, the transmitter
must meet all electrical idle
specifications within this time.
This is considered a
debounce time for the
transmitter to meet electrical
idle after transitioning from
LO.
TTX-IDLE-SET-TO-IDLE ——20UI—
Maximum time to
transition to valid Tx
specifications after
leaving an electrical idle
condition
Maximum time to meet all Tx
specifications when
transitioning from electrical
idle to sending differential
data. This is considered a
debounce time for the Tx to
meet all Tx specifications after
leaving electrical idle
TTX-IDLE-TO-DIFF-DATA ——20UI—
Differential return loss Measured over 50 MHz to
1.25 GHz.
RLTX-DIFF 12 — — dB 4
Table 57. Differential Transmitter (Tx) Output Specifications (continued)
Parameter Conditions Symbol Min Typical Max Units Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 69
15.4.2 Transmitter Compliance Eye Diagrams
The Tx eye diagram in Figure 46 is specified using the passive compliance/test measurement load (se e
Figure 48) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that
must be met for the transmitt er . Both diagrams must be aligned in time using the jitter median to locate the
center of the eye diagram. The dif ferent eye diagrams diff er in voltage depending on whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relati ve to the transition bit.
Common mode return
loss
Measured over 50 MHz to
1.25 GHz.
RLTX-CM 6——dB4
DC differential Tx
impedance
Tx DC differential mode low
impedance
ZTX-DIFF-DC 80 100 120 Ω—
Transmitter DC
impedance
Required Tx D+ as well as D–
DC impedance during all
states
ZTX-DC 40 — — Ω—
Lane-to-Lane output
skew
Static skew between any two
transmitter lanes within a
single link
LTX-SKEW — — 500 +
2UI
ps —
AC coupling capacitor All transmitters should be AC
coupled. The AC coupling is
required either within the
media or within the
transmitting component itself.
CTX 75 — 200 nF —
Crosslink random
timeout
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
downstream and one
upstream port.
Tcrosslink 0—1ms7
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 48 and measured
over any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 46.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+
and D– line (that is, as measured by a vector network analyzer with 50-Ω probes, see Figure 48). Note that the series
capacitors, CTX, is optional for the return loss measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 48 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the
PCI Express Base Specifications
, Rev 1.0a.
7. See Section 4.2.6.3 of the
PCI Express Base Specifications
, Rev 1.0a.
Table 57. Differential Transmitter (Tx) Output Specifications (continued)
Parameter Conditions Symbol Min Typical Max Units Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
70 Freescale Semiconductor
The eye diagram must be valid for any 250 conse cutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
It is recommended that the r ecovered Tx UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Figure 46. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3 Differential Receiver (Rx) Input Specifications
This tabl e defines the specifications for the dif ferential input at all receivers. The parameters are specified
at the component pins.
Table 58. Differential Receiver (Rx) Input Specifications
Parameter Comments Symbol Min Typical Max Units Note
Unit interval Each UPERX is 400 ps ± 300
ppm. UPERX does not account
for Spread Spectrum Clock
dictated variations.
UI 399.88 400 400.12 ps 1
Differential peak-to-peak
output voltage
VPEDPPRX = 2 × |VRX-D+ –
VRX-D-|
VRX-DIFFp-p 0.175 — 1.200 V 2
[De-emphasized Bit]
566 mV (3 dB) >= V
TX-DIFFp-p-MIN
>= 505 mV (4 dB)
[Transition Bit]
V
TX-DIFFp-p-MIN
= 800 mV
[Transition Bit]
V
TX-DIFFp-p-MIN
= 800 mV
0.7 UI = UI – 0.3 UI(J
TX-TOTAL-MAX
)
V
TX-DIFF
= 0 mV
(D+ D– Crossing Point)
V
TX-DIFF
= 0 mV
(D+ D– Crossing Point)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 71
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
TRX-MAX-JITTER = 1 –
UPEEWRX = 0.6 UI.
TRX-EYE 0.4——UI2, 3
Maximum time between
the jitter median and
maximum deviation from
the median.
Jitter is defined as the
measurement variation of the
crossing points (VPEDPPRX = 0
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is measured
using all edges of the 250
consecutive UI in the center of
the 3500 UI used for calculating
the Tx UI.
TRX-EYE-MEDIAN-to
-MAX-JITTER
— — 0.3 UI 2, 3, 7
AC peak common mode
input voltage
VPEACPCMRX = |VRXD+ –
VRXD-|/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+
– VRX-D-|/2
VRX-CM-ACp — — 150 mV 2
Differential return loss Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at +300 mV and –300
mV, respectively.
RLRX-DIFF 10 — — dB 4
Common mode return
loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at 0 V.
RLRX-CM 6——dB4
DC differential input
impedance
RX DC differential mode
impedance.
ZRX-DIFF-DC 80 100 120 Ω5
DC Input Impedance Required RX D+ as well as D-
DC impedance (50 ± 20%
tolerance).
ZRX-DC 40 50 60 Ω2, 5
Powered down DC input
impedance
Required RX D+ as well as D–
DC impedance when the
receiver terminations do not
have power.
ZRX-HIGH-IMP-DC 200 k — — Ω6
Electrical idle detect
threshold
VPEEIDT = 2 × |VRX-D+ -VRX-D-|
Measured at the package pins
of the receiver
VRX-IDLE-DET-DIFF
p-p
65 — 175 mV —
Table 58. Differential Receiver (Rx) Input Specifications (continued)
Parameter Comments Symbol Min Typical Max Units Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
72 Freescale Semiconductor
15.5 Receiver Compliance Eye Diagrams
The Rx eye diagram in Figure 47 is specified using the passive compliance/t est me asur ement loa d (see
Figure 48) in place of any real PCI Express Rx component. In general, the minimum receiver eye diagram
measured with the compliance/test measurement load (see Figure 48) is larger than the minimum receiver
eye diagram measured over a range of systems at the input receiver of any real PCI Express component.
The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon
parasitic characteristics that c ause the real PCI Express component to vary in impedance from the
Unexpected Electrical Idle
Enter Detect Threshold
Integration Time
An unexpected electrical idle
(Vrx-diffp-p <
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
TRX-IDLE-DET-DIFF-
ENTERTIME
——10ms—
Total Skew Skew across all lanes on a link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
Symbols) at the Rx as well as
any delay differences arising
from the interconnect itself.
LRX-SKEW — — 20 ns —
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 48 should be used
as the Rx device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 47). If the
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3. A TRx-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRx-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. The receiver input impedance will result in a differential return loss greater than or equal to 10 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured
by a vector network analyzer with 50-Ω probes, see Figure 48). Note that the series capacitors, CTx, is optional for the return
loss measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.
7. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.
Table 58. Differential Receiver (Rx) Input Specifications (continued)
Parameter Comments Symbol Min Typical Max Units Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 73
compliance/test measurement load. The input rece iver eye diagram is implementation specific and is not
specified. Rx component designer should provide additional margin to adequately compensate for the
degraded minimum receiver eye diagram (shown in Figure 47) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the Rx package and
silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.
The eye diagram must be valid for any 250 conse cutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line ( that is, as measured by a Vector Network Analyzer
with 50 Ω probes—see Figure 48). Note that the serie s capacitor s,
CPEACCTX, are optional for the return loss measurement.
Figure 47. Minimum Receiver Eye Timing and Voltage Compliance Specification
V
RX-DIFFp-p-MIN
> 175 mV
0.4 UI = T
RX-EYE-MIN
V
RX-DIFF
= 0 mV
(D+ D– Crossing Point)
V
RX-DIFF
= 0 mV
(D+ D– Crossing Point)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
74 Freescale Semiconductor
15.5.1 Compliance Test and Measurement Load
The AC timing and voltag e paramete rs must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test /measurement load shown in Figure 48.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length a t the package
pin boundary. If the vendor does not explicitly state where the measurement
point is located, the measurement point is assumed to be the D+ and D–
package pins.
Figure 48. Compliance Test/Measurement Load
16 Timers
This section describes the DC and AC electrical specific ations for the timers of the chip.
16.1 Timers DC Electrical Characteristics
This table provides the DC electrical characteristics for the device timers pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 59. Timers DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
Output high voltage IOH = –6.0 mA VOH 2.4 — V
Output low voltage IOL = 6.0 mA VOL —0.5V
Output low voltage IOL = 3.2 mA VOL —0.4V
Input high voltage — VIH 2.0 OVDD + 0.3 V
Input low voltage — VIL –0.3 0.8 V
Input current 0 V ≤ VIN ≤ OVDD IIN — ± 30 μA
TX Silicon +
Package
R = 50 ΩR = 50 Ω
C = CTX
C = CTX
D+ Package Pin
D– Package Pin
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 75
16.2 Timers AC Timing Specifications
This table provides the timers input and output AC timing specifications.
This figure provides the AC test load for the tim ers.
Figure 49. Timers AC Test Load
17 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the chip.
17.1 GPIO DC Electrical Characteristics
This table provides the DC electri cal chara ct er istics for the device GPIO.
Table 60. Timers Input AC Timing Specifications1
Parameter Symbol
2Min Unit
Timers inputs—minimum pulse width tTIWID 20 ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation
Table 61. GPIO DC Electrical Characteristics
This specification applies when operating at 3.3 V ± 165 mV supply.
Parameter Condition Symbol Min Max Unit
Output high voltage IOH = –6.0 mA VOH 2.4 — V
Output low voltage IOL = 6.0 mA VOL —0.5V
Output low voltage IOL = 3.2 mA VOL —0.4V
Input high voltage — VIH 2.0 OVDD +0.3 V
Input low voltage — VIL –0.3 0.8 V
Input current 0 V ≤ VIN ≤ OVDD IIN —± 30μA
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
76 Freescale Semiconductor
17.2 GPIO AC Timing Specifications
This table provides the GPIO input and output AC timing specifications.
This figure provides the AC test load for the GPIO.
Figure 50. GPIO AC Test Load
18 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the chip.
18.1 IPIC DC Electrical Characteristics
This table provides the DC electrical characteristics for the external in terrupt pins of the chip.
Table 62. GPIO Input AC Timing Specifications
Parameter Symbol Min Unit
GPIO inputs—minimum pulse width tPIWID 20 ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
Table 63. IPIC DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.0 OVDD + 0.3 V
Input low voltage — VIL –0.3 0.8 V
Input current — IIN —±30μA
Output low voltage IOL = 6.0 mA VOL —0.5V
Output low voltage IOL = 3.2 mA VOL —0.4V
Note:
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT.
2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 77
18.2 IPIC AC Timing Specifications
This table provides the IPIC input and output AC timing specifications.
19 SPI
This section descr ibes t he DC and AC electrical specif i cati ons for the SPI of the chip.
19.1 SPI DC Electrical Characteristics
This table provides the DC electri cal ch ara cter isti cs for the device SPI.
19.2 SPI AC Timing Specifications
This table provides the SPI input and output AC timing specifications.
Table 64. IPIC Input AC Timing Specifications
Parameter Symbol Min Unit
IPIC inputs—minimum pulse width tPIWID 20 ns
Note:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
Table 65. SPI DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.0 OVDD + 0.3 V
Input low voltage — VIL –0.3 0.8 V
Input current — IIN —± 30μA
Output high voltage IOH = –8.0 mA VOH 2.4 — V
Output low voltage IOL = 8.0 mA VOL —0.5V
Output low voltage IOL = 3.2 mA VOL —0.4V
Table 66. SPI AC Timing Specifications
Parameter Symbol1Min Max Unit
SPI outputs—Master mode (internal clock) delay tNIKHOV 0.5 6 ns
SPI outputs—Slave mode (external clock) delay tNEKHOV 28ns
SPI inputs—Master mode (internal clock) input setup time tNIIVKH 4—ns
SPI inputs—Master mode (internal clock) input hold time tNIIXKH 0—ns
SPI inputs—Slave mode (external clock) input setup time tNEIVKH 4—ns
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
78 Freescale Semiconductor
This figure provides the AC test load for the SPI.
Figure 51. SPI AC Test Load
These figures represent the AC timing from Table 66. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
This figure shows the SPI timing in slave mode (external clock).
Figure 52. SPI AC Timing in Slave Mode (External Clock) Diagram
SPI inputs—Slave mode (external clock) input hold time tNEIXKH 2—ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.
Table 66. SPI AC Timing Specifications (continued)
Parameter Symbol1Min Max Unit
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
SPICLK (input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 79
This figure shows the SPI timing in master mode (internal clock).
Figure 53. SPI AC Timing in Master Mode (Internal Clock) Diagram
20 High-Speed Serial Interfaces (HSSI)
This chip fea tures two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applic ations. See Table 1 for the interfaces supported.
This section describes the common portion of SerDes DC electric al specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
20.1 Signal Terms Definition
The SerDes utilizes dif ferential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of diffe rential signals.
Figure 54 shows how the signals are define d. For illustration purpos e, only one SerDes lane is used for
description. The figure shows wavef orm for e ither a transmitte r output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
Using this waveform, the de finitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signa ling
environment.
• Si ngle -Ende d Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and
SDn_RX each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’ s
single-ended swing.
•Differential Output Voltage, VOD (or Differential Output Swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the differ ence of
the two complimentary output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive
or negative.
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
80 Freescale Semiconductor
•Differential Input Voltage, VID (or Differen tial Input Swing):
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complimentary input voltages: VSDn_RX – VSDn_RX. The VID value can be either positive or
negative.
•Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential r eceiver input s ignal
is defined as differential peak volta ge, VDIFFp = |A – B| volts.
•Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p =2×VDIFFp = 2 ×|(A – B)| volts, which is twice of differential swing in amplitude, or
twice of the diff erential peak. For example, the output diff erential peak-peak voltage can also be
calculated as VTX-DIFFp-p = 2 ×|VOD|.
• Differential W avef orm
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for
example) from the non-inverting signal (SDn_TX, for example) within a diff erential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced t o ground. Refer to Figure 63 as an example for dif ferential waveform.
• Common Mode Voltage, Vcm
The common mode voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(V
SDn_TX +V
SDn_TX)÷2=(A+B)÷2, which is the arithmetic mean of the two
complim entary output voltages within a diff ere ntial pair. In a system, the common mode voltage
may often dif fer from one component’s output to the other’s input. Sometimes it may be even
different between the receiver input and driver output circuits within the same component. It is also
referred as the DC offset in some occas ion.
Figure 54. Differential Voltage Definitions for Transmitter or Receiver
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD
n
_TX or
SD
n
_RX
SD
n
_TX or
SD
n
_RX
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Vcm = (A + B)/2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 81
To illus trate these definitions usi ng real values, consider the case of a CM L (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD ) is 500 mVp-p, which is referred as the single-ended swing for each si gnal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’ s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differ ential voltage (VDIFFp) is 500 mV. The peak-to-peak diff erential voltage (VDIFFp-p)
is 1000 mVp-p.
20.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corr esponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sec tions describe the SerDes reference clock requirements and some application
information.
20.2.1 SerDes Reference Clock Receiver Characteristics
Figure 55 shows a receiver reference diagram of the SerDes reference clocks.
• SerDes Reference Clock Recei ver Ref er ence Ci r cuit Structure
—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 55. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Dif ferential Mode and Single-ended Mode description below for further detailed requirements.
• The maximum average curr ent requir ement that also determines the common mode voltage range
— When the SerDes reference clock diff e rential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, t he
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), si nce the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V ÷50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source f rom 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
82 Freescale Semiconductor
— If the device drivi ng the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off -chip.
• The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 55. Receiver of SerDes Reference Clocks
20.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the device SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as de scribed
below.
• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
— For external DC-coupled connection, as described in Section 20.2.1, “SerDes Reference
Clock Rece ive r Charact er isti cs ,” the maximum average current requirements sets the
requirement for average volt age (common m ode voltage) t o be between 100 mV and 400 mV.
Figure 56 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC- coupli ng capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 57 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
Input
Amp
50 Ω
50 Ω
SD
n
_REF_CLK
SD
n
_REF_CLK
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 83
• Si ngle -ende d Mo de
— The reference clock can also be single-ended. The SD _REF_CLK input amplitude
(single-ended swing) must be between 400 mV and 800 mVp-p (from Vmin to Vmax) with
SDn_REF_CLK either left unconnected or tied to ground.
—The SDn_REF _CLK input average voltage mu st be betwee n 200 mV and 400 mV. Figure 58
shows the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally . For the best noise performance, the reference of the clock could be DC
or AC-coupled int o the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
Figure 56. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 57. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 58. Single-Ended Reference Clock Input DC Requirements
SD
n
_REF_CLK
SD
n
_REF_CLK
Vmax < 800 mV
Vmin > 0 V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SD
n
_REF_CLK
SD
n
_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
150
Vmin > Vcm – 400m V
fdafdVmax < Vcm + 400 mV
Vmax < Vcm + 400 mV
SD
n
_REF_CLK
SD
n
_REF_CLK
400 mV < SD
n
_REF_CLK Input Amplitude < 800 mV
0V
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
84 Freescale Semiconductor
20.2.3 Interfacing With Other Differential Signaling Levels
The following list provides information about interfacing with other differential signaling levels.
• W ith on-chip termination to SGND_SRDSn (xcorevss), the diff erential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
• Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the li mited common mode input range all owed
(100 mV to 400 mV) for DC-coupled connection.
• LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
NOTE
Figure 59 to Figure 62 below are for conceptua l reference only. Due to the
fact that clock driver chip's internal structure, output impedance, and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by the clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefor e,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the device SerDes reference clock receiver requirement
provided in this document.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 85
This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver . It
assumes that the DC levels of the clock driver chip is compati ble with device SerDes refer ence clock
input’s DC requirement.
Figure 59. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’ s common-mode voltage is higher than the device SerDes reference clock input’ s
allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS
output driver features a 50-Ω termination r esistor. It also assumes that the LVDS transmitter establi shes its
own common mode level without relying on the receiver or other external component.
Figure 60. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 61 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’ s DC levels (both common mode voltages and output swing) are incompatible with
device SerDes reference clock input’s DC requirem ent, AC-coupling has to be used. Figure 61 assumes
50 Ω
50 Ω
SD
n
_REF_CLK
SD
n
_REF_CLK
Clock Driver 100 Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
CLK_Out
HCSL CLK Driver Chip
33 Ω
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Chip
CLK_Out
50 Ω
50
Ω
SD
n
_REF_CLK
SD
n
_REF_CLK
Clock Driver 100 Ω differential PWB trace SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
CLK_Out
LVDS CLK Driver Chip
10 nF
10 nF
Chip
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
86 Freescale Semiconductor
that the LVPEC L clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL outputs
prior to AC-coupling. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver vendor’ s
requirement. R2 is used together with the SerDes reference clock receiver’s 50 Ω termination resistor to
attenuate the LVPECL output’s differential pe ak level such that it meets t he device SerDes refe renc e
clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For
example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input
amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult clock
driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock
driver chip.
Figure 61. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
50 Ω
50 Ω
SD
n
_REF_CLK
SD
n
_REF_CLK
Clock Driver 100 Ω differential PWB trace SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
CLK_Out
LVPECL CLK Driver Chip
R2
R2
R1
R1
10
nF
10
nF
Chip
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 87
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’ s DC
requirement.
Figure 62. Single-Ended Connection (Reference Only)
20.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selecte d should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. P hase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters common to SGMII and protocols
Table 67. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.
Parameter Symbol Min Max Unit Note
Rising Edge Rate Rise Edge Rate 1.0 4.0 V/ns 2, 3
Falling Edge Rate Fall Edge Rate 1.0 4.0 V/ns 2, 3
Differential Input High Voltage VIH 200 — mV 2
Differential Input Low Voltage VIL — –200 mV 2
50 Ω
50 Ω
SD
n
_REF_CLK
SD
n
_REF_CLK
100 Ω differential PWB trace SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
Chip
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
88 Freescale Semiconductor
Figure 63. Differential Measurement Points for Rise and Fall Time
Figure 64. Single-Ended Measurement Points for Rise and Fall Time Matching
Rising edge rate (SD
n
_REF_CLK) to falling edge rate
(SD
n
_REF_CLK) matching
Rise-Fall Matching — 20 % 1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD
n
_REF_CLK minus SD
n
_REF_CLK).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 63.
4. Matching applies to rising edge rate for SD
n
_REF_CLK and falling edge rate for SD
n
_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SD
n
_REF_CLK falling. The
median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of SD
n
_REF_CLK should be compared to the Fall Edge Rate of SD
n
_REF_CLK, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 64.
Table 67. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V ± 5%.
Parameter Symbol Min Max Unit Note
VIH = +200 mV
0.0 V
VIL = –200 mV
SD
n
_REF_CLK
Minus
SD
n
_REF_CLK
Rise Edge Rate Fall Edge Rate
TFA L L TRISE
SD
n
_REF_CLK
VCROSS MEDIAN
SD
n
_REF_CLK
SD
n
_REF_CLK
VCROSS MEDIAN
SD
n
_REF_CLK
VCROSS MEDIAN –100 mV
VCROSS MEDIAN +100 mV
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 89
20.3 SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 65. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in
this document based on the applicati on usage:
•Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)”
•Section 15, “PCI Express ”
Note that an external AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in specification of each protocol sect ion.
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
21.1 Package Parameters for the MPC8378E TePBGA II
The package parameters are provided in the following list. The package type is 31 mm × 31 mm,
689 plastic ball grid array (Te PBGA II ).
Package outline 31 mm × 31 mm
Interconnects 689
Pitch 1.00 mm
Module height (typical) 2.0 mm to 2.46 mm (maximum)
Solder Balls 3.5% Ag, 96.5% Sn
Ball diameter (typical) 0.60 mm
50 Ω
50 ΩReceiver
Transmitter
SD1_TX
n
or
SD2_TX
n
SD1_TX
n
or
SD2_TX
n
SD1_RX
n
or
SD2_RX
n
SD1_RX
n
or
SD2_RX
n
50
Ω
50
Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
90 Freescale Semiconductor
This figure shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II
package.
Figure 66. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II
Note:
1All dimensions are in millimeters.
2Dimensioning and tolerancing per ASME Y14. 5M-1994.
3Maximum solder ball diameter measured parallel to Datum A.
4Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 91
5Parallelism measurement should exclude any effect of mark on top surface of package.
21.2 Pinout Listings
This table provides the pinout listing for the TePBGA II package.
Table 68. TePBGA II Pinout Listing
Signal Package Pin Number Pin Type Power Supply Note
Clock Signals
CLKIN K24 I OVDD —
PCI_CLK/PCI_SYNC_IN C10 I OVDD —
PCI_SYNC_OUT N24 O OVDD 3
PCI_CLK0 L24 O OVDD —
PCI_CLK1 M24 O OVDD —
PCI_CLK2 M25 O OVDD —
PCI_CLK3 M26 O OVDD —
PCI_CLK4 L26 O OVDD —
RTC/PIT_CLOCK AF11 I OVDD —
DDR SDRAM Memory Interface
MA0 U3 O GVDD —
MA1 U1 O GVDD —
MA2 T5 O GVDD —
MA3 T3 O GVDD —
MA4 T2 O GVDD —
MA5 T1 O GVDD —
MA6 R1 O GVDD —
MA7 P2 O GVDD —
MA8 P1 O GVDD —
MA9 N4 O GVDD —
MA10 V3 O GVDD —
MA11 M5 O GVDD —
MA12 N1 O GVDD —
MA13 M2 O GVDD —
MA14 M1 O GVDD —
MBA0 U5 O GVDD —
MBA1 U4 O GVDD —
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
92 Freescale Semiconductor
MBA2 M3 O GVDD —
MCAS_B W5 O GVDD —
MCK_B0 H1 O GVDD —
MCK_B1 K1 O GVDD —
MCK_B2 V1 O GVDD —
MCK_B3 W2 O GVDD —
MCK_B4 AA1 O GVDD —
MCK_B5 AB2 O GVDD —
MCK0 J1 O GVDD —
MCK1 L1 O GVDD —
MCK2 V2 O GVDD —
MCK3 W1 O GVDD —
MCK4 Y1 O GVDD —
MCK5 AB1 O GVDD —
MCKE0 M4 O GVDD 3
MCKE1 R5 O GVDD 3
MCS_B0 W3 O GVDD —
MCS_B1 P3 O GVDD —
MCS_B2 T4 O GVDD —
MCS_B3 R4 O GVDD —
MDIC0 AH8 I/O GVDD 9
MDIC1 AJ8 I/O GVDD 9
MDM0 B6 O GVDD —
MDM1 B2 O GVDD —
MDM2 E2 O GVDD —
MDM3 E1 O GVDD —
MDM4 Y6 O GVDD —
MDM5 AC6 O GVDD —
MDM6 AE6 O GVDD —
MDM7 AJ4 O GVDD —
MDM8 L6 O GVDD —
MDQ0 A8 I/O GVDD 11
MDQ1 A6 I/O GVDD 11
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 93
MDQ2 C7 I/O GVDD 11
MDQ3 D8 I/O GVDD 11
MDQ4 A7 I/O GVDD 11
MDQ5 A5 I/O GVDD 11
MDQ6 A3 I/O GVDD 11
MDQ7 C6 I/O GVDD 11
MDQ8 D7 I/O GVDD 11
MDQ9 E8 I/O GVDD 11
MDQ10 B1 I/O GVDD 11
MDQ11 D5 I/O GVDD 11
MDQ12 B3 I/O GVDD 11
MDQ13 D6 I/O GVDD 11
MDQ14 C3 I/O GVDD 11
MDQ15 C2 I/O GVDD 11
MDQ16 D4 I/O GVDD 11
MDQ17 E6 I/O GVDD 11
MDQ18 F6 I/O GVDD 11
MDQ19 G4 I/O GVDD 11
MDQ20 F8 I/O GVDD 11
MDQ21 E4 I/O GVDD 11
MDQ22 C1 I/O GVDD 11
MDQ23 G6 I/O GVDD 11
MDQ24 F2 I/O GVDD 11
MDQ25 G5 I/O GVDD 11
MDQ26 H6 I/O GVDD 11
MDQ27 H4 I/O GVDD 11
MDQ28 D1 I/O GVDD 11
MDQ29 G3 I/O GVDD 11
MDQ30 H5 I/O GVDD 11
MDQ31 F1 I/O GVDD 11
MDQ32 W6 I/O GVDD 11
MDQ33 AC1 I/O GVDD 11
MDQ34 AC3 I/O GVDD 11
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
94 Freescale Semiconductor
MDQ35 AE1 I/O GVDD 11
MDQ36 V6 I/O GVDD 11
MDQ37 Y5 I/O GVDD 11
MDQ38 AA4 I/O GVDD 11
MDQ39 AB6 I/O GVDD 11
MDQ40 AD3 I/O GVDD 11
MDQ41 AC4 I/O GVDD 11
MDQ42 AD4 I/O GVDD 11
MDQ43 AF1 I/O GVDD 11
MDQ44 AE4 I/O GVDD 11
MDQ45 AC5 I/O GVDD 11
MDQ46 AE2 I/O GVDD 11
MDQ47 AE3 I/O GVDD 11
MDQ48 AG1 I/O GVDD 11
MDQ49 AG2 I/O GVDD 11
MDQ50 AG3 I/O GVDD 11
MDQ51 AF5 I/O GVDD 11
MDQ52 AE5 I/O GVDD 11
MDQ53 AD7 I/O GVDD 11
MDQ54 AH2 I/O GVDD 11
MDQ55 AG4 I/O GVDD 11
MDQ56 AH3 I/O GVDD 11
MDQ57 AG5 I/O GVDD 11
MDQ58 AF8 I/O GVDD 11
MDQ59 AJ5 I/O GVDD 11
MDQ60 AF6 I/O GVDD 11
MDQ61 AF7 I/O GVDD 11
MDQ62 AH6 I/O GVDD 11
MDQ63 AH7 I/O GVDD 11
MDQS0 C8 I/O GVDD 11
MDQS1 C4 I/O GVDD 11
MDQS2 E3 I/O GVDD 11
MDQS3 G2 I/O GVDD 11
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 95
MDQS4 AB5 I/O GVDD 11
MDQS5 AD1 I/O GVDD 11
MDQS6 AH1 I/O GVDD 11
MDQS7 AJ3 I/O GVDD 11
MDQS8 G1 I/O GVDD 11
MECC0/MSRCID0 J6 I/O GVDD —
MECC1/MSRCID1 J3 I/O GVDD —
MECC2/MSRCID2 K2 I/O GVDD —
MECC3/MSRCID3 K3 I/O GVDD —
MECC4/MSRCID4 J5 I/O GVDD —
MECC5/MDVAL J2 I/O GVDD —
MECC6 L5 I/O GVDD —
MECC7 L2 I/O GVDD —
MODT0 N5 O GVDD 6
MODT1 U6 O GVDD 6
MODT2 M6 O GVDD 6
MODT3 P6 O GVDD 6
MRAS_B AA3 O GVDD —
MVREF1 K4 I GVDD 11
MVREF2 W4 I GVDD 11
MWE_B Y2 O GVDD —
DUART Interface
UART_SIN1/
MSRCID2/LSRCID2
L28 I/O OVDD —
UART_SOUT1/
MSRCID0/LSRCID0
L27 O OVDD —
UART_CTS_B[1]/
MSRCID4/LSRCID4
K26 I/O OVDD —
UART_RTS_B1 N27 O OVDD —
UART_SIN2/
MSRCID3/LSRCID3
K27 I/O OVDD —
UART_SOUT2/
MSRCID1/LSRCID1
K28 O OVDD —
UART_CTS_B[2]/
MDVAL/LDVAL
K29 I/O OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
96 Freescale Semiconductor
UART_RTS_B[2] L29 O OVDD —
Enhanced Local Bus Controller (eLBC) Interface
LAD0 E24 I/O LBVDD —
LAD1 G28 I/O LBVDD —
LAD2 H25 I/O LBVDD —
LAD3 F26 I/O LBVDD —
LAD4 C26 I/O LBVDD —
LAD5 J28 I/O LBVDD —
LAD6 F21 I/O LBVDD —
LAD7 F23 I/O LBVDD —
LAD8 E25 I/O LBVDD —
LAD9 E26 I/O LBVDD —
LAD10 A23 I/O LBVDD —
LAD11 F24 I/O LBVDD —
LAD12 G24 I/O LBVDD —
LAD13 F25 I/O LBVDD —
LAD14 H28 I/O LBVDD —
LAD15 G25 I/O LBVDD —
LA11/LAD16 F27 I/O LBVDD —
LA12/LAD17 B21 I/O LBVDD —
LA13/LAD18 A25 I/O LBVDD —
LA14/LAD19 C28 I/O LBVDD —
LA15/LAD20 H24 I/O LBVDD —
LA16/LAD21 E23 I/O LBVDD —
LA17/LAD22 B28 I/O LBVDD —
LA18/LAD23 D28 I/O LBVDD —
LA19/LAD24 A27 I/O LBVDD —
LA20/LAD25 C25 I/O LBVDD —
LA21/LAD26 B27 I/O LBVDD —
LA22/LAD27 H27 I/O LBVDD —
LA23/LAD28 E21 I/O LBVDD —
LA24/LAD29 F20 I/O LBVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 97
LA25/LAD30 D29 I/O LBVDD —
LA26/LAD31 E20 I/O LBVDD —
LA27 H26 O LBVDD —
LA28 C29 O LBVDD —
LA29 E28 O LBVDD —
LA30 B26 O LBVDD —
LA31 J25 O LBVDD —
LA10/LALE H29 O LBVDD —
LBCTL A22 O LBVDD —
LCLK0 B22 O LBVDD —
LCLK1 C23 O LBVDD —
LCLK2 B23 O LBVDD —
LCS_B0 D25 O LBVDD —
LCS_B1 F19 O LBVDD —
LCS_B2 C27 O LBVDD —
LCS_B3 D24 O LBVDD —
LCS_B4/LDP0 C24 I/O LBVDD —
LCS_B5/LDP1 B29 I/O LBVDD —
LA7/LCS_B6/LDP2 E29 I/O LBVDD —
LA8/LCS_B7/LDP3 F29 I/O LBVDD —
LFCLE/LGPL0 D21 O LBVDD —
LFALE/LGPL1 A26 O LBVDD —
LFRE_B/LGPL2/LOE_B F22 O LBVDD —
LFWP_B/LGPL3 C21 O LBVDD —
LGPL4/LFRB_B/LGTA_B/
LUPWAIT/LPBSE
J29 I/O LBVDD 17
LA9/LGPL5 G29 O LBVDD —
LSYNC_IN A21 I LBVDD —
LSYNC_OUT D23 O LBVDD —
LWE_B0/LFWE0/LBS_B0 E22 O LBVDD —
LWE_B1/LFWE1/LBS_B1 B25 O LBVDD —
LWE_B2/LFWE2/LBS_B2 E27 O LBVDD —
LWE_B3/LFWE3/LBS_B3 F28 O LBVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
98 Freescale Semiconductor
eTSEC1/GPIO1/GPIO2/CFG_RESET Interface
TSEC1_COL/GPIO2[20] AF22 I/O LVDD1 17
TSEC1_CRS/GPIO2[21] AE20 I/O LVDD1 17
TSEC1_GTX_CLK AJ25 O LVDD1 17
TSEC1_RX_CLK AG22 I LVDD1 17
TSEC1_RX_DV AD19 I LVDD1 17
TSEC1_RX_ER/GPIO2[25] AD20 I/O LVDD1 17
TSEC1_RXD0 AD22 I LVDD1 17
TSEC1_RXD1 AE21 I LVDD1 17
TSEC1_RXD2 AE22 I LVDD1 17
TSEC1_RXD3 AD21 I LVDD1 17
TSEC1_TX_CLK AJ22 I LVDD1 17
TSEC1_TX_EN AG23 O LVDD1 17
TSEC1_TX_ER/CFG_LBMUX AH22 I/O LVDD1 17
TSEC1_TXD0/
CFG_RESET_SOURCE[0]
AD23 I/O LVDD1 17
TSEC1_TXD1/
CFG_RESET_SOURCE[1]
AE23 I/O LVDD1 17
TSEC1_TXD2/
CFG_RESET_SOURCE[2]
AF23 I/O LVDD1 17
TSEC1_TXD3/
CFG_RESET_SOURCE[3]
AJ24 I/O LVDD1 17
EC_GTX_CLK125 AH24 I LVDD1 17
EC_MDC/CFG_CLKIN_DIV AJ21 I/O LVDD1 17
EC_MDIO AH21 I/O LVDD1 17
eTSEC2/GPIO1 Interface
TSEC2_COL/GPIO1[21]/
TSEC1_TMR_TRIG1
AJ27 I/O LVDD2 17
TSEC2_CRS/GPIO1[22]/
TSEC1_TMR_TRIG2
AG29 I/O LVDD2 17
TSEC2_GTX_CLK AF28 O LVDD2 17
TSEC2_RX_CLK/
TSEC1_TMR_CLK
AF25 I LVDD2 17
TSEC2_RX_DV/GPIO1[23] AF26 I/O LVDD2 17
TSEC2_RX_ER/GPIO1[25] AG25 I/O LVDD2 17
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 99
TSEC2_RXD0/GPIO1[16] AE28 I/O LVDD2 17
TSEC2_RXD1/GPIO1[15] AE29 I/O LVDD2 17
TSEC2_RXD2/GPIO1[14] AH26 I/O LVDD2 17
TSEC2_RXD3/GPIO1[13] AH25 I/O LVDD2 17
TSEC2_TX_CLK/GPIO2[24]/
TSEC1_TMR_GCLK
AG28 I/O LVDD2 17
TSEC2_TX_EN/GPIO1[12]/
TSEC1_TMR_ALARM2
AJ26 I/O LVDD2 17
TSEC2_TX_ER/GPIO1[24]/
TSEC1_TMR_ALARM1
AG26 I/O LVDD2 17
TSEC2_TXD0/GPIO1[20] AH28 I/O LVDD2 17
TSEC2_TXD1/GPIO1[19]/
TSEC1_TMR_PP1
AF27 I/O LVDD2 17
TSEC2_TXD2/GPIO1[18]/
TSEC1_TMR_PP2
AJ28 I/O LVDD2 17
TSEC2_TXD3/GPIO1[17]/
TSEC1_TMR_PP3
AF29 I/O LVDD2 17
GPIO1 Interface
GPIO1[0]/GTM1_TIN1/
GTM2_TIN2/DREQ0_B
P25 I/O OVDD —
GPIO1[1]/GTM1_TGATE1_B/
GTM2_TGATE2_B/DACK0_B
N25 I/O OVDD —
GPIO1[2]/GTM1_TOUT1_B/
DDONE0_B
N26 I/O OVDD —
GPIO1[3]/GTM1_TIN2/
GTM2_TIN1/DREQ1_B
B9 I/O OVDD —
GPIO1[4]/GTM1_TGATE2_B/
GTM2_TGATE1_B/DACK1_B
N29 I/O OVDD —
GPIO1[5]/GTM1_TOUT2_B/
GTM2_TOUT1_B/DDONE1_B
M29 I/O OVDD —
GPIO1[6]/GTM1_TIN3/
GTM2_TIN4/DREQ2_B
A9 I/O OVDD —
GPIO1[7]/GTM1_TGATE3_B/
GTM2_TGATE4_B/DACK2_B
B10 I/O OVDD —
GPIO1[8]/GTM1_TOUT3_B/
DDONE2_B
J26 I/O OVDD —
GPIO1[9]/GTM1_TIN4/
GTM2_TIN3/DREQ3_B
J24 I/O OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
100 Freescale Semiconductor
GPIO1[10]/GTM1_TGATE4_B/
GTM2_TGATE3_B/DACK3_B
J27 I/O OVDD —
GPIO1[11]/GTM1_TOUT4_B/
GTM2_TOUT3_B/DDONE3_B
P24 I/O OVDD —
USB/GPIO2 Interface
USBDR_CLK/GPIO2[23] AJ11 I/O OVDD —
USBDR_DIR_DPPULLUP/
GPIO2[9]
AG12 I/O OVDD —
USBDR_NXT/GPIO2[8] AJ10 I/O OVDD —
USBDR_PCTL0/GPIO2[11]/
SD_DAT2
AF10 I/O OVDD —
USBDR_PCTL1/GPIO2[22]/
SD_DAT3
AE9 I/O OVDD —
USBDR_PWRFAULT/
GPIO2[10]/SD_DAT1
AG13 I/O OVDD —
USBDR_STP_SUSPEND AH12 O OVDD 12
USBDR_D0_ENABLEN/
GPIO2[0]
AG10 I/O OVDD —
USBDR_D1_SER_TXD/
GPIO2[1]
AF13 I/O OVDD —
USBDR_D2_VMO_SE0/
GPIO2[2]
AG11 I/O OVDD —
USBDR_D3_SPEED/GPIO2[3] AH11 I/O OVDD —
USBDR_D4_DP/GPIO2[4] AG9 I/O OVDD —
USBDR_D5_DM/GPIO2[5] AF9 I/O OVDD —
USBDR_D6_SER_RCV/
GPIO2[6]
AH13 I/O OVDD —
USBDR_D7_DRVVBUS/
GPIO2[7]
AH10 I/O OVDD —
I2C Interface
IIC1_SCL C12 I/O OVDD 2
IIC1_SDA B12 I/O OVDD 2
IIC2_SCL A10 I/O OVDD 2
IIC2_SDA A12 I/O OVDD 2
JTAG Interface
TCK B13 I OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 101
TDI E14 I OVDD 4
TDO C13 O OVDD 3
TMS A13 I OVDD 4
TRST_B E11 I OVDD 4
PCI Signals
PCI_AD0 P26 I/O OVDD —
PCI_AD1 N28 I/O OVDD —
PCI_AD2 P29 I/O OVDD —
PCI_AD3 P27 I/O OVDD —
PCI_AD4 R26 I/O OVDD —
PCI_AD5 R29 I/O OVDD —
PCI_AD6 T24 I/O OVDD —
PCI_AD7 T25 I/O OVDD —
PCI_AD8 R27 I/O OVDD —
PCI_AD9 P28 I/O OVDD —
PCI_AD10 U25 I/O OVDD —
PCI_AD11 R28 I/O OVDD —
PCI_AD12 U26 I/O OVDD —
PCI_AD13 U24 I/O OVDD —
PCI_AD14 T29 I/O OVDD —
PCI_AD15 V24 I/O OVDD —
PCI_AD16 Y26 I/O OVDD —
PCI_AD17 V28 I/O OVDD —
PCI_AD18 AA25 I/O OVDD —
PCI_AD19 AA26 I/O OVDD —
PCI_AD20 W29 I/O OVDD —
PCI_AD21 AA24 I/O OVDD —
PCI_AD22 AA27 I/O OVDD —
PCI_AD23 AC26 I/O OVDD —
PCI_AD24 AB25 I/O OVDD —
PCI_AD25 AB24 I/O OVDD —
PCI_AD26 AA28 I/O OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
102 Freescale Semiconductor
PCI_AD27 AA29 I/O OVDD —
PCI_AD28 AC24 I/O OVDD —
PCI_AD29 AC25 I/O OVDD —
PCI_AD30 AB28 I/O OVDD —
PCI_AD31 AE24 I/O OVDD —
PCI_C_BE_B0 T26 I/O OVDD —
PCI_C_BE_B1 T28 I/O OVDD —
PCI_C_BE_B2 V29 I/O OVDD —
PCI_C_BE_B3 Y29 I/O OVDD —
PCI_DEVSEL_B U28 I/O OVDD 5
PCI_FRAME_B V27 I/O OVDD —
PCI_GNT_B0 AE27 I/O OVDD —
PCI_GNT_B[1]/
CPCI_HS_LED
AC28 O OVDD —
PCI_GNT_B[2]/
CPCI_HS_ENUM
AD27 O OVDD —
PCI_GNT_B[3]/PCI_PME AC27 O OVDD —
PCI_GNT_B[4] AE25 O OVDD —
PCI_IDSEL W28 I OVDD 5
PCI_INTA_B/IRQ_OUT_B AD29 O OVDD 2
PCI_IRDY_B U29 I/O OVDD 5
PCI_PAR V25 I/O OVDD —
PCI_PERR_B Y25 I/O OVDD 5
PCI_REQ_B0 AE26 I/O OVDD —
PCI_REQ_B[1]/CPCI_HS_ES AC29 I OVDD —
PCI_REQ_B2 AB29 I OVDD —
PCI_REQ_B3 AD26 I OVDD —
PCI_REQ_B4 W27 I OVDD —
PCI_RESET_OUT_B AD28 O OVDD —
PCI_SERR_B V26 I/O OVDD 5
PCI_STOP_B W26 I/O OVDD 5
PCI_TRDY_B Y24 I/O OVDD 5
M66EN AD15 I OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 103
Programmable Interrupt Controller (PIC) Interface
MCP_OUT_B AD14 O OVDD 2
IRQ_B0/MCP_IN_B/GPIO2[12] F9 I/O OVDD —
IRQ_B1/GPIO2[13] E9 I/O OVDD —
IRQ_B2/GPIO2[14] F10 I/O OVDD —
IRQ_B3/GPIO2[15] D9 I/O OVDD —
IRQ_B4/GPIO2[16]/SD_WP C9 I/O OVDD —
IRQ_B5/GPIO2[17]/
USBDR_PWRFAULT
AE10 I/O OVDD —
IRQ_B6/GPIO2[18] AD10 I/O OVDD —
IRQ_B7/GPIO2[19] AD9 I/O OVDD —
PMC Interface
QUIESCE_B D13 O OVDD —
SerDes1 Interface
L1_SD_IMP_CAL_RX AJ14 I L1_XPADVDD —
L1_SD_IMP_CAL_TX AG19 I L1_XPADVDD —
L1_SD_REF_CLK AJ17 I L1_XPADVDD —
L1_SD_REF_CLK_B AH17 I L1_XPADVDD —
L1_SD_RXA_N AJ15 I L1_XPADVDD —
L1_SD_RXA_P AH15 I L1_XPADVDD —
L1_SD_RXE_N AJ19 I L1_XPADVDD —
L1_SD_RXE_P AH19 I L1_XPADVDD —
L1_SD_TXA_N AF15 O L1_XPADVDD —
L1_SD_TXA_P AE15 O L1_XPADVDD —
L1_SD_TXE_N AF18 O L1_XPADVDD —
L1_SD_TXE_P AE18 O L1_XPADVDD —
L1_SDAVDD_0 AJ18 SerDes PLL
Power
(1.0 or 1.05 V)
——
L1_SDAVSS_0 AG17 SerDes PLL
GND
——
L1_XCOREVDD AH14, AJ16, AF17, AH20, AJ20 SerDes Core
Power
(1.0 or 1.05 V)
——
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
104 Freescale Semiconductor
L1_XCOREVSS AG14, AG15, AG16, AH16, AG18, AG20 SerDes Core
GND
——
L1_XPADVDD AE16, AF16, AD18, AE19, AF19 SerDes I/O
Power (1.0 or
1.05 V)
——
L1_XPADVSS AF14, AE17, AF20 SerDes I/O
GND
——
SerDes2 Interface
L2_SD_IMP_CAL_RX C19 I L2_XPADVDD —
L2_SD_IMP_CAL_TX C15 I L2_XPADVDD —
L2_SD_REF_CLK B17 I L2_XPADVDD —
L2_SD_REF_CLK_B A17 I L2_XPADVDD —
L2_SD_RXA_N A19 I L2_XPADVDD —
L2_SD_RXA_P B19 I L2_XPADVDD —
L2_SD_RXE_N A15 I L2_XPADVDD —
L2_SD_RXE_P B15 I L2_XPADVDD —
L2_SD_TXA_N D18 O L2_XPADVDD —
L2_SD_TXA_P E18 O L2_XPADVDD —
L2_SD_TXE_N D15 O L2_XPADVDD —
L2_SD_TXE_P E15 O L2_XPADVDD —
L2_SDAVDD_0 A16 SerDes PLL
Power
(1.0 or 1.05 V)
——
L2_SDAVSS_0 C17 SerDes PLL
GND
——
L2_XCOREVDD A14, B14, D17, B18, B20 SerDes Core
Power
(1.0 or 1.05 V)
——
L2_XCOREVSS C14, C16, A18, C18, A20, C20 SerDes Core
GND
——
L2_XPADVDD D14, E16, F18, D19, E19 SerDes I/O
Power (1.0 or
1.05 V)
——
L2_XPADVSS D16, E17, D20 SerDes I/O
GND
——
SPI Interface
SPICLK/SD_CLK AH9 I/O OVDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 105
SPIMISO/SD_DAT0 AD11 I/O OVDD —
SPIMOSI/SD_CMD AJ9 I/O OVDD —
SPISEL_B/SD_CD AE11 I OVDD —
System Control Interface
SRESET_B AD12 I/O OVDD 2
HRESET_B AE12 I/O OVDD 1
PORESET_B AE14 I OVDD —
Test Interface
TEST E10 I OVDD 10
TEST_SEL0 D10 I — 13
TEST_SEL1 D12 I OVDD 14
Thermal Management
Reserved F15 I — 15
Power Supply Signals
LVDD1 AC21, AG21, AH23 Power for
eTSEC 1 I/O
(2.5 V, 3.3 V)
LVDD1 —
LVDD2 AG24, AH27, AH29 Power for
eTSEC 2 I/O
(2.5 V, 3.3 V)
LVDD2 —
LBVDD G20, D22, A24, G26, D27, A28 Power for eLBC
(3.3, 2.5, or
1.8 V)
LBVDD —
VDD K10, L10, M10, N10, P10, R10, T10, U10,
V10, W10, Y10, K11, R11, Y11, K12, Y12,
K13, Y13, K14, Y14, K15, L15, W15, Y15,
K16, Y16, K17, Y17, K18, Y18, K19, R19,
Y19, K20, L20, M20, N20, P20, R20, T20,
U20, V20, W20, Y20
Power for Core
(1.0 V or 1.5 V)
VDD —
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
106 Freescale Semiconductor
GND
(VSS)A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3, A4,
F4, J4, L4, V4, Y4, AB4, B5, E5, P5, AH5, K6,
T6, AA6, AD6, AG6, F7, J7, Y7, AJ7, B8,
AE8, AG8, G9, AC9, B11, D11, F11, L11,
M11, N11, P11, T11, U11, V11, W11,L12,
M12, N12, P12, R12, T12, U12, V12, W12,
E12, E13, L13, M13, N13, P13, R13, T13,
U13, V13, W13, AE13, AJ13, F14, L14, M14,
N14, P14, R14, T14, U14, V14, W14, M15,
N15, P15, R15, T15, U15, V15, L16, M16,
N16, P16, R16, T16, U16, V16, W16, L17,
M17, N17, P17, R17, T17, U17, V17, W17,
L18, M18, N18, P18, R18, T18, U18, V18,
W18, L19, M19, N19, P19, T19, U19, V19,
W19, AC20, G21, AF21, C22, J23, AA23,
AJ23, B24, W24, AF24, K25, R25, AD25,
D26, G27, M27, T27, Y27, AB27, AG27, A29,
AJ29
———
AVDD_C AD13 Power for e300
core PLL (1.0 V
or 1.05 V)
—16
AVDD_L F13 Power for eLBC
PLL (1.0 V or
1.05 V)
—16
AVDD_P F12 Power for
system PLL
(1.0 V or 1.05 V)
—16
GVDD A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3,
N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5,
V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7,
AE7, AG7, AD8
Power for DDR
SDRAM I/O
Voltage (2.5 or
1.8 V)
GVDD —
OVDD AC10, AF12, AJ12, K23, Y23, R24, AD24,
L25, W25, AB26, U27, M28, Y28, G10, A11,
C11
PCI, USB, and
other Standard
(3.3 V)
OVDD —
No Connect
NC F16, F17, AD16, AD17 — — 8
Pull Down
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 107
Pull Down B16, AH18 — — 7
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being released to high impedance during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, “MPC837xE Design Checklist,” for more details.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND using a 0 Ω resistor.
8. This pin must always be left not connected.
9. For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR
power using an 18.2 Ω resistor.
10.This pin must always be tied low. If it is left floating it may cause the device to malfunction.
11.See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
12.This pin must not be pulled down during PORESET.
13.This pin must always be tied to GND.
14.This pin must always be tied to OVDD.
15.Open or tie to GND.
16.Voltage settings are dependent on the frequency used; see Ta b le 3 .
17.See AN3665, “MPC837xE Design Checklist,” for proper termination.
Table 68. TePBGA II Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
108 Freescale Semiconductor
22 Clocking
This figure shows the internal distribution of clocks within this chip.
Figure 67. Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, de pending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKI N is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CL K_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow t he device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PC I agent device the CLKIN signal should be tied to GND.
Core PLL
System PLL
DDR
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MCK[0:5]
MCK[0:5]
core_clk
e300 core
csb_clk
to rest
CLKIN
csb_clk
6
6
DDR
Memory
Local Bus
PCI_CLK[0:4]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the device
ddr_clk
lbiu_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
to local bus
memory
controller
to DDR
memory
controller
DLL
Clock
Div
/2
Divider
5
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 109
As shown in Figure 67, the primary cl ock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the inte rnal c loc k f o r the
DDR controller (ddr_clk), and the internal clock for the local bus interf ace uni t (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF Eqn. 20
In PCI host mode, PCI_SYNC_I N × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serv es as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequenc y to c reate the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low register
(RCWLR) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4,
“Reset, Clocking, and Initializa tion,” in the MPC8379E Reference Manual for more informatio n on the
clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWLR[DDRCM]) Eqn. 21
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determine d by the following equation:
lbiu_clk = csb_clk × (1 + RCWLR[LBCM]) Eqn. 22
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider
to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio i s contr olled by
LCRR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk
frequency . Those units have a default clock ratio that can be configured by a memory mapped register after
the device comes out of reset. Table 69 specifies which units have a conf igurable clock frequency.
Table 69. Configurable Clock Units
Unit Default Frequency Options
eTSEC1, eTSEC2 csb_clk/3 Off,
csb_clk, csb_clk/2, csb_clk/3
eSDHC and I2C11
1This only applies to I2C1 (I2C2 clock is not configurable).
csb_clk/3 Off,
csb_clk, csb_clk/2, csb_clk/3
Security block csb_clk/3 Off,
csb_clk, csb_clk/2, csb_clk/3
USB DR csb_clk/3 Off,
csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex csb_clk Off,
csb_clk
PCI Express1, 2 csb_clk/3 Off, c
sb_clk, csb_clk/2, csb_clk/3
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
110 Freescale Semiconductor
This table provides the operating frequencies for the TePBGA II package under recommended operating
conditions (see Table 3).
22.1 System PLL Configuration
The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency
depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 71 shows the multiplication factor encodings
for the system PLL.
NOTE
If RCWLR[ DDRC M] and RCWLR[L BCM ] are both cleared, the syst em
PLL VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If eit her RCWLR [DDR CM] o r RCWLR[LBCM ] are set , t he syst em P LL
VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
Table 70. Operating Frequencies for TePBGA II
Parameter1Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
e300 core frequency (
core_clk
) 333 800
Coherent system bus frequency (
csb_clk
) 133 400
DDR2 memory bus frequency (MCK)1250 400
DDR1 memory bus frequency (MCK) 2167 333
Local bus frequency (LCLK
n
)1— 133
Local bus controller frequency (
lbc_clk
) — 400
PCI input frequency (CLKIN or PCI_CLK) 25 66
eTSEC frequency 133 400
Security encryption controller frequency — 200
USB controller frequency — 200
eSDHC controller frequency — 200
PCI Express controller frequency — 400
Notes:
1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting
csb_clk
,
MCK, LCLK[0:2], and
core_clk
frequencies do not exceed their respective maximum or minimum operating frequencies.
The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,
USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.
2. The DDR data rate is 2× the DDR memory bus frequency.
3. The local bus frequency is ½, ¼, or 1/8 of the
lbiu_clk
frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the
csb_clk
frequency (depending on RCWLR[LBCM]).
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 111
As described in Section 22, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 73
and Table 74 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_I N ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 72.
Table 71. System PLL Multiplication Factors
RCWLR[SPMF] System PLL Multiplication Factor
0000 Reserved
0001 Reserved
0010 × 2
0011 × 3
0100 × 4
0101 × 5
0110 × 6
0111–1111 × 7 to × 15
Table 72. System PLL VCO Divider
RCWLR[SVCOD] VCO Division Factor
00 4
01 8
10 2
11 1
Table 73. CSB Frequency Options for Host Mode
CFG_CLKIN_DIV
at Reset1SPMF
csb_clk
:
Input Clock Ratio1
Input Clock Frequency (MHz)2
25 33.33 66.67
csb_clk
Frequency (MHz)
High 0010 2 : 1 133
High 0011 3 : 1 200
High 0100 4 : 1 133 267
High 0101 5 : 1 167 333
High 0110 6 : 1 150 200 400
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
112 Freescale Semiconductor
High 0111 7 : 1 175 233
High 1000 8 : 1 200 267
High 1001 9 : 1 225 300
High 1010 10 : 1 250 333
High 1011 11 : 1 275 367
High 1100 12 : 1 300 400
High 1101 13 : 1 325
High 1110 14 : 1 350
High 1111 15 : 1 375
Notes:
1. CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 74. CSB Frequency Options for Agent Mode
CFG_CLKIN_DIV
at reset1SPMF
csb_clk
:
Input Clock Ratio1
Input Clock Frequency (MHz)2
25 33.33 66.67
csb_clk
Frequency (MHz)
Low 0010 2 : 1 133
Low 0011 3 : 1 200
Low 0100 4 : 1 133 267
Low 0101 5 : 1 167 333
Low 0110 6 : 1 150 200 400
Table 73. CSB Frequency Options for Host Mode (continued)
CFG_CLKIN_DIV
at Reset1SPMF
csb_clk
:
Input Clock Ratio1
Input Clock Frequency (MHz)2
25 33.33 66.67
csb_clk
Frequency (MHz)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 113
22.2 Core PLL Configuration
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the
e300 core clock (core_clk). Table 75 shows the encodings for RCWLR[COREPLL]. COREPLL values
that are not listed in Table 75 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that th e core VCO frequency is i n the
range of 800–1600 MHz.
Low 0111 7 : 1 175 233
Low 1000 8 : 1 200 267
Low 1001 9 : 1 225 300
Low 1010 10 : 1 250 333
Low 1011 11 : 1 275 367
Low 1100 12 : 1 300 400
Low 1101 13 : 1 325
Low 1110 14 : 1 350
Low 1111 15 : 1 375
Notes:
1. CFG_CLKIN_DIV doubles csb_clk if set high.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 75. e300 Core PLL Configuration
RCWLR[COREPLL]
core_clk
:
csb_clk
Ratio VCO Divider 1
0–1 2–5 6
nn 0000 0 PLL bypassed
(PLL off,
csb_clk
clocks core directly)
PLL bypassed
(PLL off,
csb_clk
clocks core
directly)
11 nnnn nn/a n/a
00 0001 01:1 2
01 0001 01:1 4
10 0001 01:1 8
00 0001 11.5:1 2
Table 74. CSB Frequency Options for Agent Mode (continued)
CFG_CLKIN_DIV
at reset1SPMF
csb_clk
:
Input Clock Ratio1
Input Clock Frequency (MHz)2
25 33.33 66.67
csb_clk
Frequency (MHz)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
114 Freescale Semiconductor
22.3 Suggested PLL Configurations
This table shows suggested PLL configurations for different input clocks (LBCM = 0).
01 0001 11.5:1 4
10 0001 11.5:1 8
00 0010 02:1 2
01 0010 02:1 4
10 0010 02:1 8
00 0010 12.5:1 2
01 0010 12.5:1 4
10 0010 12.5:1 8
00 0011 03:1 2
01 0011 03:1 4
10 0011 03:1 8
00 0011 13.5:1 2
01 0011 13.5:1 4
10 0011 13.5:1 8
00 0100 04:1 2
01 0100 04:1 4
10 0100 04:1 8
Notes:
1. Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be set properly so that the core VCO
frequency is in the range of 800–1600 MHz.
Table 76. Example Clock Frequency Combinations
eLBC 1 e300 Core 1
Ref 1LBCM DDRCM SVCOD SPMF Sys
VCO1,2CSB1,3 DDR data
rate1,4/2 /4 /8 × 1× 1.5 × 2× 2.5 × 3
25.0 0 1 2 5 500 125 250 62.531.315.6————375
25.0 0 1 2 6 600 150 300 75 637.5 18.8 — — — 375 450
33.3 0 1 2 5 667 167 333 83.3 641.6 20.8 — — 333 416 500
33.3 0 1 2 4 533 133 267 66.7 33.3 16.7 — — — 333 400
Table 75. e300 Core PLL Configuration (continued)
RCWLR[COREPLL]
core_clk
:
csb_clk
Ratio VCO Divider 1
0–1 2–5 6
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 115
23 Thermal
This section describes the thermal specifications of this chip.
23.1 Thermal Characteristics
This table provides the package thermal characteristics for the 689 31 ×31mm TePBGA II package.
48.0 0 1 2 3 576 144 288 72 636 18 — — — 360 432
66.7 0 1 2 2 533 133 266 66.7 33.3 16.7 — — — 333 400
25.0 0 0 4 8 800 200 200 100 650 25 — — 400 500 600
33.3 0 0 2 8 533 266.7 267 133 666.7 33.3 — 400 533 667 800
50.0 0 0 4 4 800 200 200 100 650 25 — — 400 500 600
50.0 0 0 2 8 800 400 400 5— 100 650 — 600 800 — —
66.7 0 0 2 4 533 266.7 267 133 666.7 33.3 — 400 533 667 800
66.7 0 0 2 5 667 333 333 — 83.3 641.6 333 500 667 — —
66.7 0 0 2 6 800 400 400 5— 100 650 400 600 800 — —
Notes:
1. Values in MHz.
2. System PLL VCO range: 400–800 MHz.
3. CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates.
4. Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz.
5. Applies to DDR2 only.
6. Applies to eLBC PLL-enabled mode only.
Table 77. Package Thermal Characteristics for TePBGA II
Parameter Symbol Value Unit Note
Junction-to-ambient natural convection on single layer board (1s) RθJA 21 °C/W 1, 2
Junction-to-ambient natural convection on four layer board (2s2p) RθJA 15 °C/W 1, 2, 3
Junction-to-ambient (at 200 ft/min) on single layer board (1s) RθJMA 16 °C/W 1, 3
Junction-to-ambient (at 200 ft/min) on four layer board (2s2p) RθJMA 12 °C/W 1, 3
Junction-to-board thermal RθJB 8°C/W 4
Junction-to-case thermal RθJC 6°C/W 5
Table 76. Example Clock Frequency Combinations (continued)
eLBC 1 e300 Core 1
Ref 1LBCM DDRCM SVCOD SPMF Sys
VCO1,2CSB1,3 DDR data
rate1,4/2 /4 /8 × 1× 1.5 × 2× 2.5 × 3
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
116 Freescale Semiconductor
23.2 Thermal Management Information
For the following sections, PD = (VDD ×IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
23.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction t emperat ure, TJ, can be obtained from the equation:
TJ = TA + (R
θ
JA × PD)
where:
TJ = junction temperature (°C)
TA = am bien t te mp er at ure fo r the p acka ge (°C)
R
θ
JA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally, the value obtained on a single layer board i s appropriate for
a tightly packed printed circuit board. The value obtained on the board with the internal plan es is usually
appropriate if the board has low power dissipation and the components are well separated. T est cases have
demonstra ted that errors of a factor of two (in the quantity TJ – TA) are possible.
23.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
NOTE
The heat sink cannot be mounted on the package.
Junction-to-package natural convection on top ψJT 6°C/W 6
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Table 77. Package Thermal Characteristics for TePBGA II (continued)
Parameter Symbol Value Unit Note
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 117
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is s trongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperatur e near the device. Specifying
the local ambient conditions explicitly a s the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TA + (R
θ
JB × PD)
where:
TA = am bien t te mp er at ure fo r the pack a ge (°C)
R
θ
JB = junction to board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be ma de. The application boa rd should be similar to the thermal test condition: the
component is soldered to a board with int ernal planes.
23.2.3 Experimental Determination of Junction Temperature
NOTE
The heat sink cannot be mounted on the package.
To determine the junction temperature of the device in the application after prototypes are available, use
the thermal char acterization paramete r (
Ψ
JT) to determine the junction temperature and a measure of the
temperature at the top center of the package case using the following equation:
TJ = TT + (
Ψ
JT × PD)
where:
TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)
Ψ
JT = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type
T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned s o
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement er rors caus ed by cooling effects of the
thermocoup le wire.
23.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
For the power va lues the de vice is expected to operate at, it is anti cipated that a heat sink will be required.
A preliminary estimate of heat sink performance can be obtained from the following first-cut approa ch.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
118 Freescale Semiconductor
The therm al resis t ance is expressed as the sum of a junction to case thermal re si stance and a
case- to-ambie nt therma l resista nc e:
R
θ
JA = R
θ
JC + R
θ
CA
where:
R
θ
JA = junction to ambient thermal resistance (°C/W)
R
θ
JC = junction to case thermal resistance (°C/W)
R
θ
CA = cas e to am bie nt the rmal resi st ance (°C/W)
R
θ
JC is device-related and cannot be influenced by the user . The user controls the thermal environment to
change the case to ambient thermal resistance, R
θ
CA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
This first-cut approach overestimates the heat sink size required, since heat flow through the board is not
accounted for, which can be as much as one-third to one-half of the power generated in the package.
Accurate thermal design re quires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling through the package and board and
the convection cooling due to t he air moving through the application. Simplified thermal models of the
packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in
the thermal resistance table. More detailed thermal models can be made available on request.
The thermal performance of devices with heat sinks has been simulated with a few commercially available
heat sinks. The heat sink choice is determined by t he application environment (temperature, air flow,
adjacent component power dissipation) and the physical space available. Beca use of the wide variety of
application environments, a single standard heat sink applicable to all cannot be specified.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 119
This table shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a
standard JEDEC environment, per JESD 51-6.
Heat sink vendors include the following:
Aavid Thermalloy
www.aavidthermalloy.com
Al pha Nov atech
www.alphanovatech.com
International Electronic Research Corporation (IERC)
www.ctscorp.com
Millennium Electronics (MEI)
www.mei-thermal.com
Table 78. Thermal Resistance with Heat Sink in Open Flow (TePBGA II)
Heat Sink Assuming Thermal Grease Air Flow
Thermal Resistance
(°/W)
AAVID 30 × 30 × 9.4 mm Pin Fin Natural Convection 13.1
0.5 m/s 10.6
1 m/s 9.3
2 m/s 8.2
4 m/s 7.5
AAVID 31 × 35 × 23 mm Pin Fin Natural Convection 11.1
0.5 m/s 8.5
1 m/s 7.7
2 m/s 7.2
4 m/s 6.8
AAVID 43× 41× 16.5mm Pin Fin Natural Convection 11.3
0.5 m/s 9.0
1 m/s 7.8
2 m/s 7.0
4 m/s 6.5
Wakefield, 53 × 53 × 25 mm Pin Fin Natural Convection 9.7
0.5 m/s 7.7
1 m/s 6.8
2 m/s 6.4
4 m/s 6.1
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
120 Freescale Semiconductor
Tyco Electronics
Chip Coolers™
www.chipcoolers.com
Wakefield Engineering
www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
www.dowcorning.com
Shin-Etsu MicroSi, Inc.
www.microsi.com
The Bergquist Company
www.bergquistcompany.com
23.3 Heat Sink Attachment
The device requires the use of heat sinks. When heat sinks are attached, an interface material is required,
preferably thermal gre ase and a spring clip. The spring clip should connect to the printed ci rcuit board,
either to the board itself, to hooks soldered to the board, or to a pla stic stiffener. Avoid attachment forces
that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the
solder joint lifetime of the pac kage. The recommended maximum compressive force on the top of the
package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces,
and its performance should be verified under the application requirements.
23.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When a heat sink is used, the junction temperature is determined from a thermocoupl e inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimize the size of the clearance to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
dif ficulties with this technique, many engineers measure the heat sink temperature and then back calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperatur e, th e junction temper at ure is determine d from the junction to case thermal resi stance.
TJ = TC + (R
θ
JC × PD)
where:
TJ = junction temperature (°C)
TC = case temperature of the package (°C)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 121
R
θ
JC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
24 System Design Information
This section provides electrical and thermal design recommendations for successful application of this
chip.
24.1 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins . The AVDD
level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD
through a low frequency filte r scheme.
There are a number of ways to reliably provid e power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 68, one to each of the five AVDD pins. By
providing independent filters to each PLL, the opportunity to c ause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minim um E f fective Series Inductance (ESL).
Consistent with the recommendations of Dr . Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be pos sible to route directly f rom the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Figure 68. PLL Power Supply Filter Circuit
24.2 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply , especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These
decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, utilizing s hort traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
VDD AVDD (or L2AVDD)
2.2 µF 2.2 µF
GND Low ESL Surface Mount Capacitors
10 Ω
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
122 Freescale Semiconductor
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be severa l bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recha rging of the sm aller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through t wo
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
24.3 Connection Recommendations
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate
signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, L VDD, OVDD, and GND pins
of the device.
24.4 Output Buffer DC Impedance
The device drivers are character i zed over process , voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 69). The
output impedance is the average of two components, the resistances of the pull-up and pull -down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
Figure 69. Driver Impedance Measurement
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 123
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output vol tage is measured while driving logic 1 without an external diff erential
termination resistor . The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differ ential termination resistor of value Rterm. The
measured voltage is V2=(1/(1/R
1+1/R
2)) × Isource. Solving for the output impedance gives Rsource =
Rterm × (V1/V2– 1). The drive current is then Isource =V
1/Rsource.
This table summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
24.5 Configuration Pin Muxing
The device provide s the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4. 7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deas serts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull- up/pull-down r esistors coupled with the lar ge value of the pull-up/ pull-down r esistor should
minimize the disr uption of signal quality or speed for output pins thus configured.
24.6 Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
including I2C pins and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interfa ce,
see AN3665, “MPC837xE Design Checklist.”
25 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 25. 1, “Part Numbers Fully Addressed by This Document.”
Table 79. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DDR DRAM Symbol Unit
RN42 Target 25 Target 42 Target 20 Target Z0W
RP42 Target 25 Target 42 Target 20 Target Z0W
Differential NA NA NA NA ZDIFF W
Note: Nominal supply voltages. See Ta bl e 2 , Tj = 105°C.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
124 Freescale Semiconductor
25.1 Part Numbers Fully Addressed by This Document
Table 80 provides the Freescale part numbe ring nomenclature for this chip. Note that the individual part
numbers correspond to a maximum processor core frequency . For available frequencies, contact your local
Freescale sales offi ce. In addition to the processor frequency, the part number ing sc heme also includes an
application modifier which may specify special application conditions. Each part number also contains a
revision code which refers to the die mask revision number.
This table lists the available core and DDR data rate frequency combinations.
Table 80. Part Numbering Nomenclature
MPC
8378 ECZQ AF D A
Product
Code
Part
Identifier
Encryption
Acceleratio
n
Temperature
Range 1Package 2e300 core
Frequency 3
DDR
Data Rate
Revision
Level 4
MPC 8378 Blank = Not
included
E = included
Blank = 0°C (Ta)
to 125°C (Tj)
C = –40°C (Ta)
to 125°C (Tj)
VR = Pb-free
689 TePBGA II
AN = 800 MHz
AL = 667 MHz
AJ = 533 MHz
AG = 400 MHz
G = 400 MHz
F = 333 MHz
D = 266 MHz
Blank = Freescale
ATM C fab
A =
GlobalFoundries
fab
Note:
1Contact local Freescale office on availability of parts with an extended temperature range.
2See Section 21, “Package and Pin Listings,” for more information on the available package type.
3Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support
other maximum core frequencies.
4No design changes occurred between initial parts and the revision “
A
” parts. Only the fab source has changed in moving
to revision “
A
” parts. Initial revision parts and revision “
A
” parts are form, fit, function, and reliability equivalent.
Table 81. Available Parts (Core/DDR Data Rate)
MPC8377E MPC8378E MPC8379E
800 MHz/400 MHz 800 MHz/400 MHz 800 MHz/400 MHz
667 MHz/400 MHz 667 MHz/400 MHz 667 MHz/400 MHz
533 MHz/333 MHz 533 MHz/333 MHz 533 MHz/333 MHz
400 MHz/266 MHz 400 MHz/266 MHz 400 MHz/266 MHz
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 125
This table shows the SVR and PVR settings by device.
25.2 Part Marking
Parts are marked as in the example as sh own in this figure.
Figure 70. Freescale Part Marking for TePBGA II Devices
26 Document Revision History
This table provides a revision history for this document.
Table 82. SVR and PVR Settings by Product Revision
Device Package
SVR PVR
Rev 1.0 Rev. 2.1 Rev. 1.0 Rev. 2.1
MPC8377
TePBGA II
0x80C7_0010 0x80C7_0021
0x8086_1010 0x8086_1011
MPC8377E 0x80C6_0010 0x80C6_0021
MPC8378 0x80C5_0010 0x80C5_0021
MPC8378E 0x80C4_0010 0x80C4_0021
MPC8379 0x80C3_0010 0x80C3_0021
MPC8379E 0x80C2_0010 0x80C2_0021
Table 83. Document Revision History
Revision Date Substantive Change(s)
8 05/2012 In Ta bl e 1 5 , “DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V,” updated Output leakage
current (IOZ) min and max values.
7 10/2011 • In Ta b l e 80 , “Part Numbering Nomenclature,” updated “Revision Level description”and added footnote 4.
6 07/2011 In Section 2.2, “Power Sequencing,” updated power down sequencing information.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
TePBGA II
*MMMMM YWWLAZ
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
126 Freescale Semiconductor
5 07/2011 • In Ta ble 2, “Absolute Maximum Ratings1,” removed footnote 5 from LBIN to OVIN. Also, corrected
footnote 5.
•In Table 3, “Recommended Operating Conditions,” added footnote 2 to AVDD.
•In Figure 2, “Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD,” added LBVDD.
•In Table 13, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” updated IOZ min/max
to –50/50.
•In Figure 15, “RGMII and RTBI AC Timing and Multiplexing Diagrams,” added distinction between
tSKRGT_RX and tSKRGT_TX signals.
•In Ta b l e 3 8 , “MII Management AC Timing Specifications,” updated MDC frequency—removed Min and
Max values, added Typical value. Also, updated footnote 2 and removed footnote 3.
•In Table 53, “PCI DC Electrical Characteristics,” updated VIH min value to 2.0.
•In Table 68, “TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to
be consistent with AN3665, “MPC837xE Design Checklist.”
•In Ta b l e 7 0 , “Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,
and corrected DDR2 Minimum and Maximum Operating Frequency values.
4 11/2010 • In Ta ble 2 5, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.
•In Table 45, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR.
•In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 22, “Clocking,” updated LCCR
to LCRR.
•In Table 68, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
TEST_SEL1 pins—no change in functionality.
3 03/2010 • Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
•In Table 39, “USB DC Electrical Characteristics,” and Ta bl e 40 , “USB General Timing Parameters (ULPI
Mode Only),” added table footnotes .
•In Table 44, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 45, “Local Bus
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.
•In Figure 26, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and
Figure 28, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
•In Figure 66, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added
heat spreader.
•In Section 24.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list
of open drain type pins.
•In Table 68, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
AVDD_P pins.
•in Tab le 6 8 , “TePBGA II Pinout Listing,” added Note 17 to eTSEC pins.
•In Ta bl e 7 3 , “CSB Frequency Options for Host Mode,” and Table 7 4, “CSB Frequency Options for Agent
Mode,” updated
csb_clk
frequencies available.
•In Table 80, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
Table 83. Document Revision History (continued)
Revision Date Substantive Change(s)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor 127
2 10/2009 • In Ta ble 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
•In Table 5, “Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.
•In Table 5, “Power Dissipation 1,” added a column for “Typical Application at Tj=65°C (W)”.
•In Table 5, “Power Dissipation 1,” added a column for “Sleep Power at Tj=65°C (W)”.
•In Table 11, removed overbar from CFG_CLKIN_DIV.
•In Ta b le 1 7 , “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
•In Tab le 2 0 , “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
•In Table 20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Ta bl e 2 1 , “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
•In Table 26, “SGMII DC Transmitter Electrical Characteristics,” updated footnote 3.
•In Table 27, “SGMII DC Receiver Electrical Characteristics,” updated bit name LSTS to SEIC
x
, the
parameter values, and the maximum value of SEIC
x
= 01 to 100.
•In Table 27, “SGMII DC Receiver Electrical Characteristics,” updated VLOS maximum value for LSTS =0
to 150 mV .
•In Table 34, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.
•In Table 68, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
•In Table 70, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
•In Table 75, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
•In Table 76, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
•In Section 19.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV
,
respectively.
1 02/2009 • In Table 3 , “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
•In Table 5, “Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667 MHz.
•In Table 1 3 , “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” Ta b l e 2 1 , “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” and Ta bl e 6 8 , “TePBGA II Pinout Listing,” added
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,
MPC837xE Design Checklist
.
•In Table 21, updated tDDKHCX minimum value for 333 MHz to 2.40.
•In Table 68, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 15.
•In Table 70, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for
core_clk
.
•In Table 76, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
• Updated part numbering information in AF column in Ta b le 8 0 , “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
•In Table 81, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0 12/2008 Initial public release.
Table 83. Document Revision History (continued)
Revision Date Substantive Change(s)
Document Number: MPC8378EEC
Rev. 8
05/2012
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