To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. "Standard": 8. 9. 10. 11. 12. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD444008L 4M-BIT CMOS FAST SRAM 512K-WORD BY 8-BIT Description The PD444008L is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM. Operating supply voltage is 3.3 V 0.3 V. The PD444008L is packaged in 36-pin PLASTIC SOJ. Features * 524,288 words by 8 bits organization * Fast access time : 8, 10, 12, ns (MAX.) * Output Enable input for easy application * Single +3.3 V power supply Ordering Information Part number Package Access time Supply current mA (MAX.) ns (MAX.) At operating At standby 5 PD444008LLE-A8 36-pin PLASTIC SOJ 8 185 PD444008LLE-A10 (10.16 mm (400)) 10 165 PD44008LLE-A12 12 155 PD444008LLE-A8-A 8 185 PD444008LLE-A10-A 10 165 PD444008LLE-A12-A 12 155 Remark Products with -A at the end of the part number are lead-free products. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M14429EJ6V0DS00 (6th edition) Date Published September 2006 NS CP(K) Printed in Japan 1999 The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. PD444008L Pin Configuration (Marking Side) /xxx indicates active low signal. 36-pin PLASTIC SOJ (10.16 mm (400)) A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 /CS 6 31 /OE I/O1 7 30 I/O8 I/O2 8 29 I/O7 VCC 9 28 GND GND 10 27 VCC I/O3 11 26 I/O6 I/O4 12 25 I/O5 /WE 13 24 A14 A5 14 23 A13 A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A9 18 19 NC A0 - A18 : Address Inputs I/O1 - I/O8 : Data Inputs / Outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawing for the 1-pin index mark. 2 Data Sheet M14429EJ6V0DS PD444008L A0 | A18 I/O1 | I/O8 Row decoder Address buffer Block Diagram Memory cell array 4,194,304 bits Input data controller Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CS /OE /WE VCC GND Truth Table /CS /OE /WE Mode I/O Supply current H x x Not selected High impedance ISB L L H Read DOUT ICC L x L Write DIN L H H Output disable High impedance Remark x : Don't care Data Sheet M14429EJ6V0DS 3 PD444008L Electrical Specifications Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage VCC -0.5 Note Input / Output voltage VT -0.5 Note Operating ambient temperature TA 0 to 70 C Storage temperature Tstg -55 to +125 C to +4.0 V to +4.0 V Note -2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V VCC+0.3 V +0.8 V 70 C Supply voltage VCC 3.0 High level input voltage VIH 2.0 Low level input voltage VIL -0.3 Operating ambient temperature TA 0 Note -2.0 V (MIN.) (pulse width : 2 ns) 4 Data Sheet M14429EJ6V0DS Note PD444008L DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input leakage current ILI VIN = 0 V to VCC -2 +2 A Output leakage current ILO VI/O = 0 V to VCC, -2 +2 A mA /CS = VIH or /OE = VIH or /WE = VIL Operating supply current ICC Standby supply current /CS = VIL, Cycle time : 8 ns 185 II/O = 0 mA, Cycle time : 10 ns 165 Minimum cycle time Cycle time : 12 ns 155 ISB /CS = VIH, VIN = VIH or VIL 40 ISB1 /CS VCC - 0.2 V, 5 mA VIN 0.2 V or VIN VCC - 0.2 V High level output voltage VOH IOH = -4.0 mA Low level output voltage VOL IOL = +8.0 mA Remark 2.4 V 0.4 V MAX. Unit VIN : Input voltage VI/O : Input / Output voltage Capacitance (TA = 25 C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. Data Sheet M14429EJ6V0DS 5 PD444008L AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 3 ns) 3.0 V 1.5 V Test Points 1.5 V 1.5 V Test Points 1.5 V GND Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 Figure 2 (tAA, tACS, tOE, tOH) (tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW ) VTT = +1.5 V +3.3 V 50 317 ZO = 50 I/O (Output) I/O (Output) 30 pF CL Remark 6 351 CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M14429EJ6V0DS 5 pF CL PD444008L Read Cycle Parameter Symbol -A8 MIN. -A10 MAX. 8 MIN. -A12 MAX. MIN. 10 Unit Notes MAX. Read cycle time tRC 12 ns Address access time tAA 8 10 12 ns /CS access time tACS 8 10 12 ns /OE access time tOE 4 5 6 ns Output hold from address change tOH 3 3 3 ns /CS to output in low impedance tCLZ 3 3 3 ns /OE to output in low impedance tOLZ 0 0 0 ns /CS to output in high impedance tCHZ 4 5 6 ns /OE to output hold in high impedance tOHZ 4 5 6 ns 1 2, 3 Notes 1. See the output load shown in Figure 1. 2. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access) tRC Address (Input) tAA tOH I/O (Output) Previous data out Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Data Sheet M14429EJ6V0DS 7 PD444008L Read Cycle Timing Chart 2 (/CS Access) tRC Address (Input) tAA tACS /CS (Input) tCLZ tCHZ /OE (Input) tOHZ tOE tOLZ I/O (Output) High impedance Data out Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 8 Data Sheet M14429EJ6V0DS High impedance PD444008L Write Cycle Parameter Symbol -A8 MIN. -A10 MAX. MIN. -A12 MAX. MIN. Unit MAX. Write cycle time tWC 8 10 12 ns /CS to end of write tCW 6 7 8 ns Address valid to end of write tAW 6 7 8 ns Write pulse width tWP 6 7 8 ns Data valid to end of write tDW 4 5 6 ns Data hold time tDH 0 0 0 ns Address setup time tAS 0 0 0 ns Write recovery time tWR 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 4 3 5 6 3 Notes 3 ns 1, 2 ns Notes 1. Transition is measured at 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWR tWP /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE. 2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14429EJ6V0DS 9 PD444008L Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) tDH Data in Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remark 10 Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M14429EJ6V0DS High impedance PD444008L Package Drawing 36-PIN PLASTIC SOJ (10.16 mm (400)) B 36 19 C 1 D 18 G H J E F U Q M N S S T P M K I NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS B 23.60.20 C 10.160.1 D 11.180.2 E 1.0050.1 F 0.74 G H 3.50.2 2.5450.2 I 0.8 MIN. J K 2.6 1.27 (T.P.) M 0.42 +0.08 -0.07 N 0.12 P 9.40.20 Q 0.1 T R 0.85 U 0.22 +0.08 -0.07 P36LE-400A-2 Data Sheet M14429EJ6V0DS 11 PD444008L Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD444008L. Type of Surface Mount Device <R> PD444008LLE : 36-pin PLASTIC SOJ (10.16 mm (400)) PD444008LLE-A : 36-pin PLASTIC SOJ (10.16 mm (400)) Quality Grade * A quality grade of the products is "Standard". * Anti-radioactive design is not implemented in the products. * Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the ground and so forth. 12 Data Sheet M14429EJ6V0DS PD444008L Revision History Edition/ Date 6th edition/ Page Type of This Previous edition edition p.12 p.12 Location (Previous edition This edition) revision Addition Description Quality Grade Section of Quality Grade has been added. Sep. 2006 Data Sheet M14429EJ6V0DS 13 PD444008L [ MEMO ] 14 Data Sheet M14429EJ6V0DS PD444008L NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet M14429EJ6V0DS 15 PD444008L * The information in this document is current as of September, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1