1996-2011 Microchip Technology Inc. DS21178H-page 1
24AA00/24LC00/24C00
Device Selection Table
Features:
• Single Supply with Operation down to 1.8V for
24AA00 Devices, 2.5V for 24LC00 Devices
• Low-Power CMOS Technology:
- Read current 500 A, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, Typical
• Self-Timed Erase/Write Cycle
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges Available:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire
serial interface. Low-voltage design permits operation
down to 1.8 volts for the 24AA00 version, and every
version maintains a maximum standby current of only
1 A and typical active current of only 500 A. This
device was designed for where a small amount of
EEPROM is needed for the storage of calibration
values, ID numbers or manufacturing information, etc.
The 24XX00 is available in 8-pin PDIP, 8-pin SOIC
(3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN, TDFN and
the 5-pin SOT-23 packages.
Package Types
Block Diagram
Device VCC Range Temp Range
24AA00 1.8-5.5 I
24LC00 2.5-5.5 I
24C00 4.5-5.5 I,E
1
2
3
4
8
7
6
5
15
4
3
8-PIN PDIP/SOIC
8-PIN TSSOP
5-PIN SOT-23
NC
NC
NC
Vss
VCC
NC
SCL
SDA
NC
NC
NC
VSS
VCC
NC
SCL
SDA
SCL
VSS
SDA
VCC
NC
1
2
3
4
8
7
6
5
2
DFN/TDFN
NC
NC
NC
VSS
NC
SCL
SDA
VCC
8
7
6
5
1
2
3
4
HV Generator
EEPROM
Array
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
SDA SCL
VCC
VSS
128-Bit I2C™ Bus Serial EEPROM
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
I2C is a trademark of Philips Corporation.
24AA00/24LC00/24C00
DS21178H-page 2 1996-2011 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins..........................................................................................................................................4 kV
FIGURE 1-1: BUS TIMING DATA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Industrial (I): TA = -40°C to +85°C, VCC = 1.8V to 5.5V
Automotive (E) TA = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage VIH 0.7 VCC —V(Note)
Low-level input voltage VIL —0.3 VCC V(Note)
Hysteresis of Schmitt Trigger
inputs
VHYS .05 VCC —VVCC 2.5V (Note)
Low-level output voltage VOL —0.4VIOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current ILI —±1AVIN = VCC or VSS
Output leakage current ILO —±1AVOUT = VCC or VSS
Pin capacitance (all inputs/outputs) CIN,
COUT
—10pFVCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
Operating current ICC Write — 2 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —1AVCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.
TFTHIGH TR
TSU:STA
TLOW THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TSP
SCL
SDA
IN
SDA
OUT
THD:STA
1996-2011 Microchip Technology Inc. DS21178H-page 3
24AA00/24LC00/24C00
TABLE 1-2: AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I) : TA = -40°C to +85°C, VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min Max Units Conditions
Clock frequency FCLK —
—
—
100
100
400
kHz 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Clock high time THIGH 4000
4000
600
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Clock low time TLOW 4700
4700
1300
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
SDA and SCL rise time
(Note 1)
TR—
—
—
1000
1000
300
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
SDA and SCL fall time TF—300ns(Note 1)
Start condition hold time THD:STA 4000
4000
600
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Start condition setup time TSU:STA 4700
4700
600
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Data input hold time THD:DAT 0—ns(Note 2)
Data input setup time TSU:DAT 250
250
100
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Stop condition setup time TSU:STO 4000
4000
600
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Output valid from clock
(Note 2)
TAA —
—
—
3500
3500
900
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF 4700
4700
1300
—
—
—
ns 4.5V Vcc 5.5V (E Temp range)
1.8V Vcc 4.5V
4.5V Vcc 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF 20+0.1
CB
250 ns (Note 1), CB 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP —50ns(Notes 1, 3)
Write cycle time TWC —4ms
Endurance 1M — cycles (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
24AA00/24LC00/24C00
DS21178H-page 4 1996-2011 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
Pin Function Table
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3 Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Name PDIP SOIC TSSOP DFN(1) TDFN(1) SOT-23 Description
NC 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 — Not Connected
VSS 4 4 4 4 4 2 Ground
SDA 5 5 5 5 5 3 Serial Address/Data I/O
SCL 6 6 6 6 6 1 Serial Clock
WP 7 7 7 7 7 5 Write-Protect Input
VCC 8 8 8 8 8 4 +1.8V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
1996-2011 Microchip Technology Inc. DS21178H-page 5
24AA00/24LC00/24C00
3.0 FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
24AA00/24LC00/24C00
DS21178H-page 6 1996-2011 Microchip Technology Inc.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(A) (B) (C) (D) (A)(C)
SCL
SDA
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL 987654321 123
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter Data from transmitter
SDA
Acknowledge
Bit
1996-2011 Microchip Technology Inc. DS21178H-page 7
24AA00/24LC00/24C00
5.0 DEVICE ADDRESSING
After generating a Start condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of
operation is to be performed. The slave address for the
24XX00 consists of a 4-bit device code ‘1010’ followed
by three “don’t care” bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected (Figure 5-1). The 24XX00 monitors the bus for
its corresponding slave address all the time. It
generates an Acknowledge bit if the slave address was
true and it is not in a programming mode.
FIGURE 5-1: CONTROL BYTE FORMAT
1010xxxSACKR/W
Device Select
Bits
Don’t Care
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
24AA00/24LC00/24C00
DS21178H-page 8 1996-2011 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 bits), the “don’t care” bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be
written into the Address Pointer of the 24XX00. Only
the lower four address bits are used by the device, and
the upper four bits are “don’t cares.” The 24XX00 will
acknowledge the address byte and the master device
will then transmit the data word to be written into the
addressed memory location. The 24XX00 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time the 24XX00 will not generate Acknowl-
edge signals (Figure 6-1). After a byte Write command,
the internal address counter will not be incremented
and will point to the same address location that was just
written. If a Stop bit is transmitted to the device at any
point in the Write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the Stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a Stop bit is sent before a
full eight data bits have been transmitted, then the
Write command will abort and no data will be written.
The 24XX00 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)
at nominal conditions.
FIGURE 6-1: BYTE WRITE
SP
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte
Word
Address Data
A
C
K
A
C
K
A
C
K
10 x10 xxx
x = “don’t care” bit
xxx
0
1996-2011 Microchip Technology Inc. DS21178H-page 9
24AA00/24LC00/24C00
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA00/24LC00/24C00
DS21178H-page 10 1996-2011 Microchip Technology Inc.
8.0 READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX00 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
device discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
device as part of a write operation.
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. Then the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX00 will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the device discontinues transmission
(Figure 8-2). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24XX00 contains an
internal Address Pointer which is incremented by one
at the completion of each read operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
FIGURE 8-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PS
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1100xxx1
x = “don’t care” bit
1996-2011 Microchip Technology Inc. DS21178H-page 11
24AA00/24LC00/24C00
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address(n)
Control
Byte
S
T
A
R
T
Data (n)
A
C
K
A
C
K
N
O
A
C
K
x xxx
S1100xxx0 S110 0xxx1
x = “don’t care” bit
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
Control
Byte
A
C
K
N
O
A
C
K
Data n Data n + 1 Data n + 2 Data n + x
A
C
K
A
C
K
A
C
K
24AA00/24LC00/24C00
DS21178H-page 12 1996-2011 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC00
I/P 13F
0527
24LC00I
SN 0527
13F
XXXX
TYWW
NNN
4L00
I527
13F
5-Lead SOT-23 Example:
XXNN M03F
8-Lead 2x3 DFN Example:
204
527
13
XXX
YWW
NN
3
e
3
e
8-Lead 2x3 TDFN Example:
A04
527
13
XXX
YWW
NN
1996-2011 Microchip Technology Inc. DS21178H-page 13
24AA00/24LC00/24C00
Part Number
1st Line Marking Codes
TSSOP
SOT-23 DFN TDFN
I Temp. E Temp. I Temp. E Temp. I Temp. E Temp.
24AA00 4A00 B0NN — 201 — A01 —
24LC00 4L00 M0NN — 204 — A04 —
24C00 4C00 D0NN E0NN 207 — A07 A08
Note: NN = Alphanumeric traceability code
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
24AA00/24LC00/24C00
DS21178H-page 14 1996-2011 Microchip Technology Inc.
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
1996-2011 Microchip Technology Inc. DS21178H-page 15
24AA00/24LC00/24C00
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA00/24LC00/24C00
DS21178H-page 16 1996-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc. DS21178H-page 17
24AA00/24LC00/24C00
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24AA00/24LC00/24C00
DS21178H-page 18 1996-2011 Microchip Technology Inc.
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E
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NOTE 1
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c
A
A1
A2
L1 L
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1996-2011 Microchip Technology Inc. DS21178H-page 19
24AA00/24LC00/24C00
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA00/24LC00/24C00
DS21178H-page 20 1996-2011 Microchip Technology Inc.
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N
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NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
1996-2011 Microchip Technology Inc. DS21178H-page 21
24AA00/24LC00/24C00
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA00/24LC00/24C00
DS21178H-page 22 1996-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc. DS21178H-page 23
24AA00/24LC00/24C00
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA00/24LC00/24C00
DS21178H-page 24 1996-2011 Microchip Technology Inc.
,$*-./00%12(,
1996-2011 Microchip Technology Inc. DS21178H-page 25
24AA00/24LC00/24C00
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N
b
E
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123
e
e1
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A1
A2 c
L
L1
24AA00/24LC00/24C00
DS21178H-page 26 1996-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc. DS21178H-page 27
24AA00/24LC00/24C00
APPENDIX A: REVISION HISTORY
Revision E
Added DFN package.
Revision F (02/2007)
Revised Device Selection Table; Features Section;
Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2;
Revised Product ID System; Replaced Package
Drawings; Replaced On-line Support page.
Revision G (03/2007)
Replaced Package Drawings (Rev. AM).
Revision H (11/2011)
Added TDFN Package.
24AA00/24LC00/24C00
DS21178H-page 28 1996-2011 Microchip Technology Inc.
NOTES:
1996-2011 Microchip Technology Inc. DS21178H-page 29
24AA00/24LC00/24C00
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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information:
•Product Support – Data sheets and errata,
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•General Technical Support – Frequently Asked
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representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
24AA00/24LC00/24C00
DS21178H-page 30 1996-2011 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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DS21178H24AA00/24LC00/24C00
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1996-2011 Microchip Technology Inc. DS21178H-page31
24AA00/24LC00/24C00
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X/XX
PackageTemperature
Range
Device
Device: 24AA00: = 1.8V, 128 bit I2C™ Serial EEPROM
24AA00T: = 1.8V, 128 bit I2C Serial EEPROM
(Tape and Reel)
24LC00: = 2.5V, 128 bit I2C Serial EEPROM
24LC00T: = 2.5V, 128 bit I2C Serial EEPROM
(Tape and Reel)
24C00: = 5V, 128 bit I2C™ Serial EEPROM
24C00T: = 5V, 128 bit I2C™ Serial EEPROM
(Tape and Reel)
Temperature
Range:
I = -40°C to +85°C
E = -40°C to +125°C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
OT = Plastic SOT-23, 5-lead (Tape and Reel only)
MC = Plastic DFN (2x3x0.9 mm body), 8-lead
MNY(1) = Plastic TDFN, (2x3x0.75 mm body), 8-lead
(Tape and Reel only)
Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish.
Examples:
a) 24AA00-I/P: Industrial Temperature,1.8V
PDIP package
b) 24AA00-I/SN: Industrial Temperature,
1.8V, SOIC package
c) 24AA00T-I/OT: Industrial Temperature,
1.8V, SOT-23 package, tape and reel
d) 24LC00-I/P: Industrial Temperature,
2.5V, PDIP package
e) 24C00-E/SN: Extended Temperature,
5V, SOIC package
f) 24LC00T-I/OT: Industrial Temperature,
2.5V, SOT-23 package, tape and reel
g) 24C00T-I/MNY: Industrial Temperature,
5V, TDFN pacakge
24AA00/24LC00/24C00
DS21178H-page 32 1996-2011 Microchip Technology Inc.
NOTES:
1996-2011 Microchip Technology Inc. DS21178H-page 33
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 1996-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-767-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21178H-page 34 1996-2011 Microchip Technology Inc.
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08/02/11
