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Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.11
FUJITSU SEMICONDUCTOR
DATA SHEET DS405-00015-1v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.1
ASSP for Power Management Applications
2ch Buck DC/DC Converter + 1ch LDO
with I2C interface and SW FET
MB39C031
DESCRIPTION
The MB39C031 contains 2ch buck DC/DC converter and 1ch LDO. It is possible to supply the main power
supply line in a system by using only one chip. The current mode system is adopted for the DC/DC
converter, and it is possible to use the chip inductor with the high switching frequency operation which
contains internal SW FET. The MB39C031 contains the output setting resistor and the the phase
compensation circuit, and contributes to reduce the number of external components and the mounting area.
Also, it contains the CTL input pin which can control the ON/OFF for each CH, the Power Good signal
output pin and the I2C communication interface, therefore it is easy to design the power supply sequence.
It is possible to tune in the output voltage exactly using the I2C communication and possible to correspond
to the DVS/ASV system.
FEATURES
Operating input voltage range:2.5V to 5.5V (Maximum rating: 7V)
Output voltage setting range, Maximum output current: DD1*:1.0V to 1.3V (20mV/step), 1.4A (DC)
DD2*:1.2V to 1.95V (50mV/step), 0.6A (DC)
LDO:2.8V/2.85V/3.0V/3.3V, 0.25A (DC)
Note: Each channel has selective preset voltage (Lineup for a total of 32 kinds) .
Soft-start time setting range: 0.9ms to 14.3ms (approximately 0.9ms/step)
Switching frequency for the DC/DC block:3MHz (fixed)
Communication interface: I2C (ON/OFF, Output voltage, Soft-start time setting)
Built-in PFM/PWM auto switching mode
Built-in function: Output setting resistor, Phase compensation circuit, Discharge resistor, Soft-start
Each Channel Power Good output function (Open-drain)
Protection function: Under voltage lockout protection circuit (UVLO), Over current protection circuit
(OCP), Thermal shutdown protection circuit (TSD)
Error signal output pin installed (Open-drain)
Small package: QFN28 (4mm × 4mm × 0.8mm, 0.4mm pitch)
*: DD1,DD2 : DC/DC converter block 1, 2
APPLICATION
Network equipment: Wifi-tuner, Surveillance camera
Data-storage device: HDD, SSD, Picture recording equipment
Image and voice output equipment: MFP, Printer, Scanner, Projector, Electrophone, STB
Various terminals: POS, FA, HEMS etc.
2
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
APPLICATION CIRCUIT EXAMPLE
0.1μF0.1μF
0.1μF
0.1μF
0.47μF
CTL Signal
I2C Signal
4.7μF4.7μF4.7μF
Vin
5.0V
MB39C031
LX2
CTL1
PGND1
LX1
PVCC1
IN1
CTLMAIN
VCC
VCCI2C
SCL
SDA
ADDSEL
GND
VR
VREF
IN2
PVCC2
PGND2
CTL2
GND
CTLL LDO
PVCCL
VCC
1.5μH
10μF
Vo1
1.2V 1.4A
1.5μH
10μF
Vo2
1.8V 0.6A
10μF
LDO
3.3V 0.25A
100k 100k 100k 100k
PG1
PG2
PGL
ERR
3
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
RECOMMENDED APPLICATION SPECIFICATIONS
[Input Voltage Range]
Input voltage VCC (V)
Min Typ Max
2.5 3.6 5.5
[Output Specification]
(Ta=+25°C)
Output voltage
(V)
Output
current
(mA)
Limit
Current
(mA)
Channel
Symbol
Accuracy
Min Typ Max Max Min
Mode
Switching
frequency
(MHz)
Coil
(μH)
Output
capacitance
(μF)
Soft-start
time
(ms)
Discharge
resistance
(kΩ)
Remarks
0.99* 1.00* 1.01* 14.3
1.01 1.02 1.03 0.9*
1.03 1.04 1.05 1.8
1.05 1.06 1.07 2.7
1.07 1.08 1.09 3.6
1.09* 1.10* 1.11* 4.5
1.11 1.12 1.13 5.4
1.13 1.14 1.15 6.3
1.15 1.16 1.17 7.2
1.17 1.18 1.19 8.1
1.19* 1.20* 1.21* 9.0
1.21 1.22 1.23 9.9
1.23 1.24 1.25 10.8
1.24 1.26 1.28 11.6
1.26 1.28 1.30 12.5
DD1 Vo1 ±1.2%
1.28* 1.30* 1.32*
1400 2000
Buck
(synchronous
rectification)
C-mode
3.0 1.5 10
13.4
5
Built-in SW
FET
Built-in
output setting
resistors
Operation
mode
switching
(Fixed PWM,
PFM/PWM)
1.19* 1.20* 1.21* 14.3
1.24 1.25 1.27 0.9*
1.28 1.30 1.32 1.8
1.33* 1.35* 1.37* 2.7
1.38 1.40 1.42 3.6
1.43 1.45 1.47 4.5
1.48* 1.50* 1.52* 5.4
1.53 1.55 1.57 6.3
1.58 1.60 1.62 7.2
1.63 1.65 1.67 8.1
1.68 1.70 1.72 9.0
1.73 1.75 1.77 9.9
1.78* 1.80* 1.82* 10.8
1.83 1.85 1.87 11.6
1.88 1.90 1.92 12.5
DD2 Vo2 ±1.2%
1.93 1.95 1.97
600 900
Buck
(synchronous
rectification)
C-mode
3.0 1.5 10
13.4
5
Built-in SW
FET
Built-in
output setting
resistors
Operation
mode
switching
(Fixed PWM,
PFM/PWM)
4
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
Output voltage
(V)
Output
current
(mA)
Limit
Current
(mA)
Channel
Symbol
Accuracy
Min Typ Max Max Min
Mode
Switching
frequency
(MHz)
Coil
(μH)
Output
capacitance
(μF)
Soft-start
time
(ms)
Discharge
resistance
(kΩ)
Remarks
2.75 2.80 2.85 14.3
2.80* 2.85* 2.90* 0.9
2.95 3.00 3.05 1.8
3.24* 3.30* 3.36* 2.7*
- - - 3.6
- - - 4.5
- - - 5.4
- - - 6.3
- - - 7.2
- - - 8.1
- - - 9.0
- - - 9.9
- - - 10.8
- - - 11.6
- - - 12.5
LDO LDO ±1.8%
- - -
250 300 LDO - - 4.7
13.4
5
*: Preset value
Note: It is possible to set the output voltage and to change the soft-start time using I2C.
5
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PIN ASSIGNMENT
(TOP VIEW)
VCC
ERR
PVCCL
LDO
PGL
CTLL
GND
CTL1 121
CTL2
PG1 220
PG2
PGND1 319
PGND2
LX1 4Top View 18 LX2
PVCC1 517
PVCC2
IN1 6EP(Exposed Pad) 16 IN2
CTLMAIN 715
VREF
VCC
VCCI2C
SCL
SDA
ADDSEL
GND
VR
8 9 10 11 12 13 14
28 27 26 25 24 23 22
(LCC-28P-M70)
6
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PIN DESCRIPTIONS (PKG)
Circuit
block Pin name
Numb
er of
pin for
PKG
Pin
No I/O Description
(PKG)
Pull-
down
resista
nce
PAD
treatment
when not
using DD1
PAD
treatment
when not
using DD2
PAD
treatment
when not
using LDO
PAD
treatment
when not
using I2C
communic
ation
IN1 1 6 I
DD1·Output voltage
feedback pin. - GND
connection - - -
PVCC1 1 5 -
DD1·Output block
power supply pin - VCC
connection - - -
LX1 1 4 O
DD1·Pin for
inductance
connection.
- Open - - -
PG1 1 2 O
DD1·POWERGOOD
output pin - Open - - -
DD1
PGND1 1 3 -
DD1·Output block
ground pin - GND
connection - - -
IN2 1 16 I
DD2·Output voltage
feedback pin. - - GND
connection - -
PVCC2 1 17 -
DD2·Output block
power supply pin - - VCC
connection - -
LX2 1 18 O
DD2·Pin for
inductance
connection.
- - Open - -
PG2 1 20 O
DD2·POWERGOOD
output pin - - Open - -
DD2
PGND2 1 19 -
DD2·Output block
ground pin - - GND
connection - -
PVCCL 1 26 -
LDO·Power supply
pin - - - VCC
connection -
LDO 1 25 O LDO·Output pin - - - Open -
LDO
PGL 1 24 O
LDO·POWERGOOD
output pin - - - Open -
CTL1 1 1 I DD1 Control pin Open - - -
CTL2 1 21 I DD2 Control pin - Open - -
CTLL 1 23 I LDO Control pin - - Open -
CTL
CTLMAIN 1 7 I
Control pin for
common block and
digital block *
- - - -
ERR ERR 1 27 O
ERR signal output
pin - - - - -
VCCI2C 1 9 -
Power supply pin for
I2C. - - - - GND
connection
SCL 1 10 I I2C clock pin × - - - Open
SDA 1 11 I/O I2C data I/O pin × - - - Open
I2C
ADDSEL 1 12 I
Switch pin for slave
address
- - - Open
7
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
Circuit
block Pin name
Numb
er of
pin for
PKG
Pin
No I/O Description
(PKG)
Pull-
down
resista
nce
PAD
treatment
when not
using DD1
PAD
treatment
when not
using DD2
PAD
treatment
when not
using LDO
PAD
treatment
when not
using I2C
communic
ation
VCC 2
8,
28 - Control circuit block
power supply pin - - - - -
VREF 1 15 O
Reference voltage
(2.4V) output pin - - - - -
VR 1 14 O
Reference voltage
(0.6V) output pin - - - - -
Common
GND 2
13,
22 - Control circuit block
ground pin - - - - -
- GND 1 EP - Ground pin - - - - -
*: When turning on DD1, DD2 and LDO, it is also necessary to set CTLMAIN to "H". See OPERATION
MODE LIST for the details.
8
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
BLOCK DIAGRAM
Common block
VREF BGR
Common block
power supply
Logic control
block
PVCCL
LDO
<<LDO>>
LDO:2.80V/2.85V/
Io(Max):250mA
(2.4V)
RT
VREF
SCP (counter & latch)
UVLO
CT
OTP
scp1/2/l
OSC
SCL
SDA
VR
(0.6V)
Vo1:1.00V to 1.30V
(20mV step)
Io(Max):1400mA
A
A
ErrAMP
0.6V
<<DD1>>
PVCC1
SLP
PWM
Logic
Control
ICOMP
LX1
IN1
LV
CNV
AST
L Priority
DEC
PGND1
vsel1
VCC VCC
VCC
cs1 scp1 clk1
UVLO
POR
VREF
clk1/2
VREF
cs1/2/l
vsel1/2/l
DEC
vsell
0.6V
Output voltage
switch control
Soft-start control
VCC:2.5V to 5.5V
CTL1
PG1
Vo2:1.20V to 1.95V
(50mV step)
Io(
Max
):600mA
B
B
ErrAMP
0.6V
<<DD2>>
PVCC2
SLP
PWM
Logic
Control
ICOMP
LX2
IN2
LV
CNV
AST
LPriority
DEC
PGND2
vsel2
VCC VCC
VCC
cs2 scp2 clk2
UVLO
POR
CTL2
PG2
CTLL
UVLO
POR
PGL
ERR
VR,OSC,logic power supply
VR
Reference
0.6V
GND
ctl1
ctl2
ctll
ctl2
ctl1
ctll
csl scpl
VCCI2C
ADDSEL
VREF
CTLMAIN
ctlmain
ctlmain
:Pin
VCC
VCC
GND
3.00V/3.30V
9
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
ABSOLUTE MAXIMUM RATINGS
Rating
Parameter Symbol Condition Min Max
Unit
Power supply voltage VCC VCC, PVCC1, PVCC2,
PVCCL, VCCI2C pins - 7 V
VCTL CTLMAIN, 1, 2, L pins - 7 V
VOUT IN1, IN2 pins - 7 V
Input voltage
Vlogic SDA, SCL pins - 7 V
LX voltage VLX LX1, LX2 pins -0.3 +7 V
Power dissipation PD
Ta ≤ +25°C
Thermal resistor value
(θj-a):(50°C/W*)
- 1720 mW
Maximum junction
temperature Tjmax - - +125 °C
Storage temperature TSTG - -55 +125 °C
*: When mounted on a QFN28 (LCC-28P-M70) PKG, 4layers 0.8mm thickness 117mm × 84mm
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
10
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
RECOMMENDED OPERATING CONDITIONS
Value
Parameter Symbol Condition Min Typ Max
Unit
Power
supply
voltage
VCC VCC pin 2.5 3.6 5.5 V
IREF VREF pin -1 - 0 mA
Reference
voltage
output
current IR VR pin -1 - 0 μA
General
Operating
temperature Ta - -30 +25 +85 °C
Power
supply
voltage
VCC VCC, PVCC1, PVCC2 pins 2.5 3.6 5.5 V
DC/DC
CH Input
voltage VOUT IN1, IN2 pins 0 - VCC V
LDO
CH
Power
supply
voltage
VCC
VCC, PVCCL pins
Output voltage setting: default
(3.3V)
3.5 3.6 5.5 V
CTL
block
Input
voltage VCTL CTL* pin 0 - VCC V
Power
supply
voltage
VCC VCCI2C pin 1.76 - 3.37 V
Digital
block
(I2C) Logic
input
voltage
Vlogic SDA, SCL pin 0 - VCCI2C V
*: CTLMAIN, CTL1, CTL2, CTLL
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
11
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
ELECTRICAL CHARACTERISTICS
1. Common Block
(Ta=+25°C, VCC=PVCC1, PVCC2, L=3.6V)
Value
Parameter Symbol Condition
Min Typ Max Unit
VR VR pin =0mA 0.594 0.600 0.606 V
VREF1 VREF pin =0mA 2.376 2.400 2.424 V
VREF2 VCC pin =2.5V to 5.5V 2.370 2.400 2.430 V
Reference Voltage
Block
[VR, VREF]
Output voltage
VREF3 VREF pin =0mA to -1mA 2.370 2.400 2.430 V
Threshold
voltage VTH VCC pin = 2.156 2.20 2.244 V
Under Voltage
Lockout
Protection Circuit
Block
[VCC UVLO]
Hysteresis
width VH - - 0.20 - V
Over Current
Protection Circuit
Block [OCP]
Timer time tOCP1 DD1, DD2, LDO Default
value 0.5 1 1.5 ms
Thermal
shutdown
Protection Circuit
Block [TSD]
Stop
temperature TTSDH - - 150* - °C
VIH CTL* pin VCC
× 0.7 - VCC V
Input voltage
VIL CTL* pin 0 - 0.4 V
ICTLH CTL* pin =3.6V 2.7 3.6 5.1 μA
Input current ICTLL CTL* pin =0V - - 1 μA
Control Block
(CTL)
[CTL]
Input pull-down
resistor RP CTL* pin - 1 - MΩ
IVCCS1 CTL* pin =0V - 0 1.0 μA
IVCCS2 CTLMAIN=3.6V
CTL1, CTL2.L pins =0V - 80 120 μA
IVCC
CTLMAIN, L pins =3.6V
Only LDO operation No
load
- 200 300 μA
IVCC
CTL* pin = 3.6V
all CH No load
(DD operation mode:
PFM/PWM mode)
- 450 680 μA
IVCC
CTL* pin = 3.6V
all CH No load
(DD operation mode:
Fixed PWM mode)
- 10.8 16.2 mA
General
(DC/DC block)
Power supply
current
IVCCI2C CTLMAIN, L pin=3.6V
VCCI2C pin = 1.8V - 7.2 12.0 μA
*: These are not the rated values. Use these values as reference when planning.
12
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
2. DD1, DD2
(Ta=+25°C, VCC=PVCC1, PVCC2, L=3.6V)
Value
Parameter Symbol Condition
Min Typ Max Unit
Output voltage VOUT
Output voltage setting:
1.2V
IOUT=-10mA
1.186 1.20 1.214 V
Input stability VLINE IOUT=-10mA,
VCC=2.5V to 5.5V -5 - +5 mV
IOUT=-1mA to
-1400mA (when in
Fixed PWM mode)
-10 - - mV
Load stability VLOAD IOUT=-1mA to
-1400mA (when in
PFM/PWM mode)
-10 - +15 mV
IN1 pin input
impedance RIN
IN1 pin=1.5V
output voltage setting:
1.2V
- 400 - kΩ
SW PMOS-Tr ON
resistance RPMOS LX1 pin=-30mA - 0.12* - Ω
SW NMOS-Tr ON
resistance RNMOS LX1 pin= 30mA - 0.09* - Ω
SW PMOS-Tr leak
current ILEAK LX1 pin=0V -1 - - μA
SW NMOS-Tr leak
current ILEAK LX1 pin=3.6V - - 1 μA
Overcurrent protection
value ILIMIT L=1.5μH 2000 - - mA
PFM/PWM
reshuffling electric
current
IPFM L=1.5μH - 40* - mA
Discharge resistor RDIS - - 5 - kΩ
Soft-start time tSS Preset value 0.8 0.9 1.0 ms
DC/DC
Converter
Block
[DD1]
Switching frequency fOSC - 2.7 3.0 3.3 MHz
13
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
Value
Parameter Symbol Condition
Min Typ Max Unit
Output voltage VOUT Output voltage setting:
1.8V IOUT=-10mA 1.778 1.80 1.822 V
Input stability VLINE IOUT=-10mA
VCC=2.5V to 5.5V -5 - +5 mV
IOUT=-1mA to -600mA
(when in Fixed PWM
mode)
-10 - - mV
Load stability VLOAD IOUT=-1mA to -600mA
(when in PFM/PWM
mode)
-10 - +20 mV
IN2 pin input
impedance RIN
IN2 pin =2.0V
Output voltage setting:
1.8V
- 300 - kΩ
SW PMOS-Tr ON
resistance RPMOS LX2 pin =-30mA - 0.16* - Ω
SW NMOS-Tr ON
resistance RNMOS LX2 pin = 30mA - 0.14* - Ω
SW PMOS-Tr leak
current ILEAK LX2 pin =0V -1 - - μA
SW NMOS-Tr leak
current ILEAK LX2 pin =3.6V - - 1 μA
Overcurrent protection
value ILIMIT L=1.5μH 900 - - mA
PFM/PWM
reshuffling electric
current
IPFM L=1.5μH - 70* - mA
Discharge resistor RDIS - - 5 - kΩ
Soft-start time tSS Preset value 0.8 0.9 1.0 ms
DC/DC
Converter
Block
[DD2]
Switching frequency fOSC - 2.7 3.0 3.3 MHz
*: These are not the rated values. Use these values as reference when planning.
14
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
3. LDO
(Ta=+25°C, VCC=PVCC1, PVCC2, L=3.6V)
Value
Parameter Symbol Condition Min Typ Max Unit
Output voltage VOUT Output voltage setting : 3.3V
IOUT=-10mA 3.241 3.300 3.359 V
I/O voltage
difference VDIF IOUT=-10mA - - 0.20 V
Input stability VLINE IOUT=-10mA,
VCC=3.5V to 5.5V -5 - +5 mV
Load stability VLOAD IOUT=-1mA to -150mA -30 -20 - mV
PVCCL=0.2Vrms, f=10Hz,
IOUT=-150mA 35 75 - dB
Ripple remove
ratio RR PVCCL=0.2Vrms, f=10kHz,
IOUT=-150mA 15 50 - dB
Overcurrent
protection value ILIMIT Vout×0.9 300 - - mA
IPVCCLS At stand-by - 0 1 μA Control macro
consumption
current IPVCCL IOUT=0mA - 80 105 μA
Discharge resistor RDIS - - 5 - kΩ
LDO
Block
[LDO]
Soft-start time tSS Preset value 2.4 2.7 3.0 ms
15
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
4. Digital Block
(Ta=+25°C, VCC=PVCC1, PVCC2, L=3.6V)
Value
Parameter Symbol Condition
Min Typ Max
Unit
Output
voltage VOL PG1, PG2, L pins
IOL=1mA - - 0.4 V
Output
current IOL PG1, PG2, L pins 1 - - mA
Low-voltage
detection Vth IN1, IN2, LDO
pins = - Vo ×
0.75* - V
POWER-GOOD
Block
[Power Good ]
Power-on
detection
voltage
Vth IN1, IN2, LDO
pins = - Vo ×
0.85* - V
Output
voltage VOL ERR pin IOL =
1mA - - 0.4 V
Error Block
[ERR] Output
current IOL ERR pin 1 - - mA
VIH SCL, SDA pins
VCCI2C=3.3V
VCCI2C ×
0.7 - VCCI2C V
Input voltage
VIL SCL, SDA pins
VCCI2C=3.3V 0 -
VCCI2C ×
0.3 V
IIH SCL, SDA pins
VCCI2C=3.3V - - 10 μA
Input current
IIL SCL, SDA pins
VCCI2C=3.3V -10 - - μA
Output
voltage VOL SDA pin IOL
=3mA - - 0.4 V
Output
current IOL SDA pin 3 - - mA
I2C Block
[I2C]
Input
pull-down
resistor
RP ADDSEL pin - 1 - MΩ
*: These are not the rated values. Use these values as reference when planning.
16
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
OPERATION MODE LIST
Mode Stand-by Stand-by 2 General
ERR
detection
CTLMAIN (External) L H H H
CTL1 (External / I2C) L L H/L X
CTL2 (External / I2C) L L H/L X
CTL Signal
CTLL (External / I2C) L L H/L X
General OFF ON ON ON
Digital Block OFF ON ON ON
OSC, VR Block OFF OFF ON*2 OFF
DD1 OFF OFF ON/OFF OFF
DD2 OFF OFF ON/OFF OFF
Operation
Block
LDO OFF OFF ON/OFF OFF
I2C
Communication I2C communication Disabled Enabled Enabled Enabled
Thermal shutdown
Protection (TSD) Not available Not available Available *1
Protection
Operating Over Current Protection
(OCP) Not available Not available Available *1
*1: This is the state after detection of ERR. It is possible to release the ERR detection mode by turning the power
supply on again or turning CTLMAIN on again.
*2: When only LDO is operating, the OSC block stops (OFF) after LDO activation. Also, the VR block keeps
operating (ON) after LDO activation.
Priority of the external pin/I2C communication for CTL1, CTL2 and L
CTLMAIN
(External pin)
CTL*
(External pin)
CTL*
(I2C communication) Relevant CH
H H H Unavailable
H H L ON
H L H ON
H L L OFF
L X Communication disabled OFF
*: The I2C communication is enabled after the common block and digital block activation setting the external
CTLMAIN pin to "H".
When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the
ON/OFF control using I2C. Aside from the ON/OFF control, it is possible to control everything else using
I
2C.
When executing the ON/OFF control for DD1, DD2 and LDO using I2C, input "L" to the CTL* pin (the pin
is open or in the GND connection condition).
17
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
STATE TRANSITION DIAGRAM
Stand-by
Stand-by
2
General
Error
detection
(1) (2)
(6)
(5)
(4)(3)
(1) External CTLMAIN pin "H"
(2) External CTLMAIN pin "L"
(3) External CTL pin "H" / I2C communication "relevant CH_ON"
(4) External CTL pin "L" / I2C communication "relevant CH_OFF"
(5) Error detection (OCP, OCP_1ms continuation)
(6) Turning on the power supply again (equal to or less than uvlo_vcc reset voltage) or setting CTLMAIN to "L"
Notes: When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the
ON/OFF control using I2C. Aside from the ON/OFF control, it is possible to control everything else
using I2C.
When executing the ON/OFF control for DD1, DD2 and LDO using I2C, input "L" to the CTL* pin
(the pin is open or in the GND connection condition).
18
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
TURNING ON AND OFF SEQUENCE (Turning ON CTL*:CTL1, CTL2,
CTLMAIN=VCC Simultaneously)
VCC
VR
osc
(IC
internal signal
)
2.2V
0.6V
85%
DD1
PG1
CTL*
ctl*
(IC
internal signal
)
2.0V
VCCI2C
85%
DD2
PG2
0V
UVLO release to DD*activation
Time till start *
Typ:200μS
Max:300μS
Soft-start time
uvlo_vcc
(IC
internal signal
)
VREF
2.4V
Discharge
Discharge
90%
*: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF pin capacitance : 0.1μF
VR pin capacitance : 0.47μF
19
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
CTL* TURNING ON AND OFF SEQUENCE 1 (VCC → CTL*: CTL1, CTL2,
CTLMAIN)
VCC
VR
osc
(IC internal signal)
3.6V
0.6V
85%
DD1
PG1
CTL
*
ctl*
(IC internal signal)
VCCI2C
85%
DD2
PG2
0V
Turning on CTL
*
to DD
*
activation
Typ:270μS
Max:450μS
Soft-start time
uvlo_vcc
(IC internal signal)
VREF 2.4V
Discharge
90%
Discharge
Time till start *
*: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF pin capacitance : 0.1μF
VR pin capacitance : 0.47μF
20
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
CTL* TURNING ON AND OFF SEQUENCE 2 (VCC→CTLMAIN→CTL1→CTL2)
VCC
VR
osc (IC internal signal)
3.6V
0.6V
85%
DD1
PG1
CTLMAIN
ctl1 (IC internal signal)
VCCI2C
85%
DD2
PG2
0V
Soft-start time
uvlo_vcc
(IC internal signal)
VREF 2.4V
Discharge
Discharge
90%
CTL1
CTL2
ctl2 (IC internal signal)
Soft-start time
(1)
(2)
(1) Time from turning on CTLMAIN to VREF activation completion (=communication enabled)*
Typ: 130μS, Max: 200μS
(2) Time from turning on CTL1 to ctll (IC internal signal) "H"
Typ: 150μS, Max: 250μS
*: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance.
Time in the sequence figure above is applied for the following condition.
VREF pin capacitance : 0.1μF
VR pin capacitance : 0.47μF
21
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
CTL* PIN THRESHOLD VOLTAGE
The input circuit structure for the CTL* pin is the schmitt trigger style, and the threshold voltage shows the
hysteresis characteristics when CTL* OFF → ON and ON → OFF. (See "·CTL* pin equivalent circuit
diagram" below.)
Also, the threshold voltage level depends on the VCC pin voltage.
Moreover, make sure to input either the "H" level (>"VCC×0.7"V) or "L" level (<0.4V) to the CTL* pin
when in use.
CTL* pin equivalent circuit diagram
GND
CTL*
VCC
ESD protection
element
The CTL threshold voltage
shows the hysteresis
characteristics.
ESD protection
element
22
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PROTECTION OPERATION SEQUENCE
DD channel
The DD channel monitors the FET current peak value at any time during the operation. When the DD output
becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed
and the output stops after about 1ms progress.
LDO channel
It contains the fold-back type over current protection circuit in order to prevent destroy because of the over
load and the output over current. It limits the output current and the output voltage from the peak around the
over current protection value for LDO (ILIMIT) to the over current current (Is).
At this time, if the output voltage Vo gets lower than the detection voltage Vd (Vd: Vo×0.5), the timer
operation starts and the output stops after about 1ms progress. Moreover, because the over current protection
circuit does not operate at the soft-start (0V to Vo × 0.7), neither the output stops nor the error signal outputs.
However, the fold-back type over current protection characteristic functions. The following shows the
fold-back type over current protection characteristic.
Output voltage
Output current Io
Vo
Vo×0.5
Is ILmax ILIMIT
Vd
Soft-start
Vo
t
Output voltage setting value
Fold-back characteristic over current function
(over current limit operation)
Vo×0.9
Vo×0.7
Over current protection
circuit stop
(no stop output)
Over current protection
circuit operation
(stop output)
Thermal shutdown protection
If the temperature at the junction part reaches +150°C, the thermal shutdown protection circuit turns all
channels off.
23
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
Error detection sequence
DD1, DD2, LD
O
ERR detection mode
ERROR signal output (ERR pin)
Voltage drop
1ms
Continue for 1ms?
No
Normal
operation
Yes
Over current
detection
Normal
operation
Thermal
shutdown
protection
The whoIe IC
ERR detection mode release
It is necessary to turn the power supply on again, or to turn CTLMAIN on again to release the ERR detection
mode.
24
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
OPERATION CONDITION, STOP CIRCUIT AND RELEASE CONDITION FOR
PROTECTION CIRCUIT
Channel
Operation
whilst
under
protection
Over voltage
protection
(OCP)
Under voltage lockout
protection (UVLO)
Thermal
shutdown
protection
(TSD)
DD1, DD2 Discharge
Operating condition:
After about 1ms progress in
the over current condition
Process during protection
operation:
DD1, DD2, LDO stop
Recovery condition:
(1) Power supply reasserted
(2) CTLMAIN reasserted
LDO Discharge
Operating condition:
After about 1ms progress in
the over current condition
Process during protection
operation:
DD1, DD2, LDO stop
Recovery condition:
(1) Power supply
re-asserted
(2) CTLMAIN reasserted
Operating condition: Input
voltage drop
Process during protection
operation:
DD1, DD2, LDO stop
Recovery condition: Input
voltage rise
UVLO operates only
when CTLMAIN is "H"
(normal operation).
Operating condition:
Chip temperature
increment
Process during
protection operation:
DD1, DD2, LDO
stop
Recovery condition:
(1) Power supply
reasserted
(2) CTLMAIN
reasserted
Only when
CTLMAIN is in the
"H" state and one of
CTL1, CTL2 or L is
in the "H" state, TSD
will operate.
ERR output
(ERRpin) -
"L" output when detecting
OCP at CH of DD1, DD2,
or LDO
No change "L" output when
detecting TSD
Thermal shutdown protection (TSD) operation during over current protection timer operation
When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer
operation, the thermal shutdown protection has priority.
Operation when releasing under voltage lockout protection (UVLO)
DD1, DD2 and LDO: Activation following the condition for CTL* pin
25
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DD SOFT-START OPERATION
The soft-start operation for DD1, DD2 and LDO is enabled in order to prevent the rush current during the
DD activation. The soft-start time can be controlled by I2C.
Soft-start control: enabled to set at DD1, DD2 and LDO
DD, LDO soft-start
t
Output voltage
setting value
Soft-start time
CH ON/OFF signal (internal signal)
26
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DISCHARGE OPERATION
• DD channel
When executing the DD OFF operation at the CH ON/OFF signal, the DC/DC smooth capacitance charged
for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage
is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current.
The discharge time is calculated by the following equation.
Discharge time (time till the output becomes 10% without load)
toff(s) ≈ 2.3 × RDIS × Cout(F)
Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value.
Error
Amp
0.6V
R1
R2
INx
CH ON/OFF Cont.
A
PVCCX
PGNDx
A
Resistor for discharge
Cout
LXx
• LDO channel
When executing the LD OFF operation at the CH ON/OFF signal, the output capacitance charged for the
output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is
decreased gradually. However, the discharge time changes depending on the output load current. The
discharge time is calculated by the following equation.
Discharge time (time till the output becomes 10% without load).
toff(s) ≈ 2.3 ×RDIS× Cout(F)
Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value.
LDO
PVCCL
0.6V
CH ON/OFF Cont.
Resistor for discharge
+
-
Cout
27
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PG1/PG2/PGL PIN AND ERR PIN
The following pins for each CH POWER GOOD output are prepared.
PG1
It is the pin for DD1 POWER GOOD output.
When the output voltage exceeds 85% of the setting value at the DD1 ON mode, "H" is output.
Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H"
output, "L" is output.
"L" is output at the DD1 OFF mode.
PG2
It is the pin for DD2 POWER GOOD output.
When the output voltage exceeds 85% of the setting value at the DD2 ON mode, "H" is output.
Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H"
output, "L" is output.
"L" is output at the DD2 OFF mode.
PGL
It is the pin for LDO POWER GOOD output.
When the output voltage exceeds 85% of the setting value at the LDO ON mode, "H" is output.
Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H"
output, "L" is output.
"L" is output at the LDO OFF mode.
The following pin for the error state output is prepared.
ERR pin
It is the pin for the error state output. "L" is output during the error detection mode.
The ERR detection mode is released by turning on the power supply or CTLMAIN again.
28
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
I2C INTERFACE
1. Structure of I2C interface
The I2C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL
(serial clock line) and a SDA (serial data line).
This bus is connected to multiple devices;
master: device to generate the clock signal and to control the data transfer (CPU and so on)
slave: device that an address is specified by a master.
This IC is set as the slave and has no function to be the master.
Each device is defined due to the communication direction as described below.
transmitter: device to send data to bus
receiver: device to receive data from bus
The IC has the function both transmitter and receiver.
SCL
SDA
master slave1
transmitter transmitter
receiver receiver
slave2
The IC defines the followings;
Write : data is transmitted from master and the IC receives data
Read : The IC transmits data and master receives data.
2. Definition of signal lines
SCL and SDA are connected to the power supply by the pull-up resistor.
The output circuit is the open Drain output.
When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state.
Note: SCL and SDA pins adopt a different ESD protection system from standard I2C specification because of
ESD enhancement (see I/O CIRCUIT TYPE).
When the power supply is in the bus line, don't shut off the power supply for an IC (VCCI2C).
SCL
SDA
I
2
C bus line power supply
RPull-up
R
input
Inside of IC
input
outpu
t
29
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
3. Validity of data
Data has the following characteristics;
change when SCL is the "L" level
valid if the state is kept while SCL is the "H" level.
SCL
SDA
data
state
data
change
data
state
Moreover, the SDA signal change means the start or stop condition when SCL is the "H" level.
4. Definition of start and stop condition
The start and stop conditions are output from the master and shows start and stop of communications to the
slave.
Start : SDA changes from "H" to "L" when SCL is "H".
Stop : SDA changes from "L" to "H" when SCL is "H".
S
D
A
S
C
L
P
stop
condition
S
start
condition
30
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
5. ACK signal
This is a signal to confirm the data reception during communication.
The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of
data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the
master generates.
A transmitter keeps SDA output "open H" in SCL9clk.
A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 clk ;
when data was received : SDA output "L" (ACK)
when no data was received : SDA output "open H" (NACK)
However, if the master is changed to the receiver, ACK is not replied after the last data reception because the
bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter
opens the bus (open H) and is set to the stop condition reception waiting state from the master.
SCL
from master
SDA
by transmitter
SDA
by receiver
1
bit0 bit7 H hold
NACK
ACK
bit0
8910
31
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
6. I2C Interface Input Timing
(within recommended operating conditions)
Value
SCL=100kHz SCL=400kHz
Parameter Symbol
Min Max Min Max
Unit
SCL clock frequency fSCL - 100 - 400 kHz
Start condition hold time tHD:start 4.0 - 0.6 - μs
Restart condition setup time tSU:start 4.7 - 0.6 - μs
Stop condition setup time tSU:stop 4.0 - 0.6 - μs
Stop to Start bus open time tbuf 4.7 - 1.3 - μs
SCL "L" time tLow 4.7 - 1.3 - μs
SCL "H" time tHigh 4.0 - 0.6 - μs
SCL/SDA rising time tr - 1.0 - 0.3 μs
SCL/SDA falling time tf - 0.3 - 0.3 μs
Data hold time tHD:data 0.0 - 0.0 - μs
Data setup time tSU: data 0.25 - 0.10 - μs
SCL/SDA capacitor load Cb - 400 - 400 pF
VIH/VIL level reference
Conform to I2C bus specifications
SCL
SPSr
tr tf
t
HD:start
t
High
t
Low
t
SU:data
t
HD:data
t
SU:start
t
SU:stop
t
buf
SDA
32
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
7. Slave Address
This is a slave address when communicating with the I2C interface.
The slave address of this IC is set by the first seven bits as shown below.
The seventh bit follows the ADDSEL pin and "0"/"1" are variable.
The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0"
shows that information will be written from the master to the slave.
The bit "1" shows that the master reads information from the slave.
This does not support the general call address.
When the ADDSEL pin is in "H"
When the ADDSEL pin is in "L"
S
T
A
R
T MSB LSB
11 1 R/W
1
0
1
0
S
T
O
P
slave address
S
T
A
R
T MSB LSB
11 0 R/W
1
0
1
0
S
T
O
P
slave address
33
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
8. Bit structure of data on I2C interface
(1) Writing data to register and reading data
The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit
(LSB).
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
No. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
0S P1111 1W0 1 000000 0 gabcde f h
slave address register address data
*When the ADDSEL pin is in "H"
Register
DATA
D
07 D
06 D
05 D
04 D
03 D
02 D
01 D
00
00H
01H
02Ha b c d e f g h
address 10H
11H
..
..
Output the "stop" condition after sending the Write data.
34
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
(2) I2C Interface Data Format
I2C communication
1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving
the slave address.
2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting.
3. If a non-existing register address is specified, data is not written to a register.
4. Output the "stop" condition after sending the write data.
< During write (W)>
S0101111W P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
O
P
slave address register address DATA 1 data
: Signal that master sends
: Signal that the IC sends
*When the ADDSEL pin is in "H"
Write is allowed per one address. (sequential writing is not allowed.)
Send register address and data as one unit.
< During read (R) >
S0101111W S0101111R P
A
C
K
S
T
A
R
T
S
T
A
R
T
S
T
O
T
A
C
K
A
C
K
A
C
K
slave address slave address data
register address
: Signal that master sends
: Signal that the IC sends
*When the ADDSEL pin is in "H" *When the ADDSEL pin is in "H"
Read is allowed per one address. Be sure to perform read by specifying the register addresses.
(sequential reading is not allowed.)
35
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
STRUCTURE OF I2C INTERFACE AND DATA
Register map
DATA
address d07 d06 d05 d04 d03 d02 d01 d00 Default
Writing
timing Remarks
00H X X X X D03 D02 D01 D00
00H*
05H*
0AH*
0FH*
ACK DD1 output voltage
setting
01H X X X X D03 D02 D01 D00
00H*
03H*
06H*
0CH*
ACK DD2 output voltage
setting
Output
voltage
02H X X X X X X D01 D00 03H ACK
LDO output voltage
setting
10H X X X X D03 D02 D01 D00 01H ACK
DD1 soft-start time
setting
11H X X X X D03 D02 D01 D00 01H*/
03H* ACK DD2 soft-start time
setting
Soft
start
12H X X X X D03 D02 D01 D00 03H ACK
LDO soft-start time
setting
DD
operation
mode
20H X X X X X X D01 D00 00H ACK
DD1, DD2 operation
mode setting
"0": Fixed PWM mode,
"1": PFM/PWM mode
ON/OFF 30H X X X X X D02 D01 D00 00H ACK
DD1, DD2, LDO
output ON/OFF setting
"0":Output OFF/
"1":Output ON
For test FXH - - - - - - - - - - Disabled
*: The value depends on the preset value.
Because the "X" block in the register map has no register, "0" is returned when in reading.
The address FXH is used for tests. It is normally disabled.
Don't read/write to the FXH address.
36
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
(1) DD1 and DD2 output voltage control
1. Addresses 00H, 01H are allocated as registers for the DC/DC output voltage control.
2. The DC/DC output voltage control is controlled by writing data to addresses 00H, 01H.
DATA
MSB LSB
S
T
A
R
T
S
T
O
P
A
C
K
0000D
03
D
02
D
01
D
00
address 00H : For DD1 output voltage setting
address 01H : For DD2 output voltage setting
D
03 to D00: Set the output voltage
*: The selectable output voltage setting as preset value.
DD1 output voltage setting table DD2 output voltage setting table
DATA Output voltage DATA Output voltage
00H 1.00*
00H 1.20*
01H 1.02
01H 1.25
02H 1.04
02H 1.30
03H 1.06
03H 1.35*
04H 1.08
04H 1.40
05H 1.10*
05H 1.45
06H 1.12
06H 1.50*
07H 1.14
07H 1.55
08H 1.16
08H 1.60
09H 1.18
09H 1.65
0AH* 1.20*
0AH 1.70
0BH 1.22
0BH 1.75
0CH 1.24
0CH* 1.80*
0DH 1.26
0DH 1.85
0EH 1.28
0EH 1.90
0FH 1.30*
[V] 0FH 1.95 [V]
37
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
(2) LDO output voltage control
1. Address 02H is allocated as a register for the LDO output voltage control.
2. The LDO output voltage control is controlled by writing data to addresse 02H.
MSB
DATA
LSB
S
T
A
R
T
S
T
O
P
D
01
000000 D
00
A
C
K
address 02H: For LDO output voltage setting
D
01 to D00: Set the output voltage
LDO output voltage setting table
DATA Output voltage
00H 2.80
01H 2.85*
02H 3.00
03H* 3.30*
[V]
*: The selectable output voltage using the preset value changing products
38
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
(3) Soft start time
1. Address 10H to 12H are allocated as registers for the soft start time control.
2. The soft start time control is controlled by writing data to addresses 10H to 12H.
MSB
DATA
LSB
S
T
A
R
T
S
T
O
P
D
01
00D
03
D
02
00 D
00
A
C
K
address10H: For DD1 soft start time setting
address11H: For DD2 soft start time setting
address12H: For LDO soft start time setting
D
03 to D00: Set the soft start time
Soft start time setting table
DATA1 Soft start time Default setting
00H 14.3mS
01H 0.9mS DD1, DD2
02H 1.8mS
03H 2.7mS LDO
04H 3.6mS
05H 4.5mS
06H 5.4mS
07H 6.3mS
08H 7.2mS
09H 8.1mS
0AH 9.0mS
0BH 9.9mS
0CH 10.8mS
0DH 11.6mS
0EH 12.5mS
0FH 13.4mS
39
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
(4) DC/DC operation mode
1. Address 20H is allocated as a register for the DC/DC operation mode control.
2. The DC/DC operation mode is controlled by writing data to address 20H.
MSB
DATA
LSB
S
T
A
R
T
S
T
O
P
D01
000000 D00
A
C
K
address20H: For DC/DC operation mode setting
D
01 to D00: Set the DC/DC operation mode
address Bit Value Description Value Description
20H D00 0* DD1 Fixed PWM* 1 DD1 PFM/PWM
20H D01 0* DD2 Fixed PWM* 1 DD2 PFM/PWM
*: It is a preset value.
(5) ON/OFF for DC/DC and LDO
1. Address 30H is allocated as a register for the DC/DC and LDO ON/OFF.
2. The DC/DC and LDO ON/OFF is controlled by writing data to address 30H.
MSB
DATA
LSB
S
T
A
R
T
S
T
O
P
000D
02
D
01
00 D
00
A
C
K
address30H: For DC/DC and LDO ON/OFF
D
02 to D00: Set ON/OFF for DC/DC and LDO
address Bit Value Description Value Description
30H D00 0* DD1 output OFF* 1 DD1 output ON
30H D01 0* DD2 output OFF* 1 DD2 output ON
30H D02 0* LDO output OFF* 1 LDO output ON
*: It is a preset value.
40
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
I/O PIN EQUIVALENT CIRCUIT DIAGRAM
<<VCC>>
VCC
GND
ESD
protection
element
VCC
VREF
GND
VR
GND
VREF
VCC
<<Output block (DD1,2)>>
LXx
PVCCx
VCC
GND
<<IN1,2>>
INx,LXx,PGNDx
:each channel
INx
VCC
GND
LXx
PGNDx
<<PVCCL/LDO>>
VCC
LDO
GND
PVCCL
LDO_S
<<Reference voltage block VREF>> <<Reference voltage block VR>>
PGNDx
PVCCx,PGNDx,VODDx
: each channel
41
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
I/O CIRCUIT TYPE
CTLMAIN/CTL1/CTL2/CTLL/ADDSEL pins
VCC
CTL*
ADDSEL
GND
SCL pin
VCCI2C
SCL
GND
SDA pin
V
CCI2C
SDA
GND
PG1/PG2/PGL/ERR pins
GND
VCC
PG*/ERR
42
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
TYPICAL OPERATION CHARACTERISTIC MEASUREMENT CIRCUIT
LDO:2.80V/2.85V/
3.00V/3.30V
Io(Max):250mA
Vo1:1.00V to 1.30V
Io(Max):1400mA
(20mV step)
(50mV step)
VCC:2.5V to 5.5V
C3
4.7μF
L1
C10
10μ
R1
100k
C9
10μ
C5
4.7μFC8
4.7μ
C1
0.1μF
C2
0.1μF
C7
0.47μF
C6
0.1μF
R2
100k
R3
100k
VREF VR GNDGND
R4
100k
MB39C031
SCL
SDA
3.3V
3.3V
3.3V
3.3V
3.3V
C4
4.7μF
L2
ERR
PGL
PG2
PG1
Vo2:1.20V to 1.95V
Io(Max):600mA
PVCCL
PVCC1
CTL1
CTLL
VCC
VCC
CTLMAIN
VCCI2C
SCL
SDA
ADDSEL
PVCC2
CTL2
LDO
LX1
PGND1
PG1
LX2
PGND2
PG2
PGL
IN1
IN2
ERR
43
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
Part list
Symbol
(Circuit diagram notation) Parts Part number Specifications Vendor
L1 Metal alloy inductor 1299AS-H-1R5N 1.5μH TOKO
L2 Metal alloy inductor 1299AS-H-1R5N 1.5μH TOKO
C1 Ceramic Capacitor C1608X5R1H104K 0.1μF TDK
C2 Ceramic Capacitor C1608X5R1H104K 0.1μF TDK
C3 Ceramic Capacitor C1608X5R1V475K 4.7μF TDK
C4 Ceramic Capacitor C1608X5R1V475K 4.7μF TDK
C5 Ceramic Capacitor C1608X5R1V475K 4.7μF TDK
C6 Ceramic Capacitor C1608X5R1H104K 0.1μF TDK
C7 Ceramic Capacitor C1608X5R1H474K 0.47μF TDK
C8 Ceramic Capacitor C1608X5R1V475K 4.7μF TDK
C9 Ceramic Capacitor C1608X5R1A106K 10μF TDK
C10 Ceramic Capacitor C1608X5R1A106K 10μF TDK
R1 Resistor RR0816P-104-D 100kΩ SSM
R2 Resistor RR0816P-104-D 100kΩ SSM
R3 Resistor RR0816P-104-D 100kΩ SSM
R4 Resistor RR0816P-104-D 100kΩ SSM
TOKO : TOKO, INC.
TDK : TDK Corporation
SSM : SUSUMU CO., LTD.
Note: The list above is recommended parts.
44
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
REFERENCE DATA
DC/DC Load efficiency characteristics
• DD1
Vo=1.0V (Min) Vo=1.2V Vo=1.3V (Max)
Load efficiency Load efficiency Load efficiency
Vin=2.5V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load efficiency Load efficiency Load efficiency
Vin=3.6V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load efficiency Load efficiency Load efficiency
Vin=5.5V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
45
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2
Vo=1.2V (Min) Vo=1.8V Vo=1.95V (Max)
Load efficiency Load efficiency Load efficiency
Vin=2.5V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load efficiency Load efficiency Load efficiency
Vin=3.6V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load efficiency Load efficiency Load efficiency
Vin=5.5V
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Efficiency[%]
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
46
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DC/DC line efficiency characteristics
• DD1
Vo=1.0V (Min) Vo=1.2V Vo=1.3V (Max)
Line efficiency
characteristics (Io=400mA)
Line efficiency characteristics
(Io=400mA)
Line efficiency
characteristics (Io=400mA)
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Input voltage Vin[V] Input voltage Vin[V] Input voltage Vin[V]
• DD2
Vo=1.2V (Min) Vo=1.8V Vo=1.95V (Max)
Line efficiency
characteristics (Io=400mA)
Line efficiency characteristics
(Io=400mA)
Line efficiency
characteristics (Io=400mA)
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Efficiency[%]
60
65
70
75
80
85
90
95
100
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fixed PWM
PFMPWM
Input voltage Vin[V] Input voltage Vin[V] Input voltage Vin[V]
47
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DC/DC line regulation characteristics
• DD1
Vo=1.0V (Min) Vo=1.2V Vo=1.3V (Max)
Line regulation
(Io=400mA)
Line regulation
(Io=400mA)
Line regulation
(Io=400mA)
Output voltage Vout[V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Output voltage Vout[V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Output voltage Vout[V]
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Input voltage Vin[V] Input voltage Vin[V] Input voltage Vin[V]
• DD2
Vo=1.2V (Min) Vo=1.8V Vo=1.95V (Max)
Line regulation
(Io=400mA)
Line regulation
(Io=400mA)
Line regulation
(Io=400mA)
Output voltage Vout[V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Output voltage Vout[V]
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Output voltage Vout[V]
1.930
1.935
1.940
1.945
1.950
1.955
1.960
1.965
1.970
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Fixed PWM
PFMPWM
Input voltage Vin[V] Input voltage Vin[V] Input voltage Vin[V]
LDO line regulation characteristics
• LDO
Vo=2.8V (Min)
Vo=3.3V (Max)
Line regulation
(Io=50mA)
Line regulation
(Io=50mA)
Output voltage Vout[V]
2.740
2.760
2.780
2.800
2.820
2.840
2.860
3 3.5 4 4.5 5 5.5
Output voltage Vout[V]
3.240
3.260
3.280
3.300
3.320
3.340
3.360
3 3.5 4 4.5 5 5.5
Input voltage Vin[V]
Input voltage Vin[V]
48
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DC/DC load regulation characteristics
• DD1
Vo=1.0V (Min) Vo=1.2V Vo=1.3V (Max)
Load regulation Load regulation Load regulation
Vin=2.5V
Output voltage [V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0 0.2 0.4 0.6 0.8 11.21.41.6
Fixed PWM
PFMPWM
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fixed PWM
PFMPWM
Output voltage [V]
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.
6
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load regulation Load regulation Load regulation
Vin=3.6V
Output voltage [V]
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fixed PWM
PFMPWM
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fixed PWM
PFMPWM
Output voltage [V]
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.
6
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load regulation Load regulation Load regulation
Vin=5.5V
Output voltage [V]
0
.980
0
.985
0
.990
0
.995
1.000
1.005
1.010
1.015
1.020
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fixed PWM
PFMPWM
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Fixed PWM
PFMPWM
Output voltage [V]
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.
6
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
49
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2
Vo=1.2V (Min) Vo=1.8V Vo=1.95V (Max)
Load regulation Load regulation Load regulation
Vin=2.5V
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Output voltage [V]
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 0.10.20.30.40.50.60.7
Fixed PWM
PFMPWM
Output voltage [V]
1.930
1.935
1.940
1.945
1.950
1.955
1.960
1.965
1.970
0 0.10.20.30.40.50.60.7
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load regulation Load regulation Load regulation
Vin=3.6V
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Output voltage [V]
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Output voltage [V]
1.930
1.935
1.940
1.945
1.950
1.955
1.960
1.965
1.970
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
Load regulation Load regulation Load regulation
Vin=5.5V
Output voltage [V]
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Output voltage [V]
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Output voltage [V]
1.930
1.935
1.940
1.945
1.950
1.955
1.960
1.965
1.970
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Fixed PWM
PFMPWM
Load current [A] Load current [A] Load current [A]
50
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
LDO load regulation characteristics
• LDO
Vo=2.8V (Min)
Vo=3.3V (Max)
Load regulation
Load regulation
Vin=3.0V
Output voltage [V]
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
0 0.05 0.1 0.15 0.2 0.25
Vin=3.5V
Output voltage [V]
0 0.05 0.1 0.15 0.2 0.25
3.240
3.260
3.280
3.300
3.320
3.340
3.360
Load current [A]
Load current [A]
Load regulation
Load regulation
Vin=3.6V
Output voltage [V]
0 0.05 0.1 0.15 0.2 0.2
5
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
Vin=3.6V
Output voltage [V]
0 0.05 0.1 0.15 0.2 0.2
5
3.240
3.260
3.280
3.300
3.320
3.340
3.360
Load current [A]
Load current [A]
Load regulation
Load regulation
Vin=5.5V
Output voltage [V]
0 0.05 0.1 0.15 0.2 0.25
2.750
2.760
2.770
2.780
2.790
2.800
2.810
2.820
2.830
2.840
2.850
Vin=5.5V
Output voltage [V]
0 0.05 0.1 0.15 0.2 0.25
3.240
3.260
3.280
3.300
3.320
3.340
3.360
Load current [A]
Load current [A]
51
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DC/DC output ripple waveform
• DD1 (Fixed PWM mode)
Output voltage =1.2V setting
Io=0mA Io=400mA Io=1400mA
VIN=2.5V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
200ns
1
200ns
1
200ns
VIN=3.6V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
200ns
1
200ns
1
200ns
VIN=5.5V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
200ns
1
200ns
1
200ns
52
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD1 (PFM/PWM mode)
Output voltage =1.2V setting
Io=0mA Io=400mA Io=1400mA
VIN=2.5V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
4.0ms
1
200ns
1
200ns
VIN=3.6V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
4.0ms
1
200ns
1
200ns
VIN=5.5V
Vo1 (10.0mV/div_DC)
offset:1.200V
1
4.0ms
1
200ns
1
200ns
53
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2 (Fixed PWM mode)
Output voltage =1.8V setting
Io=0mA Io=400mA Io=600mA
VIN=2.5V
Vo2 (10.0mV/div_DC)
offset:1.800V
1
200ns
1
200ns
1
200ns
VIN=3.6V
Vo2 (10.0mV/div_DC)
offset:1.800V
1
200ns
1
200ns
1
200ns
VIN=5.5V
Vo2 (10.0mV/div_DC)
offset:1.806V
1
200ns
1
200ns
1
400ns
54
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2 (PFM/PWM mode)
Output voltage =1.8V setting
Io=0mA Io=400mA Io=600mA
VIN=2.5V
Vo2 (10.0mV/div_DC)
offset:1.800V
1
4.0ms
1
200ns
1
200ns
VIN=3.6V
Vo2 (10.0mV/div_DC)
offset:1.800V
1
4.0ms
1
200ns
1
200ns
VIN=5.5V
Vo2 (10.0mV/div_DC)
offset:1.800V
1
4.0ms
1
200ns
1
200ns
55
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DD1 startup/shutdown waveform
Output voltage =1.2V setting
Soft-start setting=0.9ms
Fixed PWM mode
Control using the external pin (CTL1)
VCC = 2.5V
Io=1400mA
Io=0mA
1
2
3
4
200μs/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(1A/div)
1
2
3
4
20ms/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(10mA/div)
VCC = 3.6V
Io=1400mA
Io=0mA
1
2
3
4
200μs/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(1A/div)
1
2
3
4
20ms/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(10mA/div)
VCC = 5.5V
Io=1400mA
Io=0mA
1
2
3
4
200μs/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(1A/div)
1
2
3
4
20ms/div
CTL1(3V/div)
PG1(3V/div)
Vo1(0.6V/div)
IIN(10mA/div)
56
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DD2 startup/shutdown waveform
Output voltage =1.8V setting
Soft-start setting=0.9ms
Fixed PWM mode
Control using the external pin (CTL2)
VCC = 2.5V
Io=600mA
Io=0mA
1
2
3
4
200μs/div
CTL2(3V/div)
PG2(3V/div)
Vo1(0.9V/div)
IIN(500mA/div)
1
2
3
4
20ms/div
CTL2(3V/div)
PG2(3V/div)
Vo2(0.9V/div)
IIN(10mA/div)
VCC = 3.6V
Io=600mA
Io=0mA
1
2
3
4
200μs/div
CTL2(3V/div)
PG2(3V/div)
Vo1(0.9V/div)
IIN(500mA/div)
1
2
3
4
20ms/div
CTL2(3V/div)
PG2(3V/div)
Vo2(0.9V/div)
IIN(10mA/div)
VCC = 5.5V
Io=600mA
Io=0mA
1
2
3
4
200μs/div
CTL2(3V/div)
PG2(3V/div)
Vo1(0.9V/div)
IIN(500mA/div)
1
2
3
4
20ms/div
CTL2(3V/div)
PG2(3V/div)
Vo2(0.9V/div)
IIN(10mA/div)
57
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
LDO startup/shutdown waveform
Output voltage =3.3V setting
Soft-start setting=2.7ms
Control using the external pin (CTLL)
VCC = 3.6V
Io=250mA
Io=0mA
1
2
3
4
1ms/div
CTLL(3V/div)
PGL(3V/div)
LDO(1.5V/div)
IIN(200mA/div)
2
1
3
4
20ms/div
CTLL(3V/div)
PGL(3V/div)
LDO(1.5V/div)
IIN(20mA/div)
VCC = 5.5V
Io=250mA
Io=0mA
1
2
3
4
1ms/div
CTLL(3V/div)
PGL(3V/div)
LDO(1.5V/div)
IIN(200mA/div)
2
3
4
1
20ms/div
CTLL(3V/div)
PGL(3V/div)
LDO(1.5V/div)
IIN(20mA/div)
58
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
DC/DC Sudden load change characteristics
• DD1(Fixed PWM mode) 0mA1400mA/10μs
Output voltage =1.2V setting
VCC=2.5V
1
4
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
10μs
1
4
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
VCC=3.6V
1
4
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
1
4
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
VCC=5.5V
1
4
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
1
4
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
59
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2 (Fixed PWM mode) 0mA600mA/10μs
Output voltage =1.8V setting
VCC=2.5V
1
4
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
1
4
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
VCC=3.6V
1
4
Vo2(50mV/div)
offset:1.800V
10μs
Io(200mA/div)
1
4
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
VCC=5.5V
1
4
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
1
4
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
60
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD1 (PFM/PWM mode) 0mA1400mA/10μs
Output voltage =1.2V setting
VCC=2.5V
4
1
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
1
4
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
VCC=3.6V
1
4
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
1
4
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
VCC=5.5V
1
4
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
1
4
a
b
10μs
Vo1(50mV/div)
offset:1.200V
Io(1.0A/div)
61
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
• DD2 (PFM/PWM mode) 0mA600mA/10μs
Output voltage =1.8V setting
VCC=2.5V
4
1
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
1
4
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
VCC=3.6V
4
1
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
1
4
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
VCC=5.5V
4
1
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
1
4
a
b
10μs
Vo2(50mV/div)
offset:1.800V
Io(200mA/div)
62
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
LDO Sudden load change characteristics
• LDO 0mA150mA/2μs
Output voltage =3.3V setting
VCC=3.6V
1
2
a
b
LDO(10mV/div)
offset:3.300V
Io(100mA/div)
5μs
1
2
a
b
5μs
LDO(10mV/div)
offset:3.300V
Io(100mA/div)
VCC=5.5V
1
2
5μs
LDO(10mV/div)
offset:3.300V
Io(100mA/div)
a
b
1
2
5μs
LDO(10mV/div)
offset:3.300V
Io(100mA/div)
a
b
Power dissipation
Power dissipation vs.
Operation ambient temperature
0.0
-50 -25 0 +25 +50 +75 +100
0.4
0.8
1.2
1.6
2.0
Pd [W]
1.72
Temperature [°C]
63
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings.
If the lC is used over the maximum ratings, the LSl may be permanently damaged.
It is preferable for the device to be normally operated within the recommended usage conditions. Usage
outside of these conditions can have a bad effect on the reliability of the LSI.
2. Use the devices within recommended operating conditions.
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device.
All of the device's electrical characteristics are warranted when the device is operated within these
ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the
data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
3. Printed circuit board ground lines should be set up with consideration for common impedance.
4. Take appropriate measures against static electricity.
Containers for semiconductor materials should have anti-static protection or be made of conductive
material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in series between body
and ground.
5. Do not apply negative voltages.
The use of negative voltages below -0.3 V may cause the parasitic transistor to be activated on LSI lines,
which can cause malfunctions.
6. When all channels are operating, the reliability level is designed under the condition that the
average ambient temperature Ta=+60°C, the typical input voltage, the typical output voltage
and the typical output current condition are used.
64
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
ORDERING INFORMATION
Part number Package Remarks
MB39C31WQN 28-pin plastic QFN
(LCC-28P-M70)
65
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PRESET CODE (MB39C031)
Preset code DD1 output voltage
preset code value
DD2 output voltage
preset code value
LDO output voltage
preset code value
111 1.00V 1.20V 2.85V
112 1.00V 1.20V 3.30V
121 1.00V 1.35V 2.85V
122 1.00V 1.35V 3.30V
131 1.00V 1.50V 2.85V
132 1.00V 1.50V 3.30V
141 1.00V 1.80V 2.85V
142 1.00V 1.80V 3.30V
211 1.10V 1.20V 2.85V
212 1.10V 1.20V 3.30V
221 1.10V 1.35V 2.85V
222 1.10V 1.35V 3.30V
231 1.10V 1.50V 2.85V
232 1.10V 1.50V 3.30V
241 1.10V 1.80V 2.85V
242 1.10V 1.80V 3.30V
311 1.20V 1.20V 2.85V
312 1.20V 1.20V 3.30V
321 1.20V 1.35V 2.85V
322 1.20V 1.35V 3.30V
331 1.20V 1.50V 2.85V
332 1.20V 1.50V 3.30V
341 1.20V 1.80V 2.85V
342 1.20V 1.80V 3.30V
411 1.30V 1.20V 2.85V
412 1.30V 1.20V 3.30V
421 1.30V 1.35V 2.85V
422 1.30V 1.35V 3.30V
431 1.30V 1.50V 2.85V
432 1.30V 1.50V 3.30V
441 1.30V 1.80V 2.85V
442 1.30V 1.80V 3.30V
66
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
EV BOARD ORDERING INFORMATION
EV boad part number EV board version No. Remarks
MB39C031-EVB-01 MB39C031-EVB-01 REV3.0
MARKING FORMAT (Lead Free version)
39C031
342 E1
XXXXXXX
XX
INDEX
Lead-free version
Preset code
67
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead-free mark
JEITA logo JEDEC logo
The part number of a lead-free product has
the trailing characters "E1".
"ASSEMBLED IN CHINA" is printed on the label
of a product assembled in China.
68
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
MB39C031 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
Recommended Reflow Condition
Item Condition
Mounting Method IR (infrared reflow), warm air reflow
Mounting times 3 times in a low
Before opening Please use it within two years after
manufacture.
From opening to the reflow Less than 7 days
Storage period
When the storage period after opening
was exceeded*
Please process within 7 days after baking
(125°C±3°C, 24H＋2H/－0H)
Baking can be performed up to two times.
Storage conditions 5°C to 30°C, 60％RH or less (the lowest possible humidity)
*: Concerning the Tape & Reel product, please transfer product to heatproof tray and so on when you perform
baking.
Also please prevent lead deforming and ESD damage during baking process.
Supplier T
P
≥ T
C
Supplier t
P
User T
P
≤ T
C
User t
P
T
C
-5°C
-5°C
T
C
T
C
Preheat Area
Time 25°C to Peak
T
smax
T
smin
Max. Ramp Up Rate = 3°C/s
Max. Ramp Down Rate = 6°C/s
Temperature
→
Time →
25
T
L
tL
tS
TP
tP
260°C or less (J-STD-020D)
TL to TP : Temperature Increase gradient 3°C/s Max.
TS : Preliminary heating 150°C - 200°C, 60s -120s
TP - tP : Peak temperature 260°C or less, within 30s
TL - tL : Main Heating 217°C, 60s - 150s
TP to TL : Cooling Increase gradient 6°C/s Max.
Time 25°C to Peak 8min Max.
69
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
PACKAGE DIMENSIONS
28-pin plastic QFN Lead pitch 0.40 mm
Package width ×
package length 4.00 mm × 4.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.04 g
28-pin plastic QFN
(LCC-28P-M70)
(LCC-28P-M70)
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C28070S-c-1-2
INDEX AREA
(.157±.004)
4.00±0.10
4.00±0.10
(.157±.004)
2.40±0.10
0.40(.016)
TYP
(.016±.002)
0.40±0.05
1PIN CORNER
(C0.35(C.014))
0.20±0.05
(.008±.002)
(.030±.002)
0.75±0.05
(0.20(.008))
(.094±.004)
2.40±0.10
(.094±.004)
+0.03
–0.02
–.001
+.001
0.02
(.001 )
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
70
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
71
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
72
FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.0
MB39C031
DS405-00015-1v0-E
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR")
reserves the right to make changes to the information contained in this document without notice. Please contact your
FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented
solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU
SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to such
information, including, without limitation, quality, accuracy, performance, proper operation of the device or
non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device based on
such information, you must assume any responsibility or liability arising out of or in connection with such information or
any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any damages whatsoever arising
out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or
any other intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express
or implied. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual
property rights or other rights of third parties resulting from or in connection with the information contained herein or use
thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other
loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass
transport control system, medical life support system and military application), or (2) for use requiring extremely high
level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU
SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in
connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs
and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures
into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and
other abnormal operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade
Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are
responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and
technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Mouser Electronics
Authorized Distributor
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MB39C031WQN-G-132-JNEFE1 MB39C031WQN-G-442-JNEFE1 MB39C031WQN-G-112-JNEFE1 MB39C031WQN-
G-232-JNEFE1 MB39C031WQN-G-221-JNEFE1 MB39C031WQN-G-431-JNEFE1 MB39C031WQN-G-312-JNEFE1
MB39C031WQN-G-141-JNEFE1 MB39C031WQN-G-331-JNEFE1 MB39C031WQN-G-441-JNEFE1 MB39C031WQN-
G-422-JNEFE1 MB39C031WQN-G-212-JNEFE1 MB39C031WQN-G-322-JNEFE1 MB39C031WQN-G-311-JNEFE1
MB39C031WQN-G-131-JNEFE1 MB39C031WQN-G-242-JNEFE1 MB39C031WQN-G-111-JNEFE1 MB39C031WQN-
G-411-JNEFE1 MB39C031WQN-G-211-JNEFE1 MB39C031WQN-G-321-JNEFE1 MB39C031WQN-G-122-JNEFE1
MB39C031WQN-G-241-JNEFE1 MB39C031WQN-G-432-JNEFE1 MB39C031WQN-G-421-JNEFE1 MB39C031WQN-
G-341-JNEFE1 MB39C031WQN-G-412-JNEFE1 MB39C031WQN-G-121-JNEFE1 MB39C031WQN-G-222-JNEFE1
MB39C031WQN-G-231-JNEFE1
