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FUJITSU SEMICONDUCTOR DATA SHEET DS405-00015-1v0-E ASSP for Power Management Applications 2ch Buck DC/DC Converter + 1ch LDO with I2C interface and SW FET MB39C031 DESCRIPTION The MB39C031 contains 2ch buck DC/DC converter and 1ch LDO. It is possible to supply the main power supply line in a system by using only one chip. The current mode system is adopted for the DC/DC converter, and it is possible to use the chip inductor with the high switching frequency operation which contains internal SW FET. The MB39C031 contains the output setting resistor and the the phase compensation circuit, and contributes to reduce the number of external components and the mounting area. Also, it contains the CTL input pin which can control the ON/OFF for each CH, the Power Good signal output pin and the I2C communication interface, therefore it is easy to design the power supply sequence. It is possible to tune in the output voltage exactly using the I2C communication and possible to correspond to the DVS/ASV system. FEATURES Operating input voltage range:2.5V to 5.5V (Maximum rating: 7V) Output voltage setting range, Maximum output current: DD1*:1.0V to 1.3V (20mV/step), 1.4A (DC) DD2*:1.2V to 1.95V (50mV/step), 0.6A (DC) LDO:2.8V/2.85V/3.0V/3.3V, 0.25A (DC) Note: Each channel has selective preset voltage (Lineup for a total of 32 kinds) . Soft-start time setting range: 0.9ms to 14.3ms (approximately 0.9ms/step) Switching frequency for the DC/DC block:3MHz (fixed) Communication interface: I2C (ON/OFF, Output voltage, Soft-start time setting) Built-in PFM/PWM auto switching mode Built-in function: Output setting resistor, Phase compensation circuit, Discharge resistor, Soft-start Each Channel Power Good output function (Open-drain) Protection function: Under voltage lockout protection circuit (UVLO), Over current protection circuit (OCP), Thermal shutdown protection circuit (TSD) Error signal output pin installed (Open-drain) Small package: QFN28 (4mm x 4mm x 0.8mm, 0.4mm pitch) *: DD1,DD2 : DC/DC converter block 1, 2 APPLICATION Network equipment: Wifi-tuner, Surveillance camera Data-storage device: HDD, SSD, Picture recording equipment Image and voice output equipment: MFP, Printer, Scanner, Projector, Electrophone, STB Various terminals: POS, FA, HEMS etc. Copyright(c)2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.11 FUJITSU SEMICONDUCTOR CONFIDENTIAL r1.1 MB39C031 APPLICATION CIRCUIT EXAMPLE Vin 5.0V MB39C031 4.7F 4.7F 0.1F PVCC1 PVCC2 PVCCL LX1 IN1 PGND1 VCC VCC LX2 IN2 PGND2 4.7F 0.1F CTL1 CTL2 CTLL CTLMAIN I2C Signal VCCI2C SCL SDA ADDSEL 0.1F VR VREF LDO Vo1 1.2V 1.4A 10F 1.5H CTL Signal 0.47F 1.5H Vo2 1.8V 0.6A 10F LDO 3.3V 0.25A 10F 100k 100k 100k 100k PG1 PG2 PGL ERR GND GND 2 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 RECOMMENDED APPLICATION SPECIFICATIONS [Input Voltage Range] Input voltage VCC (V) Min Typ Max 2.5 3.6 5.5 [Output Specification] Accuracy Symbol Channel (Ta=+25C) Output Limit Output voltage current Current (V) (mA) (mA) Min Typ Max Max Min Vo1 1.2% Switching Output Soft-start Discharge Coil frequency capacitance time resistance (H) (MHz) (F) (ms) (k) 0.99* 1.00* 1.01* 14.3 1.01 1.02 1.03 0.9* 1.03 1.04 1.05 1.8 1.05 1.06 1.07 2.7 1.07 1.08 1.09 3.6 1.09* 1.10* 1.11* 4.5 1.11 1.12 1.13 DD1 Mode 1.13 1.14 1.15 1.15 1.16 1.17 5.4 Buck 1400 2000 1.17 1.18 1.19 (synchronous rectification) C-mode 3.0 1.5 10 Vo2 1.2% 7.2 9.0 1.21 1.22 1.23 9.9 1.23 1.24 1.25 10.8 1.24 1.26 1.28 11.6 1.26 1.28 1.30 12.5 1.28* 1.30* 1.32* 13.4 1.19* 1.20* 1.21* 14.3 1.24 1.25 1.27 0.9* 1.28 1.30 1.32 1.8 1.33* 1.35* 1.37* 2.7 1.38 1.40 1.42 3.6 1.43 1.45 1.47 4.5 1.48* 1.50* 1.52* Buck 5.4 1.53 1.55 1.57 (synchronous rectification) C-mode 1.58 1.60 1.62 1.63 1.65 1.67 5 8.1 1.19* 1.20* 1.21* DD2 6.3 600 900 3.0 1.5 10 6.3 7.2 8.1 1.68 1.70 1.72 9.0 1.73 1.75 1.77 9.9 1.78* 1.80* 1.82* 10.8 1.83 1.85 1.87 11.6 1.88 1.90 1.92 12.5 1.93 1.95 1.97 13.4 5 Remarks Built-in SW FET Built-in output setting resistors Operation mode switching (Fixed PWM, PFM/PWM) Built-in SW FET Built-in output setting resistors Operation mode switching (Fixed PWM, PFM/PWM) DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 3 r1.0 Accuracy Symbol Channel MB39C031 LDO LDO 1.8% Output Limit Output voltage current Current (V) (mA) (mA) Min Typ Max Max Mode Min Switching Output Soft-start Discharge Coil frequency capacitance time resistance (H) (MHz) (F) (ms) (k) 2.75 2.80 2.85 14.3 2.80* 2.85* 2.90* 0.9 2.95 3.00 3.05 1.8 3.24* 3.30* 3.36* 2.7* - - - 3.6 - - - 4.5 - - - 5.4 - - - - - - - - - 8.1 - - - 9.0 - - - 9.9 - - - 10.8 250 300 LDO - - 4.7 6.3 7.2 - - - 11.6 - - - 12.5 - - - 13.4 Remarks 5 *: Preset value Note: It is possible to set the output voltage and to change the soft-start time using I2C. 4 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 PIN ASSIGNMENT VCC ERR PVCCL LDO PGL CTLL GND (TOP VIEW) 28 27 26 25 24 23 22 CTL1 1 21 CTL2 PG1 2 20 PG2 PGND1 3 19 PGND2 LX1 4 18 LX2 PVCC1 5 17 PVCC2 IN1 6 16 IN2 CTLMAIN 7 15 VREF Top View 11 12 13 14 ADDSEL GND VR VCCI2C 10 SDA 9 SCL 8 VCC EP(Exposed Pad) (LCC-28P-M70) DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 5 r1.0 MB39C031 PIN DESCRIPTIONS (PKG) Pin No I/O IN1 1 6 I DD1*Output voltage feedback pin. - GND connection - - - PVCC1 1 5 - DD1*Output block power supply pin - VCC connection - - - LX1 1 4 O DD1*Pin for inductance connection. - Open - - - PG1 1 2 O DD1*POWERGOOD output pin - Open - - - PGND1 1 3 - DD1*Output block ground pin - GND connection - - - IN2 1 16 I DD2*Output voltage feedback pin. - - GND connection - - PVCC2 1 17 - DD2*Output block power supply pin - - VCC connection - - LX2 1 18 O DD2*Pin for inductance connection. - - Open - - PG2 1 20 O DD2*POWERGOOD output pin - - Open - - PGND2 1 19 - DD2*Output block ground pin - - GND connection - - PVCCL 1 26 - LDO*Power supply pin - - - VCC connection - LDO 1 25 O LDO*Output pin - - - Open - PGL 1 24 O LDO*POWERGOOD output pin - - - Open - CTL1 1 1 I DD1 Control pin Open - - - CTL2 1 21 I DD2 Control pin - Open - - CTLL 1 23 I LDO Control pin - - Open - CTLMAIN 1 7 I Control pin for common block and digital block * - - - - ERR 1 27 O ERR signal output pin - - - - - VCCI2C 1 9 - Power supply pin for I2C. - - - - GND connection SCL 1 10 I I2C clock pin x - - - Open SDA 1 11 I/O I2C data I/O pin x - - - Open ADDSEL 1 12 I - - - Open Circuit Pin name block DD1 DD2 LDO CTL ERR I2 C PAD PullPAD PAD PAD treatment down treatment treatment treatment when not resista when not when not when not using I2C nce using DD1 using DD2 using LDO communic ation Numb er of pin for PKG Description (PKG) Switch pin for slave address 6 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 Pin No I/O VCC 2 8, 28 - Control circuit block power supply pin - - - - - VREF 1 15 O Reference voltage (2.4V) output pin - - - - - VR 1 14 O Reference voltage (0.6V) output pin - - - - - GND 2 13, 22 - Control circuit block ground pin - - - - - GND 1 EP - Ground pin - - - - - Circuit Pin name block Common - PAD PullPAD PAD PAD treatment down treatment treatment treatment when not resista when not when not when not using I2C nce using DD1 using DD2 using LDO communic ation Numb er of pin for PKG Description (PKG) *: When turning on DD1, DD2 and LDO, it is also necessary to set CTLMAIN to "H". See OPERATION MODE LIST for the details. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 7 r1.0 MB39C031 BLOCK DIAGRAM IN1 PVCC1 <<DD1>> VCC:2.5V to 5.5V L Priority A VCC VCC VCC ErrAMP ctl1 DEC UVLO POR PWM Logic AST Control ICOMP 0.6V A LX1 LV CNV Vo1:1.00V to 1.30V (20mV step) Io(Max):1400mA PGND1 SLP PG1 IN2 scp1 cs1 vsel1 clk1 PVCC2 <<DD2>> L Priority B VCC VCC VCC ErrAMP ctl2 0.6V DEC UVLO POR B PWM Logic AST Control ICOMP LX2 LV CNV Vo2:1.20V to 1.95V (50mV step) Io(Max):600mA PGND2 SLP PG2 cs2 vsel2 scp2 clk2 PVCCL <<LDO>> LDO:2.80V/2.85V/ 3.00V/3.30V Io(Max):250mA LDO 0.6V ctll DEC UVLO POR csl vsell PGL scpl VREF CTLMAIN Logic control block ctlmain VCCI2C SCL SDA ADDSEL CTL1 ctl1 CTL2 ctl2 CTLL ctll scp1/2/l ERR SCP (counter & latch) OTP Soft-start control Output voltage switch control Common block power supply ctlmain cs1/2/l Common block vsel1/2/l VR,OSC,logic power supply VREF VCC VCC BGR UVLO VREF VREF Reference 0.6V OSC CT RT VR clk1/2 VREF (2.4V) VR GND GND : Pin (0.6V) 8 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage LX voltage Power dissipation Symbol VCC VCTL VOUT Vlogic VLX PD Condition VCC, PVCC1, PVCC2, PVCCL, VCCI2C pins CTLMAIN, 1, 2, L pins IN1, IN2 pins SDA, SCL pins LX1, LX2 pins Ta +25C Thermal resistor value (j-a):(50C/W*) Rating Unit Min Max - 7 V -0.3 7 7 7 +7 V V V V - 1720 mW Maximum junction Tjmax +125 temperature Storage temperature TSTG -55 +125 *: When mounted on a QFN28 (LCC-28P-M70) PKG, 4layers 0.8mm thickness 117mm x 84mm C C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 9 r1.0 MB39C031 RECOMMENDED OPERATING CONDITIONS Parameter General DC/DC CH LDO CH CTL block Power supply voltage Reference voltage output current Operating temperature Power supply voltage Input voltage Power supply voltage Symbol Condition Min Value Typ Max Unit VCC VCC pin 2.5 3.6 5.5 V IREF VREF pin -1 - 0 mA VR pin -1 - 0 A -30 +25 +85 C 2.5 3.6 5.5 V 0 - VCC V 3.5 3.6 5.5 V 0 - VCC V 1.76 - 3.37 V 0 - VCCI2C V IR Ta - VCC VCC, PVCC1, PVCC2 pins VOUT IN1, IN2 pins VCC VCC, PVCCL pins Output voltage setting: default (3.3V) Input VCTL voltage Power supply VCC Digital voltage block Logic (I2C) input Vlogic voltage *: CTLMAIN, CTL1, CTL2, CTLL CTL* pin VCCI2C pin SDA, SCL pin WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 10 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 ELECTRICAL CHARACTERISTICS 1. Common Block (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter Reference Voltage Block [VR, VREF] Under Voltage Lockout Protection Circuit Block [VCC UVLO] Over Current Protection Circuit Block [OCP] Thermal shutdown Protection Circuit Block [TSD] Output voltage Control Block (CTL) [CTL] Hysteresis width VH Timer time tOCP1 Stop temperature TTSDH Input pull-down resistor VR pin =0mA VREF pin =0mA VCC pin =2.5V to 5.5V VREF pin =0mA to -1mA 0.594 2.376 2.370 2.370 0.600 2.400 2.400 2.400 0.606 2.424 2.430 2.430 V V V V VCC pin = 2.156 2.20 2.244 V - 0.20 - V 0.5 1 1.5 ms - 150* - C VR VREF1 VREF2 VREF3 VTH Input current Value Typ Max Condition Threshold voltage Input voltage Min Symbol DD1, DD2, LDO Default value - VIH CTL* pin VIL CTL* pin CTL* pin =3.6V CTL* pin =0V ICTLH ICTLL RP CTL* pin IVCCS1 CTL* pin =0V CTLMAIN=3.6V IVCCS2 CTL1, CTL2.L pins =0V CTLMAIN, L pins =3.6V IVCC Only LDO operation No load CTL* pin = 3.6V all CH No load General Power supply IVCC (DD operation mode: (DC/DC block) current PFM/PWM mode) CTL* pin = 3.6V all CH No load IVCC (DD operation mode: Fixed PWM mode) CTLMAIN, L pin=3.6V IVCCI2C VCCI2C pin = 1.8V *: These are not the rated values. Use these values as reference when planning. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Unit VCC x 0.7 0 2.7 - - VCC V 3.6 - 0.4 5.1 1 V A A - 1 - M - 0 1.0 A - 80 120 A - 200 300 A - 450 680 A - 10.8 16.2 mA - 7.2 12.0 A 11 r1.0 MB39C031 2. DD1, DD2 (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter Output voltage VOUT Input stability VLINE Load stability DC/DC Converter Block [DD1] Symbol IN1 pin input impedance SW PMOS-Tr ON resistance SW NMOS-Tr ON resistance SW PMOS-Tr leak current SW NMOS-Tr leak current Overcurrent protection value PFM/PWM reshuffling electric current Discharge resistor Soft-start time Switching frequency VLOAD RIN Condition Output voltage setting: 1.2V IOUT=-10mA IOUT=-10mA, VCC=2.5V to 5.5V IOUT=-1mA to -1400mA (when in Fixed PWM mode) IOUT=-1mA to -1400mA (when in PFM/PWM mode) IN1 pin=1.5V output voltage setting: 1.2V Min Value Typ Max Unit 1.186 1.20 1.214 V -5 - +5 mV -10 - - mV -10 - +15 mV - 400 - k RPMOS LX1 pin=-30mA - 0.12* - RNMOS LX1 pin= 30mA - 0.09* - ILEAK LX1 pin=0V -1 - - A ILEAK LX1 pin=3.6V - - 1 A ILIMIT L=1.5H 2000 - - mA IPFM L=1.5H - 40* - mA RDIS tSS fOSC Preset value - 0.8 2.7 5 0.9 3.0 1.0 3.3 k ms MHz 12 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 Parameter Symbol Output voltage VOUT Input stability VLINE Load stability IN2 pin input impedance VLOAD RIN DC/DC Converter Block [DD2] Condition Output voltage setting: 1.8V IOUT=-10mA IOUT=-10mA VCC=2.5V to 5.5V IOUT=-1mA to -600mA (when in Fixed PWM mode) IOUT=-1mA to -600mA (when in PFM/PWM mode) IN2 pin =2.0V Output voltage setting: 1.8V SW PMOS-Tr ON RPMOS LX2 pin =-30mA resistance SW NMOS-Tr ON RNMOS LX2 pin = 30mA resistance SW PMOS-Tr leak ILEAK LX2 pin =0V current SW NMOS-Tr leak ILEAK LX2 pin =3.6V current Overcurrent protection ILIMIT L=1.5H value PFM/PWM reshuffling electric IPFM L=1.5H current Discharge resistor RDIS Soft-start time tSS Preset value Switching frequency fOSC *: These are not the rated values. Use these values as reference when planning. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Min Value Typ Max Unit 1.778 1.80 1.822 V -5 - +5 mV -10 - - mV -10 - +20 mV - 300 - k - 0.16* - - 0.14* - -1 - - A - - 1 A 900 - - mA - 70* - mA 0.8 2.7 5 0.9 3.0 1.0 3.3 k ms MHz 13 r1.0 MB39C031 3. LDO (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter LDO Block [LDO] Symbol Condition Output voltage VOUT Output voltage setting : 3.3V IOUT=-10mA I/O voltage difference VDIF IOUT=-10mA Input stability VLINE Load stability VLOAD Ripple remove ratio Overcurrent protection value Control macro consumption current Discharge resistor Soft-start time RR ILIMIT IOUT=-10mA, VCC=3.5V to 5.5V IOUT=-1mA to -150mA PVCCL=0.2Vrms, f=10Hz, IOUT=-150mA PVCCL=0.2Vrms, f=10kHz, IOUT=-150mA Voutx0.9 Min Value Typ Max 3.241 3.300 3.359 V - - 0.20 V -5 - +5 mV -30 -20 - mV 35 75 - dB 15 50 - dB 300 - - mA Unit IPVCCLS At stand-by - 0 1 A IPVCCL IOUT=0mA - 80 105 A RDIS tSS Preset value 2.4 5 2.7 3.0 k ms - 14 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 4. Digital Block (Ta=+25C, VCC=PVCC1, PVCC2, L=3.6V) Parameter POWER-GOOD Block [Power Good ] Error Block [ERR] Output voltage Output current Low-voltage detection Power-on detection voltage Output voltage Output current Min Value Typ Max PG1, PG2, L pins IOL=1mA - - 0.4 V IOL PG1, PG2, L pins 1 - - mA Vth IN1, IN2, LDO pins = - Vo x 0.75* - V - Vo x 0.85* - V Symbol Condition VOL Vth pins = VOL ERR pin IOL = 1mA - - 0.4 V IOL ERR pin 1 - - mA VCCI2C x 0.7 - VCCI2C V 0 - VCCI2C x 0.3 V - - 10 A -10 - - A - 0.4 V - - mA 1 - M VIH Input voltage VIL IIH I2C Block [I2C] IN1, IN2, LDO Unit Input current IIL SCL, SDA pins VCCI2C=3.3V SCL, SDA pins VCCI2C=3.3V SCL, SDA pins VCCI2C=3.3V SCL, SDA pins VCCI2C=3.3V SDA pin IOL =3mA Output VOL voltage Output IOL SDA pin 3 current Input pull-down RP ADDSEL pin resistor *: These are not the rated values. Use these values as reference when planning. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 15 r1.0 MB39C031 OPERATION MODE LIST Stand-by Stand-by 2 General ERR detection L L L L OFF OFF OFF OFF OFF OFF H L L L ON ON OFF OFF OFF OFF H H/L H/L H/L ON ON ON*2 ON/OFF ON/OFF ON/OFF H X X X ON ON OFF OFF OFF OFF I2C communication Disabled Enabled Enabled Enabled Thermal shutdown Protection (TSD) Not available Not available Available *1 Over Current Protection (OCP) Not available Not available Available *1 Mode CTL Signal Operation Block I2 C Communication Protection Operating CTLMAIN (External) CTL1 (External / I2C) CTL2 (External / I2C) CTLL (External / I2C) General Digital Block OSC, VR Block DD1 DD2 LDO *1: This is the state after detection of ERR. It is possible to release the ERR detection mode by turning the power supply on again or turning CTLMAIN on again. *2: When only LDO is operating, the OSC block stops (OFF) after LDO activation. Also, the VR block keeps operating (ON) after LDO activation. *: Priority of the external pin/I2C communication for CTL1, CTL2 and L CTLMAIN (External pin) CTL* (External pin) CTL* (I2C communication) Relevant CH H H H Unavailable H H L ON H L H ON H L L OFF L X Communication disabled OFF 2 The I C communication is enabled after the common block and digital block activation setting the external CTLMAIN pin to "H". When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the ON/OFF control using I2C. Aside from the ON/OFF control, it is possible to control everything else using I2C. When executing the ON/OFF control for DD1, DD2 and LDO using I2C, input "L" to the CTL* pin (the pin is open or in the GND connection condition). 16 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 STATE TRANSITION DIAGRAM Stand-by (1) (2) Stand-by 2 (3) (4) General (5) (6) Error detection (1) (2) (3) (4) (5) (6) External CTLMAIN pin "H" External CTLMAIN pin "L" External CTL pin "H" / I2C communication "relevant CH_ON" External CTL pin "L" / I2C communication "relevant CH_OFF" Error detection (OCP, OCP_1ms continuation) Turning on the power supply again (equal to or less than uvlo_vcc reset voltage) or setting CTLMAIN to "L" Notes: When executing the ON/OFF control for DD1, DD2 and LDO using the external pin, don't execute the ON/OFF control using I2C. Aside from the ON/OFF control, it is possible to control everything else using I2C. When executing the ON/OFF control for DD1, DD2 and LDO using I2C, input "L" to the CTL* pin (the pin is open or in the GND connection condition). DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 17 r1.0 MB39C031 TURNING ON AND OFF SEQUENCE (Turning ON CTL*:CTL1, CTL2, CTLMAIN=VCC Simultaneously) 2.0V 2.2V VCC VCCI2C 0V CTL* uvlo_vcc (IC internal signal) 2.4V VREF 90% VR 0.6V osc (IC internal signal) ctl* (IC internal signal) DD1 85% Discharge 85% Discharge PG1 DD2 PG2 UVLO release to DD*activation Time till start * Typ:200S Max:300S Soft-start time *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1F VR pin capacitance : 0.47F 18 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 CTL* TURNING ON AND OFF SEQUENCE 1 (VCC CTL*: CTL1, CTL2, CTLMAIN) VCC 3.6V VCCI2C 0V CTL* uvlo_vcc (IC internal signal) 2.4V VREF VR osc (IC internal signal) 90% 0.6V ctl* (IC internal signal) 85% Discharge 85% Discharge DD1 PG1 DD2 PG2 Turning on CTL * to DD* activation Time till start * Typ:270S Max:450S Soft-start time *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1F VR pin capacitance : 0.47F DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 19 r1.0 MB39C031 CTL* TURNING ON AND OFF SEQUENCE 2 (VCCCTLMAINCTL1CTL2) VCC 3.6V VCCI2C 0V CTLMAIN uvlo_vcc (IC internal signal) VREF CTL1 2.4V (1) 90% VR 0.6V osc (IC internal signal) ctl1 (IC internal signal) DD1 (2) Discharge 85% PG1 Soft-start time CTL2 ctl2 (IC internal signal) 85% Discharge DD2 PG2 Soft-start time (1) Time from turning on CTLMAIN to VREF activation completion (=communication enabled)* Typ: 130S, Max: 200S (2) Time from turning on CTL1 to ctll (IC internal signal) "H" Typ: 150S, Max: 250S *: VREF and VR activations depend on the VREF pin capacitance and VR pin capacitance. Time in the sequence figure above is applied for the following condition. VREF pin capacitance : 0.1F VR pin capacitance : 0.47F 20 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 CTL* PIN THRESHOLD VOLTAGE The input circuit structure for the CTL* pin is the schmitt trigger style, and the threshold voltage shows the hysteresis characteristics when CTL* OFF ON and ON OFF. (See "*CTL* pin equivalent circuit diagram" below.) Also, the threshold voltage level depends on the VCC pin voltage. Moreover, make sure to input either the "H" level (>"VCCx0.7"V) or "L" level (<0.4V) to the CTL* pin when in use. CTL* pin equivalent circuit diagram The CTL threshold voltage shows the hysteresis characteristics. VCC ESD protection element CTL* ESD protection element GND DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 21 r1.0 MB39C031 DD channel The DD channel monitors the FET current peak value at any time during the operation. When the DD output becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress. LDO channel It contains the fold-back type over current protection circuit in order to prevent destroy because of the over load and the output over current. It limits the output current and the output voltage from the peak around the over current protection value for LDO (ILIMIT) to the over current current (Is). At this time, if the output voltage Vo gets lower than the detection voltage Vd (Vd: Vox0.5), the timer operation starts and the output stops after about 1ms progress. Moreover, because the over current protection circuit does not operate at the soft-start (0V to Vo x 0.7), neither the output stops nor the error signal outputs. However, the fold-back type over current protection characteristic functions. The following shows the fold-back type over current protection characteristic. Output voltage PROTECTION OPERATION SEQUENCE Vo Output voltage setting value Vo Vox0.5 Vd Vox0.7 Vox0.9 Is ILmax ILIMIT Output current Io Soft-start t Over current protection Over current protection circuit operation circuit stop (stop output) (no stop output) Fold-back characteristic over current function (over current limit operation) Thermal shutdown protection If the temperature at the junction part reaches +150C, the thermal shutdown protection circuit turns all channels off. 22 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 Error detection sequence DD1, DD2, LDO The whoIe IC Normal operation Normal operation Over current detection Thermal shutdown protection Voltage drop No 1ms Continue for 1ms? Yes ERR detection mode ERROR signal output (ERR pin) ERR detection mode release It is necessary to turn the power supply on again, or to turn CTLMAIN on again to release the ERR detection mode. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 23 r1.0 MB39C031 OPERATION CONDITION, STOP CIRCUIT AND RELEASE CONDITION FOR PROTECTION CIRCUIT Operation whilst under protection Over voltage protection (OCP) Discharge Operating condition: After about 1ms progress in the over current condition Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted LDO Discharge Operating condition: After about 1ms progress in the over current condition Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply re-asserted (2) CTLMAIN reasserted ERR output (ERRpin) - Channel DD1, DD2 "L" output when detecting OCP at CH of DD1, DD2, or LDO Under voltage lockout protection (UVLO) Operating condition: Input voltage drop Process during protection operation: DD1, DD2, LDO stop Recovery condition: Input voltage rise UVLO operates only when CTLMAIN is "H" (normal operation). No change Thermal shutdown protection (TSD) Operating condition: Chip temperature increment Process during protection operation: DD1, DD2, LDO stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted Only when CTLMAIN is in the "H" state and one of CTL1, CTL2 or L is in the "H" state, TSD will operate. "L" output when detecting TSD Thermal shutdown protection (TSD) operation during over current protection timer operation When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal shutdown protection has priority. Operation when releasing under voltage lockout protection (UVLO) DD1, DD2 and LDO: Activation following the condition for CTL* pin 24 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 DD SOFT-START OPERATION The soft-start operation for DD1, DD2 and LDO is enabled in order to prevent the rush current during the DD activation. The soft-start time can be controlled by I2C. Soft-start control: enabled to set at DD1, DD2 and LDO DD, LDO soft-start Output voltage setting value Soft-start time CH ON/OFF signal (internal signal) t DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 25 r1.0 MB39C031 DISCHARGE OPERATION * DD channel When executing the DD OFF operation at the CH ON/OFF signal, the DC/DC smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load) toff(s) 2.3 x RDIS x Cout(F) Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value. INx A R1 PVCCX Resistor for discharge R2 A Error Amp LXx Cout 0.6V PGNDx CH ON/OFF Cont. * LDO channel When executing the LD OFF operation at the CH ON/OFF signal, the output capacitance charged for the output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the output load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load). toff(s) 2.3 xRDISx Cout(F) Note: See the table in ELECTRICAL CHARACTERISTICS for the discharge resistor value. PVCCL 0.6V + LDO Resistor for discharge Cout CH ON/OFF Cont. 26 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 PG1/PG2/PGL PIN AND ERR PIN The following pins for each CH POWER GOOD output are prepared. PG1 It is the pin for DD1 POWER GOOD output. When the output voltage exceeds 85% of the setting value at the DD1 ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H" output, "L" is output. "L" is output at the DD1 OFF mode. PG2 It is the pin for DD2 POWER GOOD output. When the output voltage exceeds 85% of the setting value at the DD2 ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H" output, "L" is output. "L" is output at the DD2 OFF mode. PGL It is the pin for LDO POWER GOOD output. When the output voltage exceeds 85% of the setting value at the LDO ON mode, "H" is output. Also, when the output voltage becomes equal to or lower than 75% of the setting value after the "H" output, "L" is output. "L" is output at the LDO OFF mode. The following pin for the error state output is prepared. ERR pin It is the pin for the error state output. "L" is output during the error detection mode. The ERR detection mode is released by turning on the power supply or CTLMAIN again. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 27 r1.0 MB39C031 I2C INTERFACE 2 1. Structure of I C interface 2 The I C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a SDA (serial data line). This bus is connected to multiple devices; master: device to generate the clock signal and to control the data transfer (CPU and so on) slave: device that an address is specified by a master. This IC is set as the slave and has no function to be the master. Each device is defined due to the communication direction as described below. transmitter: device to send data to bus receiver: device to receive data from bus The IC has the function both transmitter and receiver. SCL SDA transmitter receiver master receiver slave1 transmitter slave2 The IC defines the followings; Write : data is transmitted from master and the IC receives data Read : The IC transmits data and master receives data. 2. Definition of signal lines SCL and SDA are connected to the power supply by the pull-up resistor. The output circuit is the open Drain output. When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state. Note: SCL and SDA pins adopt a different ESD protection system from standard I2C specification because of ESD enhancement (see I/O CIRCUIT TYPE). When the power supply is in the bus line, don't shut off the power supply for an IC (VCCI2C). I2C bus line power supply R R Pull-up SCL SDA input Inside of IC 28 FUJITSU SEMICONDUCTOR CONFIDENTIAL input output DS405-00015-1v0-E r1.0 MB39C031 3. Validity of data Data has the following characteristics; change when SCL is the "L" level valid if the state is kept while SCL is the "H" level. SCL SDA data state data change data state Moreover, the SDA signal change means the start or stop condition when SCL is the "H" level. 4. Definition of start and stop condition The start and stop conditions are output from the master and shows start and stop of communications to the slave. Start : SDA changes from "H" to "L" when SCL is "H". Stop : SDA changes from "L" to "H" when SCL is "H". SCL SDA S start condition DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL P stop condition 29 r1.0 MB39C031 5. ACK signal This is a signal to confirm the data reception during communication. The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master generates. A transmitter keeps SDA output "open H" in SCL9clk. A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 clk ; when data was received : SDA output "L" (ACK) when no data was received : SDA output "open H" (NACK) However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the stop condition reception waiting state from the master. SCL from master SDA by transmitter 1 8 9 10 bit0 bit7 H hold bit0 NACK SDA by receiver ACK 30 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 2 6. I C Interface Input Timing (within recommended operating conditions) Value Parameter Symbol SCL clock frequency fSCL Start condition hold time tHD:start Restart condition setup time tSU:start Stop condition setup time tSU:stop Stop to Start bus open time tbuf SCL "L" time tLow SCL "H" time tHigh SCL/SDA rising time tr SCL/SDA falling time tf Data hold time tHD:data Data setup time tSU: data SCL/SDA capacitor load Cb VIH/VIL level reference Conform to I2C bus specifications tr S SCL=100kHz Min Max SCL=400kHz Min Max Unit 4.0 4.7 4.0 4.7 4.7 4.0 0.0 0.25 - 0.6 0.6 0.6 1.3 1.3 0.6 0.0 0.10 - kHz s s s s s s s s s s pF 100 1.0 0.3 400 400 0.3 0.3 400 tf tHigh Sr tLow P SCL tbuf SDA tHD:start tSU:data tHD:data DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL tSU:start tSU:stop 31 r1.0 MB39C031 7. Slave Address This is a slave address when communicating with the I2C interface. The slave address of this IC is set by the first seven bits as shown below. The seventh bit follows the ADDSEL pin and "0"/"1" are variable. The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will be written from the master to the slave. The bit "1" shows that the master reads information from the slave. This does not support the general call address. When the ADDSEL pin is in "H" slave address S T A R T 0 1 0 1 1 1 1 MSB R/W LSB S T O P When the ADDSEL pin is in "L" slave address S T A R T 0 1 0 MSB 32 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1 1 1 0 R/W LSB S T O P DS405-00015-1v0-E r1.0 MB39C031 2 8. Bit structure of data on I C interface (1) Writing data to register and reading data The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB). No. S T A R T slave address 1 2 3 4 5 6 7 8 A C K S 0 1 0 1 1 1 1 W register address 1 2 3 4 5 6 7 8 A C K 0 0 0 0 0 0 1 0 data 1 2 3 4 5 6 7 8 S A T C O K P a b c d e f g h P *When the ADDSEL pin is in "H" Register DATA address 00H 01H 02H 10H 11H .. .. D07 D06 D05 D04 D03 D02 D01 D00 a b c d e f g h Output the "stop" condition after sending the Write data. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 33 r1.0 MB39C031 (2) I2C Interface Data Format I2C communication 1. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address. 2. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting. 3. If a non-existing register address is specified, data is not written to a register. 4. Output the "stop" condition after sending the write data. < During write (W)> S T A R T A C K slave address register address A C K DATA 1 data S 0 1 0 1 1 1 1 W S A T C O K P P *When the ADDSEL pin is in "H" : Signal that master sends : Signal that the IC sends Write is allowed per one address. (sequential writing is not allowed.) Send register address and data as one unit. < During read (R) > S T A R T slave address A C K S T A A C R K T register address slave address A C K S 0 1 0 1 1 1 1 W S 0 1 0 1 1 1 1 R *When the ADDSEL pin is in "H" *When the ADDSEL pin is in "H" : Signal that master sends data S A T C O K T P : Signal that the IC sends Read is allowed per one address. Be sure to perform read by specifying the register addresses. (sequential reading is not allowed.) 34 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 STRUCTURE OF I2C INTERFACE AND DATA Register map address d07 d06 d05 d04 DATA d03 d02 d01 d00 Default Writing timing Remarks 00H* 00H X X X X D03 D02 D01 D00 05H* 0AH* ACK DD1 output voltage setting ACK DD2 output voltage setting 0FH* Output voltage 00H* 01H X X X X D03 D02 D01 D00 03H* 06H* 0CH* 02H X X X X X X D01 D00 03H ACK 10H X X X X D03 D02 D01 D00 01H ACK 11H X X X X D03 D02 D01 D00 01H*/ 03H* ACK 12H X X X X D03 D02 D01 D00 03H ACK DD operation mode 20H X X X X X X D01 D00 00H ACK ON/OFF 30H X X X X X D02 D01 D00 00H ACK For test FXH - - - - - - - - - - Soft start LDO output voltage setting DD1 soft-start time setting DD2 soft-start time setting LDO soft-start time setting DD1, DD2 operation mode setting "0": Fixed PWM mode, "1": PFM/PWM mode DD1, DD2, LDO output ON/OFF setting "0":Output OFF/ "1":Output ON Disabled *: The value depends on the preset value. Because the "X" block in the register map has no register, "0" is returned when in reading. The address FXH is used for tests. It is normally disabled. Don't read/write to the FXH address. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 35 r1.0 MB39C031 (1) DD1 and DD2 output voltage control 1. Addresses 00H, 01H are allocated as registers for the DC/DC output voltage control. 2. The DC/DC output voltage control is controlled by writing data to addresses 00H, 01H. DATA S T A R T 0 0 0 0 D03 D02 D01 MSB D00 LSB A C K S T O P address 00H : For DD1 output voltage setting address 01H : For DD2 output voltage setting D03 to D00: Set the output voltage DD1 output voltage setting table Output voltage DATA DD2 output voltage setting table Output voltage DATA 00H 1.00* 00H 1.20* 01H 1.02 01H 1.25 02H 1.04 02H 1.30 03H 1.06 03H 1.35* 04H 1.08 04H 1.40 05H 1.10* 05H 1.45 06H 1.12 06H 1.50* 07H 1.14 07H 1.55 08H 1.16 08H 1.60 09H 1.18 09H 1.65 0AH* 1.20* 0AH 1.70 0BH 1.22 0BH 1.75 0CH 1.24 0CH* 1.80* 0DH 1.26 0DH 1.85 0EH 1.28 0EH 1.90 0FH 1.95 [V] 0FH 1.30* *: The selectable output voltage setting as preset value. 36 FUJITSU SEMICONDUCTOR CONFIDENTIAL [V] DS405-00015-1v0-E r1.0 MB39C031 (2) LDO output voltage control 1. Address 02H is allocated as a register for the LDO output voltage control. 2. The LDO output voltage control is controlled by writing data to addresse 02H. DATA S T A R T 0 0 0 0 0 0 D01 MSB D00 LSB A C K S T O P address 02H: For LDO output voltage setting D01 to D00: Set the output voltage LDO output voltage setting table DATA Output voltage 00H 2.80 01H 2.85* 02H 3.00 [V] 03H* 3.30* *: The selectable output voltage using the preset value changing products DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 37 r1.0 MB39C031 (3) Soft start time 1. Address 10H to 12H are allocated as registers for the soft start time control. 2. The soft start time control is controlled by writing data to addresses 10H to 12H. DATA S T A R T 0 0 0 0 D03 D02 D01 D00 MSB LSB A C K S T O P address10H: For DD1 soft start time setting address11H: For DD2 soft start time setting address12H: For LDO soft start time setting D03 to D00: Set the soft start time Soft start time setting table DATA1 Soft start time 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 14.3mS 0.9mS 1.8mS 2.7mS 3.6mS 4.5mS 5.4mS 6.3mS 7.2mS 8.1mS 9.0mS 9.9mS 10.8mS 11.6mS 12.5mS 13.4mS Default setting DD1, DD2 38 FUJITSU SEMICONDUCTOR CONFIDENTIAL LDO DS405-00015-1v0-E r1.0 MB39C031 (4) DC/DC operation mode 1. Address 20H is allocated as a register for the DC/DC operation mode control. 2. The DC/DC operation mode is controlled by writing data to address 20H. DATA S T A R T 0 0 0 0 0 0 MSB D01 A C K D00 LSB S T O P address20H: For DC/DC operation mode setting D01 to D00: Set the DC/DC operation mode address Bit Value Description Value Description 20H D00 0* DD1 Fixed PWM* 1 DD1 PFM/PWM D01 *: It is a preset value. 0* DD2 Fixed PWM* 1 DD2 PFM/PWM 20H (5) ON/OFF for DC/DC and LDO 1. Address 30H is allocated as a register for the DC/DC and LDO ON/OFF. 2. The DC/DC and LDO ON/OFF is controlled by writing data to address 30H. DATA S T A R T 0 0 0 0 0 D02 D01 D00 MSB LSB A C K S T O P address30H: For DC/DC and LDO ON/OFF D02 to D00: Set ON/OFF for DC/DC and LDO address Bit 30H D00 30H D01 30H D02 *: It is a preset value. Value Description Value Description 0* 0* 0* DD1 output OFF* DD2 output OFF* LDO output OFF* 1 1 1 DD1 output ON DD2 output ON LDO output ON DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 39 r1.0 MB39C031 I/O PIN EQUIVALENT CIRCUIT DIAGRAM <<VCC>> VCC ESD protection element GND <<Reference voltage block VREF>> VCC <<Reference voltage block VR>> VCC VREF VREF VR GND GND <<IN1,2>> <<Output block (DD1,2)>> VCC VCC PVCCx INx PVCCx,PGNDx,VODDx : each channel LXx GND INx,LXx,PGNDx :each channel LXx PGNDx PGNDx GND <<PVCCL/LDO>> VCC PVCCL LDO LDO_S GND 40 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 I/O CIRCUIT TYPE CTLMAIN/CTL1/CTL2/CTLL/ADDSEL pins VCC CTL* ADDSEL GND SCL pin VCCI2C SCL GND SDA pin VCCI2C SDA GND PG1/PG2/PGL/ERR pins VCC PG*/ERR GND DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 41 r1.0 MB39C031 TYPICAL OPERATION CHARACTERISTIC MEASUREMENT CIRCUIT MB39C031 VCC:2.5V to 5.5V C1 0.1F C2 0.1F C3 4.7F VCC VCC PVCC1 LX1 CTL1 IN1 L1 R1 100k 3.3V PG1 PGND1 C4 4.7F PVCC2 LX2 CTL2 IN2 Vo1:1.00V to 1.30V (20mV step) Io(Max):1400mA C10 10 PG1 L2 Vo2:1.20V to 1.95V (50mV step) Io(Max):600mA C9 10 R2 100k 3.3V PG2 PG2 PGND2 C5 4.7F LDO PVCCL R3 100k CTLL 3.3V PGL CTLMAIN 3.3V SCL SDA LDO:2.80V/2.85V/ 3.00V/3.30V Io(Max):250mA C8 4.7 PGL R4 100k VCCI2C ERR 3.3V ERR SCL SDA ADDSEL VREF VR C6 0.1F GNDGND C7 0.47F 42 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 Part list Symbol (Circuit diagram notation) L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 R1 R2 R3 R4 TOKO : TOKO, INC. TDK : TDK Corporation SSM : SUSUMU CO., LTD. Parts Part number Specifications Vendor Metal alloy inductor Metal alloy inductor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Resistor Resistor Resistor 1299AS-H-1R5N 1299AS-H-1R5N C1608X5R1H104K C1608X5R1H104K C1608X5R1V475K C1608X5R1V475K C1608X5R1V475K C1608X5R1H104K C1608X5R1H474K C1608X5R1V475K C1608X5R1A106K C1608X5R1A106K RR0816P-104-D RR0816P-104-D RR0816P-104-D 1.5H 1.5H 0.1F 0.1F 4.7F 4.7F 4.7F 0.1F 0.47F 4.7F 10F 10F 100k 100k 100k TOKO TOKO TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK SSM SSM SSM Resistor RR0816P-104-D 100k SSM Note: The list above is recommended parts. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 43 r1.0 MB39C031 REFERENCE DATA DC/DC Load efficiency characteristics * DD1 Vo=1.0V (Min) Vo=1.2V Fixed PWM PFMPWM 1 10 Load current [A] Fixed PWM PFMPWM 0.01 Efficiency[%] Vin=3.6V Efficiency[%] PFMPWM 0.1 1 10 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM Load efficiency PFMPWM 0.1 1 Load current [A] 1 10 100 90 80 70 60 50 40 30 20 10 0 0.001 10 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM 0.1 1 Load current [A] 44 FUJITSU SEMICONDUCTOR CONFIDENTIAL 0.1 1 10 Fixed PWM PFMPWM 0.01 0.1 1 10 Load efficiency Fixed PWM 0.01 0.01 Load current [A] Load efficiency Fixed PWM 0.01 0.1 PFMPWM Load efficiency Fixed PWM 0.01 Fixed PWM Load current [A] Load current [A] Efficiency[%] Efficiency[%] Vin=5.5V Load current [A] 100 90 80 70 60 50 40 30 20 10 0 0.001 10 Load efficiency Fixed PWM 0.01 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Load current [A] Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 0.1 Efficiency[%] 0.1 Load efficiency Efficiency[%] 0.01 100 90 80 70 60 50 40 30 20 10 0 0.001 Efficiency[%] Load efficiency Efficiency[%] Efficiency[%] Vin=2.5V Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 Vo=1.3V (Max) 10 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 10 Load current [A] DS405-00015-1v0-E r1.0 MB39C031 * DD2 Vo=1.2V (Min) Vo=1.8V Fixed PWM PFMPWM 1 Load current [A] Fixed PWM PFMPWM 0.01 Efficiency[%] Vin=3.6V Efficiency[%] PFMPWM 0.1 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Load current [A] Efficiency[%] Efficiency[%] Vin=5.5V Fixed PWM PFMPWM 0.01 0.1 Load current [A] 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Load current [A] Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM 0.1 1 PFMPWM 0.1 Load current [A] DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 1 Fixed PWM PFMPWM 0.01 0.1 1 Load efficiency Fixed PWM 0.01 0.1 Load current [A] Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 PFMPWM 0.01 Load efficiency Fixed PWM 0.01 Fixed PWM Load current [A] Load efficiency Fixed PWM 0.01 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Load current [A] Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 0.1 Efficiency[%] 0.1 Load efficiency Efficiency[%] 0.01 100 90 80 70 60 50 40 30 20 10 0 0.001 Efficiency[%] Load efficiency Efficiency[%] Efficiency[%] Vin=2.5V Load efficiency 100 90 80 70 60 50 40 30 20 10 0 0.001 Vo=1.95V (Max) 1 100 90 80 70 60 50 40 30 20 10 0 0.001 Fixed PWM PFMPWM 0.01 0.1 1 Load current [A] 45 r1.0 MB39C031 DC/DC line efficiency characteristics * DD1 Vo=1.0V (Min) Vo=1.2V Line efficiency characteristics (Io=400mA) Line efficiency characteristics (Io=400mA) 100 100 95 95 95 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Efficiency[%] 100 Efficiency[%] Efficiency[%] Line efficiency characteristics (Io=400mA) Vo=1.3V (Max) 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input voltage Vin[V] Input voltage Vin[V] Input voltage Vin[V] Vo=1.2V (Min) Line efficiency characteristics (Io=400mA) Vo=1.8V Line efficiency characteristics (Io=400mA) Vo=1.95V (Max) Line efficiency characteristics (Io=400mA) 100 95 95 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 Input voltage Vin[V] 5.5 100 Efficiency[%] 100 Efficiency[%] Efficiency[%] * DD2 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 Input voltage Vin[V] 46 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.5 95 90 85 80 75 Fixed PWM 70 PFMPWM 65 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input voltage Vin[V] DS405-00015-1v0-E r1.0 MB39C031 DC/DC line regulation characteristics * DD1 Vo=1.0V (Min) Vo=1.2V Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 1.220 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 2.50 Input voltage Vin[V] Line regulation (Io=400mA) Output voltage Vout[V] 1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 2.50 Line regulation (Io=400mA) Output voltage Vout[V] Output voltage Vout[V] Line regulation (Io=400mA) Vo=1.3V (Max) Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 1.320 1.315 1.310 1.305 1.300 1.295 1.290 1.285 1.280 2.50 Input voltage Vin[V] Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] * DD2 Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 1.820 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 2.50 Input voltage Vin[V] Vo=1.95V (Max) Line regulation (Io=400mA) Output voltage Vout[V] 1.220 1.215 1.210 1.205 1.200 1.195 1.190 1.185 1.180 2.50 Vo=1.8V Line regulation (Io=400mA) Output voltage Vout[V] Output voltage Vout[V] Vo=1.2V (Min) Line regulation (Io=400mA) Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 1.970 1.965 1.960 1.955 1.950 1.945 1.940 1.935 1.930 2.50 Input voltage Vin[V] Fixed PWM PFMPWM 3.00 3.50 4.00 4.50 5.00 5.50 Input voltage Vin[V] LDO line regulation characteristics * LDO Vo=2.8V (Min) Vo=3.3V (Max) Line regulation (Io=50mA) 2.860 2.840 2.820 2.800 2.780 2.760 2.740 3 3.5 4 4.5 5 5.5 Input voltage Vin[V] DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Output voltage Vout[V] Output voltage Vout[V] Line regulation (Io=50mA) 3.360 3.340 3.320 3.300 3.280 3.260 3.240 3 3.5 4 4.5 5 5.5 Input voltage Vin[V] 47 r1.0 MB39C031 DC/DC load regulation characteristics * DD1 Vo=1.0V (Min) Vo=1.2V 1.015 Fixed PWM 1.010 PFMPWM 1.005 1.000 0.995 0.990 0.985 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.320 1.315 Fixed PWM 1.310 PFMPWM 1.305 1.300 1.295 1.290 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load regulation Load regulation PFMPWM 1.005 1.000 0.995 0.990 0.985 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.220 1.215 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output voltage [V] Load regulation Fixed PWM 1.315 Fixed PWM 1.310 PFMPWM 1.010 1.005 1.000 0.995 0.990 0.985 0.2 0.4 0.6 0.8 1 1.2 Load current [A] 1.4 1.6 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 1.180 0 0.2 0.4 0.6 0.8 1 1.2 Load current [A] 48 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.4 1.6 1.6 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load regulation 1.215 1.4 1.290 Load regulation 1.220 1.6 1.295 Load regulation PFMPWM 1.4 1.300 Load current [A] Fixed PWM 1.6 1.305 Load current [A] 1.015 1.4 1.320 Load current [A] 1.020 0 PFMPWM Load current [A] 1.010 0.980 Fixed PWM 1.210 Load current [A] 1.015 0 1.215 Load current [A] 1.020 0.980 1.220 Output voltage [V] 0 Output voltage [V] 0.980 Load regulation Output voltage [V] 1.020 Output voltage [V] Load regulation Output voltage [V] Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Vin=2.5V Load regulation Vo=1.3V (Max) 1.320 1.315 Fixed PWM 1.310 PFMPWM 1.305 1.300 1.295 1.290 1.285 1.280 0 0.2 0.4 0.6 0.8 1 1.2 Load current [A] DS405-00015-1v0-E r1.0 MB39C031 * DD2 Vo=1.2V (Min) Vo=1.8V 1.215 Fixed PWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.970 1.965 Fixed PWM 1.960 PFMPWM 1.955 1.950 1.945 1.940 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load regulation Load regulation PFMPWM 1.205 1.200 1.195 1.190 1.185 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.820 1.815 Fixed PWM 1.810 PFMPWM 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Output voltage [V] Load regulation Fixed PWM 1.965 Fixed PWM 1.960 PFMPWM 1.210 PFMPWM 1.205 1.200 1.195 1.190 1.185 0.1 0.2 0.3 0.4 0.5 Load current [A] 0.6 0.7 1.810 PFMPWM 1.805 1.800 1.795 1.790 1.785 1.780 0 0.1 0.2 0.3 0.4 0.5 Load current [A] DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 0.6 0.7 0.7 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load regulation Fixed PWM 0.6 1.940 Load regulation 1.815 0.7 1.945 Load regulation 1.820 0.6 1.950 Load current [A] Fixed PWM 0.7 1.955 Load current [A] 1.215 0.6 1.970 Load current [A] 1.220 0 PFMPWM Load current [A] 1.210 1.180 Fixed PWM 1.810 Load current [A] 1.215 0 1.815 Load current [A] 1.220 1.180 1.820 Output voltage [V] 0 Output voltage [V] 1.180 Load regulation Output voltage [V] 1.220 Output voltage [V] Load regulation Output voltage [V] Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Vin=2.5V Load regulation Vo=1.95V (Max) 1.970 1.965 Fixed PWM 1.960 PFMPWM 1.955 1.950 1.945 1.940 1.935 1.930 0 0.1 0.2 0.3 0.4 0.5 Load current [A] 49 r1.0 MB39C031 LDO load regulation characteristics * LDO Vo=2.8V (Min) Vo=3.3V (Max) Load regulation 2.850 2.840 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 2.750 0 0.05 0.1 0.15 0.2 0.25 Vin=3.5V Output voltage [V] Output voltage [V] Vin=3.0V Load regulation 3.360 3.340 3.320 3.300 3.280 3.260 3.240 0 Load current [A] 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 0.1 0.15 0.2 0.25 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 0.15 0.25 0.2 0.25 3.300 3.280 3.260 3.240 0 0.05 0.1 0.15 Load regulation 0.1 0.2 3.320 Load regulation 0.05 0.25 3.340 Load current [A] 2.840 0 0.2 3.360 Load current [A] 2.850 2.750 Vin=3.6V Output voltage [V] 2.840 0.05 0.15 Load regulation 0.2 0.25 Vin=5.5V Output voltage [V] Output voltage [V] Output voltage [V] Vin=5.5V Vin=3.6V Load regulation 0 0.1 Load current [A] 2.850 2.750 0.05 Load current [A] 50 FUJITSU SEMICONDUCTOR CONFIDENTIAL 3.360 3.340 3.320 3.300 3.280 3.260 3.240 0 0.05 0.1 0.15 Load current [A] DS405-00015-1v0-E r1.0 MB39C031 DC/DC output ripple waveform * DD1 (Fixed PWM mode) Io=0mA Output voltage =1.2V setting Io=1400mA Io=400mA VIN=2.5V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 200ns 200ns 200ns VIN=3.6V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 200ns 200ns 200ns VIN=5.5V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 200ns DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 200ns 200ns 51 r1.0 MB39C031 * DD1 (PFM/PWM mode) Io=0mA Output voltage =1.2V setting Io=1400mA Io=400mA VIN=2.5V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 200ns 200ns 4.0ms VIN=3.6V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 200ns 200ns 4.0ms VIN=5.5V Vo1 (10.0mV/div_DC) offset:1.200V 1 1 1 4.0ms 52 FUJITSU SEMICONDUCTOR CONFIDENTIAL 200ns 200ns DS405-00015-1v0-E r1.0 MB39C031 * DD2 (Fixed PWM mode) Io=0mA Output voltage =1.8V setting Io=600mA Io=400mA VIN=2.5V Vo2 (10.0mV/div_DC) offset:1.800V 1 1 1 200ns 200ns 200ns VIN=3.6V Vo2 (10.0mV/div_DC) offset:1.800V 1 1 1 200ns 200ns 200ns VIN=5.5V Vo2 (10.0mV/div_DC) offset:1.806V 1 1 1 200ns DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 200ns 400ns 53 r1.0 MB39C031 * DD2 (PFM/PWM mode) Io=0mA Output voltage =1.8V setting Io=600mA Io=400mA VIN=2.5V Vo2 (10.0mV/div_DC) offset:1.800V 1 1 1 200ns 200ns 4.0ms VIN=3.6V Vo2 (10.0mV/div_DC) offset:1.800V 1 1 1 200ns 200ns 4.0ms VIN=5.5V Vo2 (10.0mV/div_DC) offset:1.800V 1 1 1 4.0ms 54 FUJITSU SEMICONDUCTOR CONFIDENTIAL 200ns 200ns DS405-00015-1v0-E r1.0 MB39C031 DD1 startup/shutdown waveform Output voltage =1.2V setting Soft-start setting=0.9ms Fixed PWM mode Control using the external pin (CTL1) VCC = 2.5V Io=1400mA Io=0mA CTL1(3V/div) CTL1(3V/div) 1 1 PG1(3V/div) PG1(3V/div) 2 2 200s/div Vo1(0.6V/div) Vo1(0.6V/div) 3 3 IIN(1A/div) 4 20ms/div IIN(10mA/div) 4 VCC = 3.6V Io=1400mA Io=0mA CTL1(3V/div) CTL1(3V/div) 1 1 PG1(3V/div) PG1(3V/div) 2 2 200s/div Vo1(0.6V/div) Vo1(0.6V/div) 3 3 20ms/div IIN(10mA/div) 4 IIN(1A/div) VCC = 5.5V Io=1400mA Io=0mA CTL1(3V/div) 1 4 CTL1(3V/div) 1 PG1(3V/div) PG1(3V/div) 2 2 200s/div Vo1(0.6V/div) Vo1(0.6V/div) 3 3 20ms/div IIN(10mA/div) 4 IIN(1A/div) DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 55 r1.0 MB39C031 DD2 startup/shutdown waveform Output voltage =1.8V setting Soft-start setting=0.9ms Fixed PWM mode Control using the external pin (CTL2) VCC = 2.5V Io=600mA Io=0mA CTL2(3V/div) CTL2(3V/div) 1 1 PG2(3V/div) PG2(3V/div) 2 2 200s/div Vo2(0.9V/div) Vo1(0.9V/div) 3 3 20ms/div IIN(10mA/div) 4 IIN(500mA/div) VCC = 3.6V Io=600mA 4 Io=0mA CTL2(3V/div) CTL2(3V/div) 1 1 PG2(3V/div) PG2(3V/div) 2 2 200s/div Vo2(0.9V/div) Vo1(0.9V/div) 3 3 20ms/div IIN(10mA/div) 4 IIN(500mA/div) VCC = 5.5V Io=600mA 4 Io=0mA CTL2(3V/div) CTL2(3V/div) 1 1 PG2(3V/div) PG2(3V/div) 2 2 200s/div Vo2(0.9V/div) Vo1(0.9V/div) 3 3 20ms/div IIN(10mA/div) 4 IIN(500mA/div) 56 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 DS405-00015-1v0-E r1.0 MB39C031 LDO startup/shutdown waveform Output voltage =3.3V setting Soft-start setting=2.7ms Control using the external pin (CTLL) VCC = 3.6V Io=250mA Io=0mA CTLL(3V/div) CTLL(3V/div) 1 PGL(3V/div) 1 PGL(3V/div) 2 2 1ms/div LDO(1.5V/div) LDO(1.5V/div) 20ms/div 3 3 IIN(200mA/div) 4 VCC = 5.5V Io=250mA IIN(20mA/div) 4 Io=0mA CTLL(3V/div) 1 CTLL(3V/div) 1 PGL(3V/div) 2 PGL(3V/div) 2 1ms/div LDO(1.5V/div) LDO(1.5V/div) 3 3 IIN(200mA/div) 20ms/div IIN(20mA/div) 4 4 DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 57 r1.0 MB39C031 DC/DC Sudden load change characteristics * DD1(Fixed PWM mode) 0mA1400mA/10s Output voltage =1.2V setting VCC=2.5V Vo1(50mV/div) offset:1.200V Vo1(50mV/div) offset:1.200V 1 1 10s 10s Io(1.0A/div) Io(1.0A/div) 4 4 Vo1(50mV/div) offset:1.200V VCC=3.6V Vo1(50mV/div) offset:1.200V 1 1 10s 10s Io(1.0A/div) Io(1.0A/div) 4 4 VCC=5.5V Vo1(50mV/div) offset:1.200V 1 Vo1(50mV/div) offset:1.200V 1 10s 10s Io(1.0A/div) 4 Io(1.0A/div) 58 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 DS405-00015-1v0-E r1.0 MB39C031 * DD2 (Fixed PWM mode) 0mA600mA/10s Output voltage =1.8V setting Vo2(50mV/div) offset:1.800V VCC=2.5V Vo2(50mV/div) offset:1.800V 1 1 10s 10s Io(200mA/div) Io(200mA/div) 4 4 Vo2(50mV/div) offset:1.800V VCC=3.6V Vo2(50mV/div) offset:1.800V 1 1 10s 10s Io(200mA/div) 4 Io(200mA/div) 4 Vo2(50mV/div) offset:1.800V VCC=5.5V Vo2(50mV/div) offset:1.800V 1 1 10s 10s Io(200mA/div) 4 DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL Io(200mA/div) 4 59 r1.0 MB39C031 * DD1 (PFM/PWM mode) 0mA1400mA/10s Output voltage =1.2V setting VCC=2.5V Vo1(50mV/div) offset:1.200V 1 a b 1 b 10s 10s Io(1.0A/div) 4 Io(1.0A/div) 4 VCC=3.6V Vo1(50mV/div) offset:1.200V 1 a b 1 Vo1(50mV/div) offset:1.200V a b 10s 10s Io(1.0A/div) 4 Io(1.0A/div) 4 Vo1(50mV/div) offset:1.200V VCC=5.5V Vo1(50mV/div) offset:1.200V a 1 a b 1 Vo1(50mV/div) offset:1.200V a b 10s 4 10s Io(1.0A/div) 60 FUJITSU SEMICONDUCTOR CONFIDENTIAL Io(1.0A/div) 4 DS405-00015-1v0-E r1.0 MB39C031 * DD2 (PFM/PWM mode) 0mA600mA/10s Output voltage =1.8V setting VCC=2.5V Vo2(50mV/div) offset:1.800V 1 b Vo2(50mV/div) offset:1.800V a 1 b a 10s 10s Io(200mA/div) 4 Io(200mA/div) 4 Vo2(50mV/div) offset:1.800V Vo2(50mV/div) offset:1.800V VCC=3.6V a 1 b 1 b a 10s 10s Io(200mA/div) Io(200mA/div) 4 4 Vo2(50mV/div) offset:1.800V VCC=5.5V b 1 1 Vo2(50mV/div) offset:1.800V a b a 10s 10s Io(200mA/div) Io(200mA/div) 4 DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 61 r1.0 MB39C031 LDO Sudden load change characteristics * LDO 0mA150mA/2s Output voltage =3.3V setting LDO(10mV/div) offset:3.300V LDO(10mV/div) offset:3.300V VCC=3.6V a 1 1 b b a 5s 5s Io(100mA/div) Io(100mA/div) 2 2 LDO(10mV/div) offset:3.300V LDO(10mV/div) offset:3.300V VCC=5.5V a 1 1 b b a 5s 5s Io(100mA/div) Io(100mA/div) 2 2 Power dissipation Power dissipation vs. Operation ambient temperature 2.0 1.72 1.6 Pd [W] 1.2 0.8 0.4 0.0 -50 -25 0 +25 +50 +75 +100 Temperature [C] 62 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 USAGE PRECAUTION 1. Do not configure the IC over the maximum ratings. If the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to be normally operated within the recommended usage conditions. Usage outside of these conditions can have a bad effect on the reliability of the LSI. 2. Use the devices within recommended operating conditions. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 3. Printed circuit board ground lines should be set up with consideration for common impedance. 4. Take appropriate measures against static electricity. Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 k to 1 M in series between body and ground. 5. Do not apply negative voltages. The use of negative voltages below -0.3 V may cause the parasitic transistor to be activated on LSI lines, which can cause malfunctions. 6. When all channels are operating, the reliability level is designed under the condition that the average ambient temperature Ta=+60C, the typical input voltage, the typical output voltage and the typical output current condition are used. DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 63 r1.0 MB39C031 ORDERING INFORMATION Part number MB39C31WQN Package Remarks 28-pin plastic QFN (LCC-28P-M70) 64 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 PRESET CODE (MB39C031) Preset code DD1 output voltage preset code value DD2 output voltage preset code value LDO output voltage preset code value 111 112 121 122 131 132 141 142 211 212 221 222 231 232 241 242 311 312 321 322 331 332 341 342 411 412 421 422 431 432 441 442 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.30V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.20V 1.20V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V 2.85V 3.30V DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 65 r1.0 MB39C031 EV BOARD ORDERING INFORMATION EV boad part number MB39C031-EVB-01 EV board version No. Remarks MB39C031-EVB-01 REV3.0 MARKING FORMAT (Lead Free version) 39C031 XXXXXXX 342 E1 Lead-free version XX INDEX Preset code 66 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 LABELING SAMPLE (Lead free version) Lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1561190005 The part number of a lead-free product has the trailing characters "E1". DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 1/1 0605 - Z01A 1000 "ASSEMBLED IN CHINA" is printed on the label of a product assembled in China. 67 r1.0 MB39C031 MB39C031 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL Recommended Reflow Condition Item Condition Mounting Method IR (infrared reflow), warm air reflow Mounting times 3 times in a low Before opening Please use it within two years after manufacture. From opening to the reflow Less than 7 days When the storage period after opening was exceeded* Please process within 7 days after baking (125C3C, 24H2H/0H) Baking can be performed up to two times. Storage period 5C to 30C, 60RH or less (the lowest possible humidity) Storage conditions *: Concerning the Tape & Reel product, please transfer product to heatproof tray and so on when you perform baking. Also please prevent lead deforming and ESD damage during baking process. Supplier TP TC User TP TC TC TC -5C Supplier tP User tP Temperature TP tP Max. Ramp Up Rate = 3C/s Max. Ramp Down Rate = 6C/s TC -5C TL Tsmax tL Preheat Area Tsmin tS 25 Time 25C to Peak Time 260C or less (J-STD-020D) TL to TP : Temperature Increase gradient 3C/s Max. TS : Preliminary heating 150C - 200C, 60s -120s TP - tP : Peak temperature 260C or less, within 30s TL - tL : Main Heating 217C, 60s - 150s TP to TL : Cooling Increase gradient 6C/s Max. Time 25C to Peak 68 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8min Max. DS405-00015-1v0-E r1.0 MB39C031 PACKAGE DIMENSIONS 28-pin plastic QFN Lead pitch 0.40 mm Package width x package length 4.00 mm x 4.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.04 g (LCC-28P-M70) 28-pin plastic QFN (LCC-28P-M70) 4.000.10 (.157.004) 2.400.10 (.094.004) 4.000.10 (.157.004) INDEX AREA 2.400.10 (.094.004) 0.200.05 (.008.002) 0.400.05 (.016.002) 0.40(.016) TYP +0.03 0.02 -0.02 (.001 +.001 -.001 ) C 1PIN CORNER (C0.35(C.014)) 0.750.05 (.030.002) (0.20(.008)) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C28070S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 69 r1.0 MB39C031 70 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 MB39C031 DS405-00015-1v0-E FUJITSU SEMICONDUCTOR CONFIDENTIAL 71 r1.0 MB39C031 All Rights Reserved. FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves the right to make changes to the information contained in this document without notice. Please contact your FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device based on such information, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. 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The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners. 72 FUJITSU SEMICONDUCTOR CONFIDENTIAL DS405-00015-1v0-E r1.0 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Spansion Inc.: MB39C031WQN-G-342-JNEFE1 MB39C031WQN-G-332-JNEFE1 MB39C031WQN-G-142-JNEFE1 MB39C031WQN-G-132-JNEFE1 MB39C031WQN-G-442-JNEFE1 MB39C031WQN-G-112-JNEFE1 MB39C031WQNG-232-JNEFE1 MB39C031WQN-G-221-JNEFE1 MB39C031WQN-G-431-JNEFE1 MB39C031WQN-G-312-JNEFE1 MB39C031WQN-G-141-JNEFE1 MB39C031WQN-G-331-JNEFE1 MB39C031WQN-G-441-JNEFE1 MB39C031WQNG-422-JNEFE1 MB39C031WQN-G-212-JNEFE1 MB39C031WQN-G-322-JNEFE1 MB39C031WQN-G-311-JNEFE1 MB39C031WQN-G-131-JNEFE1 MB39C031WQN-G-242-JNEFE1 MB39C031WQN-G-111-JNEFE1 MB39C031WQNG-411-JNEFE1 MB39C031WQN-G-211-JNEFE1 MB39C031WQN-G-321-JNEFE1 MB39C031WQN-G-122-JNEFE1 MB39C031WQN-G-241-JNEFE1 MB39C031WQN-G-432-JNEFE1 MB39C031WQN-G-421-JNEFE1 MB39C031WQNG-341-JNEFE1 MB39C031WQN-G-412-JNEFE1 MB39C031WQN-G-121-JNEFE1 MB39C031WQN-G-222-JNEFE1 MB39C031WQN-G-231-JNEFE1