OCTOBER 2008
DSC-3619/05
1
©2007 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆64K x 32 memory configuration
◆◆
◆◆
◆Supports high system speed:
Commercial:
– A4 4.5ns clock access time (117 MHz)
Commercial and Industrial:
– 5 5ns clock access time (100 MHz)
– 6 6ns clock access time (83 MHz)
– 7 7ns clock access time (66 MHz)
◆◆
◆◆
◆Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Operates with a single 3.3V power supply (+10/-5%)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
Description
The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32
Pin Description Summary
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
64K x 32
3.3V Synchronous SRAM
Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V632/Z
with full support of the Pentium™ and PowerPC™ processor interfaces.
The pipelined burst architecture provides cost-effective 3-1-1-1 second-
ary cache performance for processors up to 117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V632 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address counter
accepts the first cycle address from the processor, initiating the access
sequence. The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode operation is
selected (ADV=LOW), the subsequent three cycles of output data will be
available to the user on the next three rising clock edges. The order of these
three addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V632 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density
in both desktop and notebook applications.
A
0
–A
15
Address Inputs Input Synchronous
CE Chip Enable Input Synchronous
CS
0
, CS
1
Chips Selects Input Synchronous
OE Output Enable Input Asynchrono us
GW Global Write Enable Input Synchronous
BWE Byte Write Enab le Input Sy nchronous
BW
1,
BW
2,
BW
3,
BW
4
Ind ividual Byte Write Se lects Inp ut Sy nchro no us
CLK Clock Input N/A
ADV Burst Address Advance Input Synchronous
ADSC Ad dress Status (Cache Co ntro lle r) Inp ut Sy nchro no us
ADSP Address Status (Processor) Input Synchronous
LBO Line ar / Interleav ed Burst Ord er Inp ut DC
ZZ Sleep Mode Input Asynchronous
I/O
0
–I/O
31
Data Inp u t/ Output I/ O Sy nc hro no us
V
DD
, V
DDQ
3.3V Power N/A
V
SS
, V
SSQ
Array Gro und, I/O G round Po we r N/A
3 619 t b l 01
6.42
2
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Sym bol Pin Fun cti on I/ O Active Descripti on
A
0
–A
15
Address Inputs I N/A Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Lo w or ADSP Low and CE Low.
ADSC Address Status
(Cache Co ntro ller) I LOW Synchronous Address Status from Cache Controller.ADSC is an a ctiv e LOW
input that is used to load the address registers with new addresses. ADSC is
NOT GA TED b y CE.
ADSP Address Status
(Processor) ILOW
Synchrono us Address Status from Processor. ADSP is an active LOW input that
is used to load the address registers with new addresses. ADSP is g ated by
CE.
ADV Burst Address Advance I LOW Synchronous Address Advance. ADV i s an ac tiv e LO W i np ut that is use d to
ad vance the internal burst co unte r, contro lling burst acc ess afte r the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, the re is no ad dress advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
–BW
4
. If BWE is
LOW at the rising edge of CLK then BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP i s HIGH and BW
X
is LOW at the rising edge of CLK then data will
b e wri tte n to the S RA M. If BWE is HIGH then the byte write inputs are blocked
and onl y GW can initiate a write cycle.
BW
1
–BW
4
Individual Byte
Write Enab le s I LOW Synchronous byte write enables. BW
1
controls I/O(7:0), BW
2
controls I/O(15:8),
etc. Any active byte write caus es all outputs to be d isabled. ADSP LOW
disables all byte writes. BW
1
–BW
4
must meet specified setup and hold times
with re s p e c t to CLK .
CE Chip Enab le I LOW S ynchro no us chip enab le . CE is use d with CS
0
and CS
1
to e nable the
IDT71V632. CE also gates ADSP.
CLK Clock I N/A This is the clock input. All timing references for the device are made with respec
t
to this inp u t.
CS
0
Chip Select 0 I HIGH Synchro nous active HIGH chip select. CS
0
is used with CE and CS
1
to e n ab le
the c hip.
CS
1
Chip Select 1 I LOW Sy nchro nous active LOW chip select. CS
1
is used with CE and CS
0
to enab le
the c hip.
GW Glob al Write Enab le I LOW Synchronous global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK. GW superced es individual byte write
enables.
I/O
0
–I/O
31
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
LBO Li ne ar B urs t Ord e r I LOW As y nc hro no us b urst o rd e r s e l ec ti o n DC input. Whe n LBO is HIGH the Interle ave d
(Intel) burst sequence is selected. When LBO is LOW the Line ar (Po we rP C) burst
sequence is selected. LBO is a static DC inp ut and mus t no t chang e state while
the device is operating.
OE Output Enab le I LOW Async hronous o utp ut enable. Whe n OE is LOW the data output drivers are
enabled on the I/O pins if the chip is also selected. When OE i s HIGH the I/ O
pins are in a high-imp edence state.
V
DD
Power Supply N/A N/A 3.3V core power supply inputs.
V
DDQ
Power Supply N/A N/A 3.3V I/O power supply inputs.
V
SS
Gro und N/A N/ A Co re g ro und p ins .
V
SSQ
Gro und N/A N/A I/O g ro und p ins.
NC No Connect N/A N/A NC pins are not electrically connected to the chip.
ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
do wn the IDT71V632 to its lo west p o wer co nsumptio n le ve l. Data retention is
guaranteed in Sleep Mode.
3619 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A
0
–A
15
ADDRESS
REGISTER
CLR
A
1
*
A
0
*
16
2
16
A
2
–A
15
64K x 32
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
32 32
ADSP
ADV
CLK
ADSC
CS0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
8
8
8
8
GW
CE
BWE
LBO
I/O
0
–I/O
31
OE
DATA INPUT
REGISTER
32
OUTPUT
BUFFER
OUTPUT
REGISTER
Powerdown
ZZ
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CE
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
3619 drw 01
.
6.42
4
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacit ance V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3619 tbl 06
Absolute Maximum Ratings(1)
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Rating Value Unit
V
TERM
(2)
Term inal Voltage w ith
Respect to GND –0.5 to + 4.6 V
V
TERM
(3)
Term inal Voltage w ith
Respect to GND –0.5 to V
DD
+0.5 V
T
A
Opera ting Tem perature 0 to +70
o
C
T
BIAS
Tem perature Under Bias –55 to +125
o
C
T
STG
St orage Tem perature –55 to +125
o
C
P
T
Pow er Dissipation 1.0 W
I
OUT
DC Output Current 50 m A
3619 tbl 05
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Max. Unit
V
DD
Core S up p l y Vo ltag e 3. 135 3. 63 V
V
DDQ
I/O Sup p ly Voltag e 3.135 3.63 V
V
SS,
V
SSQ
Ground 0 0 V
V
IH
Input High Voltage — Inputs 2.0 5.0
(1)
V
V
IH
Input High Voltage — I/O 2.0 V
DDQ
+0.3
(2)
V
V
IL
Input Lo w Voltage –0.3
(3)
0.8 V
3619 tbl 04
Recommended Operating
Temperature and Supply Voltage
Grade Temperature V
SS
V
DD
V
DDQ
Com m ercial 0° C t o + 70° C 0V 3.3V+10/-5% 3. 3V+10/ -5%
Industrial –40° C to +85° C 0V 3.3V+10/-5% 3.3V+ 10/-5%
3619 tbl 03
6.42
5
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration
Top View TQFP
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
I/O
31
I/O
30
V
DDQ
V
SSQ
I/O
29
I/O
28
I/O
27
I/O
26
V
SSQ
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SSQ
I/O
21
I/O
20
I/O
19
I/O
18
V
SSQ
V
DDQ
I/O
17
I/O
16
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
14
V
DDQ
V
SSQ
I/O
13
I/O
12
I/O
11
I/O
10
V
SSQ
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SSQ
I/O
5
I/O
4
I/O
3
I/O
2
V
SSQ
V
DDQ
I/O
1
I/O
0
NC
PK100-1
3619 drw 02
V
DD
/NC
(1)
I/O
15
A
15
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2 . ZZ = LOW for this table.
3. OE is an asynchronous input.
Operation Address
Used CE CS
0
CS
1
ADSP ADSC ADV GW BWE BW
X
OE
(3)
CLK I/O
Deselected Cycle, Power Down NoneHXXXLXXXXX ↑Hi-Z
Deselected Cycle, Power Down NoneLXHLXXXXXX↑Hi-Z
Deselected Cycle, Power Down NoneLLXLXXXXXX↑Hi-Z
Deselected Cycle, Power Down NoneLXHXLXXXXX↑Hi-Z
Deselected Cycle, Power Down NoneLLXXLXXXXX↑Hi-Z
Read Cycle, Begin Burst ExternalLH L LXXXXXL↑D
OUT
Read Cycle, Begin Burst ExternalLH L LXXXXX H↑Hi-Z
Read Cycle, Begin Burst External L H L H L X H H X L ↑D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L ↑D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H ↑Hi-Z
Write Cy cle, Begin Burst External L H L H L X H L L X ↑D
IN
Write Cy cle, Begin Burst External L H L H L X L X X X ↑D
IN
Read Cycle, Continue Burst NextXXXHH LHHXL↑D
OUT
Read Cycle, Continue Burst NextXXXHH LHHX H↑Hi-Z
Read Cycle, Continue Burst NextXXXHH LHXH L↑D
OUT
Read Cycle, Continue Burst NextXXXHH LHXHH↑Hi-Z
R ead Cycle, C ont inue Burst Next H X X X H L H H X L ↑D
OUT
R ead Cycle, C ont inue Burst Next H X X X H L H H X H ↑Hi-Z
R ead Cycle, C ont inue Burst Next H X X X H L H X H L ↑D
OUT
R ead Cycle, C ont inue Burst Next H X X X H L H X H H ↑Hi-Z
Write Cycle, Continue Burst NextXXXHH LHLLX↑D
IN
Write Cycle, Continue Burst NextXXXHH L LXXX↑D
IN
Writ e Cy cle, Continue Burst Next H X X X H L H L L X ↑D
IN
Writ e Cy cle, Continue Burst Next H X X X H L L X X X ↑D
IN
Read Cycle, Suspend Burst CurrentXXXHHHHHXL ↑D
OUT
Read Cycle, Suspend Burst CurrentXXXHHHHHX H↑Hi-Z
Read Cycle, Suspend Burst CurrentXXXHHHHX H L↑D
OUT
Read Cycle, Suspend Burst CurrentXXXHHHHX HH↑Hi-Z
Read Cycle, Suspend Burst CurrentHXXX HHHHXL ↑D
OUT
Read Cycle, Suspend Burst CurrentHXXX HHHHX H↑Hi-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L ↑D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H ↑Hi-Z
Write Cycle, Suspend Burst CurrentX X XHHHHLL X ↑D
IN
Writ e Cy cle, Suspend Burst Current X X X H H H L X X X ↑D
IN
Writ e Cy cle, Suspend Burst Current H X X X H H H L L X ↑D
IN
Writ e Cy cle, Suspend Burst Current H X X X H H L X X X ↑D
IN
3619 t bl 07
6.42
7
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Operation
(2)
OE ZZ I/ O Status Power
Read L L Data Out (I/O
0
- I/O
31
)Active
Read H L High-Z Active
Write X L High-Z — Data In (I/O
0
- I/O
31
)Active
Deselected X L High-Z Standby
Sleep X H High-Z Sleep
3619 tbl 09
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes LXXXXX
Write all Bytes HLL LLL
Write B y t e 1
(2)
HLLHHH
Write B y t e 2
(2)
HLHLHH
Write B y t e 3
(2)
HLHHLH
Write B y t e 4
(2)
HLHHHL
3619 tbl 08
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Asynchronous Truth Table(1)
Synchronous Write Function Truth Table(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = V IL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3619 tbl 10
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 00 01 10
3619 tbl 11
6.42
8
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
SA4
(3,4)
S5 S6 S7
Symbol P arameter Test Conditions C om'l. Ind. Com'l. Ind. C om'l. Ind. Com'l. Ind. Uni
t
I
DD
Opera ting Pow er
Supply Current Dev ice Select ed, O utp ut s O pen,
V
DD
= Max., V
IN
> V
IH
or < V
IL
,
f = f
MAX
(2)
220 — 200 200 180 180 160 160 mA
I
SB
St andby Pow er
Supply Current Dev ice D ese lect ed, Outp uts Open,
V
DD
= Max., V
IN
> V
IH
or < V
IL
,
f = f
MAX
(2)
70—656560605555mA
I
SB1
Full Standby Pow er
Supply Current Dev ice D ese lect ed, Outp uts Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0
(2)
15—151515151515mA
I
ZZ
Full Sleep M ode
Pow er Supply Current ZZ > V
HD
, V
DD
= Max. 10—101010101010mA
3619 tbl 13
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
3619 drw 03
DC Electrical Characteristics Over the Operating Temperature and
Supply V oltage Range(1) (VHD = VDDQ – 0.2V, VLD = 0.2V)
Figure 3. Lumped Capacitive Load, Typical Derating
* Including scope and jig capacitance.
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +10/-5%)
AC Test Loads
1
2
3
4
20 30 50 100 200
∆t
CD
(Typical, ns)
Capacitance (pF)
80
5
6
3619 drw 05
351Ω
+3.3V
317Ω
5pF*
I/O
3619 drw 04
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. SA4 speed grade corresponds to a tCD of 4.5 ns.
4. 0°C to +70°C temperature range only.
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| I nput L eakage Current V
DD
= M ax., V
IN
=
0V to V
DD
—5µA
|I
LZZ
| ZZ and LBO Input Leakage Current
(1)
V
DD
= M ax., V
IN
=
0V to V
DD
—30µA
|I
LO|
O ut put Leakage Current CE > V
IH
or OE > V
IH
, V
OUT
= 0V to V
DD
, V
DD
= Max. —5µA
V
OL
(3.3V) Output Low Voltage I
OL
= 5m A, V
DD
= Min. — 0.4 V
V
OH
(3.3V) Out put High Voltage I
OH
= –5m A, V
DD
= Min. 2.4 — V
3619 tbl 12
Figure 1. AC Test Load
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Tim ing Reference Levels
Output Tim ing Reference Levels
AC Test Load
0 to 3 .0V
2ns
1.5V
1.5V
See Figures 1 and 2
3619 tbl 14
6.42
9
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter
71V632SA4
(5,6)
71V632S5 71V632S6 71V632S7
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
CLO CK PARAMETERS
t
CYC
Clock Cycle Tim e 8.5
____
10
____
12
____
15
____
ns
t
CH
(1)
Clock High Pulse Width 3.5
____
4
____
4.5
____
5
____
ns
t
CL
(1)
Clock Low Pulse Width 3.5
____
4
____
4.5
____
5
____
ns
OUTPUT PARAMETERS
t
CD
Clock High to Valid Data
____
4.5
____
5
____
6
____
7ns
t
CDC
Clock High to Dat a Change 1. 5
____
1.5
____
2
____
2
____
ns
t
CLZ
(2)
Clo ck High to Out put Active 0
____
0
____
0
____
0
____
ns
t
CHZ
(2)
Clock High to Data High-Z 1.541.552526ns
t
OE
Out put Enable Access Tim e
____
4
____
5
____
5
____
6ns
t
OLZ
(2)
Output E nable Low to Dat a Active 0
____
0
____
0
____
0
____
ns
t
OHZ
(2)
O utput En able High to Data High-Z
____
4
____
4
____
5
____
6ns
SETUP TIMES
t
SA
Address S etup Tim e 2. 2
____
2.5
____
2.5
____
2.5
____
ns
t
SS
Ad dress St atus Set up Tim e 2.2
____
2.5
____
2.5
____
2.5
____
ns
t
SD
Data in Setup Tim e 2.2
____
2.5
____
2.5
____
2.5
____
ns
t
SW
Writ e S etup Tim e 2. 2
____
2.5
____
2.5
____
2.5
____
ns
t
SAV
Addr ess Adv ance Setup Tim e 2. 2
____
2.5
____
2.5
____
2.5
____
ns
t
SC
Chip E nable/Select Setup Tim e 2.2
____
2.5
____
2.5
____
2.5
____
ns
HOLD TIMES
t
HA
Address H old T im e 0. 5
____
0.5
____
0.5
____
0.5
____
ns
t
HS
A ddress St atus Hold Tim e 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HW
Wr it e Hold Time 0 . 5
____
0.5
____
0.5
____
0.5
____
ns
t
HAV
Add ress Adv ance Hold Tim e 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
SLEEP MODE AND CONFIGU RATION PARAMETERS
t
ZZPW
ZZ Pulse Width 100
____
100 —100
____
100
____
ns
t
ZZR
(3)
ZZ Recovery Tim e 100
____
100 — 100
____
100
____
ns
t
CFG
(4)
C onfiguration Set-up Tim e 34
____
40 — 50
____
50
____
ns
3619 tbl 15
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. The 71V632SA4 speed grade corresponds to a tCD of 4.5ns.
6. 0°C to +70°C temperature range only.
AC Electrical Characteristics
(VDD, VDDQ = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
6.42
10
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa veform of Pipelined Read Cyc le(1,2)
NOTES:
1 . O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
CHZ
t
SA
t
SC
t
HS
GW,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSP
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
ADVinsertsawait-state
CE,CS
1
(Note3)
3619drw06
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
to its initialstate)
O4(Ay)
6.42
11
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3 . O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az)
represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
O1(Az)
3619drw07
Single ReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
6.42
12
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstRead
3619drw08
BurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVsuspendsburst)
I1(Ay)
BWEis ignoredwhenADSPinitiatesburs
t
t
SC
.
t
HW
Timing Wa v e form of Write Cy c le No . 1 — GW Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2 . O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
13
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa veform of Write Cyc le No. 2 — Byte Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2 . O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
Write BurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
BWE
t
SW
(Note 3)
I1(Az)
Az
I4(Ay)
I1(Ay)
3619drw09
I4(Ay)
I3(Ay)
t
SC
BWEis ignoredwhenADSPinitiatesburs
t
BWxis ignoredwhenADSPinitiatesburs
t
I3(Az)
O3(Aw)
t
HW
t
HW
6.42
14
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa veform of Sleep (ZZ) and P ower-Down Modes(1,2,3)
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
ADDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
Single ReadSnoozeMode
t
ZZPW
3619drw10
O1(Ax)
Ax
(Note 4)
t
ZZR
Az
6.42
15
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW,BWE,BWx
CE,CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
3619 drw 11
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1 . ZZ input is LOW, ADV is HIGH and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
6.42
16
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW
CE,CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
3619 drw 12
,
Non-Burst Write Cyc le Timing Wav eform
NOTES:
1 . ZZ input is LOW, ADV and OE are HIGH, and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
17
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
18
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
S
Power
X
Speed
PF
Package
PF
71V632
A4*
5
6
7
Synchronous Access Time in nanoseconds
3619 drw 13
Device
Type
PART NUMBER SPEED IN MEGAHERTZ tCD PARAMETER CLOCK CYCLE TIME
71V632SA4PF
71V632S5PF
71V632S6PF
71V632S7PF
117 MHz
100 MHz
83 MHz
66 MHz
4.5 ns
5ns
6ns
7ns
8.5 ns
10 ns
12 ns
15 ns
* Commercial only.
X
Process/
Tempera-
ture Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Z
Z
Blank First or current generation die step.
Current generation die step optional.
6.42
19
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect Commercial and Industrial Temperature Ranges
Datasheet Document History
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9/9/99 Updated to new format
Pg. 1, 8, 9, 17 Revised speed offerings to 66–117MHz
Pg. 15, 16 Added non-burst read and write cycle timing diagrams
Pg. 18 Added Datasheet Document History
09/30/99 Pg. 1, 4, 8, 9, 17 Added industrial temperature range offerings
04/04/00 Pg. 17 Added 100pinTQFP package Diagram Outline
08/09/00 Not recommended for new designs
08/17/01 Removed “Not recommended for new designs” from the background on the datasheet
02/28/07 Pg.18 Added Z generation die step to data sheet ordering information.
10/16/08 Pg.18 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
