THC63LVDM83D-Z_Rev.1.00_E THC63LVDM83D-Z 24bit COLOR OPEN LDI(LVDS) TRANSMITTER General Description Features The THC63LVDM83D-Z transmitter is designed to support pixel data transmission between Host and Flat Panel Display up to 1080p/WUXGA resolutions. The THC63LVDM83D-Z converts 28bits of LVCMOS data into four OpenLDI(LVDS) data streams. The transmitter can be programmed for rising edge or falling edge clock through a dedicated pin. At a transmit clock frequency of 160MHz, 24bits of RGB data and 4bits of timing and control data (HSYNC, VSYNC, DE, CONT1) are transmitted at an effective rate of 1120Mbps per OpenLDI(LVDS) channel. Compatible with TIA/EIA-644 LVDS Standard 7:1 OpenLDI(LVDS) Transmitter Operating Temperature Range : -40 to +105C No Special Start-up Sequence Required Spread Spectrum Clocking Tolerant up to 100kHz Frequency Modulation and +/-2.5% Deviations. Wide Dot Clock Range: 8 to 160MHz Suited for TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz) PC Signal : QVGA(8MHz) - WUXGA(154MHz) 56pin TSSOP Package 1.2V to 3.3V LVCMOS inputs are supported. LVDS swing is reducible as 200mV by RS-pin to reduce EMI and power consumption. PLL requires no external components. Power Down Mode Input clock triggering edge is selectable by R/F-pin. EU RoHS Compliant Application Medium and Small Size Panel Tablet PC / Notebook PC Security Camera / Industrial Camera Multi Function Printer Industrial Equipment Medical Equipment Monitor Automotive Block Diagram TB0-6 TC0-6 TD0-6 7 7 7 7 CMOS/TTL PARALLEL TO SERIAL TA0-6 OpenLDI DATA DATA (LVDS) (LVDS ) THC63LVDM83D THC63LVDM83D-Z CMOS/TTL INPUTS TA +/TB +/TC +/TD +/(56-1120Mbit/On Each LVDS Channel) TRANSMITTER CLKIN (8 to 160MHz) TCLK +/- PLL CLOCK OpenLDI (LVDS) CLOCK 8-160MHz (LVDS ) 8-160MHz R/F /PDWN RS Figure 1. Block Diagram Copyright(c)2016 THine Electronics, Inc. 1/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Pin Diagram THC63LVDM83D-Z Figure 2. Pin Diagram Copyright(c)2016 THine Electronics, Inc. 2/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Pin Description Pin Name TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 Pin # 47, 48 45, 46 41, 42 37, 38 Direction Type Output LVDS Open LDI(LVDS) Data Out 39, 40 TD0 ~ TD6 51, 52, 54, 55, 56, 3, 4 6, 7, 11, 12, 14, 15, 19 20, 22, 23, 24, 27, 28, 30 50, 2, 8, 10, 16, 18, 25 /PDWN 32 Open LDI(LVDS) Clock Out Pixel Data Input Input RS LVCMOS 1 R/F 17 CLKIN 31 VCC 9, 26 GND 5, 13, 21, 29, 53 LVDS VCC LVDS GND PLL VCC PLL GND 44 36, 43 49 34 33, 35 Description H : Normal Operation L : Power Down (All outputs are Hi-Z) LVDS Swing Mode, VREF Select See Fig.7, 8 LVDS Small Swing RS Swing Input Support VCC Power - 350mV N/A 0.6V1.4V 350mV RS=VREF GND0.2V 200mV N/A VREF : is Input Reference Voltage Input Clock Triggering Edge Select H : Rising Edge L : Falling Edge Input Clock Power Supply Pins for LVCMOS inputs and digital circuit. Ground Pins for LVCMOS Inputs and Digital Circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL Circuitry. Ground Supply Pin for PLL Circuitry. Table 1. Pin Description Copyright(c)2016 THine Electronics, Inc. 3/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Absolute Maximum Ratings Parameter Min Max All Supply Voltage (VCC, LVDS_VCC, PLL_VCC) -0.3 +4.0 LVCMOS Input Voltage -0.3 VCC + 0.3 LVDS Output Pin -0.3 VCC + 0.3 Output Current -30 30 +125 Junction Temperature -55 +150 Storage Temperature +260 Reflow Peak Temperature Reflow Peak Temperature Time 10 1.8 Maximum Power Dissipation @+25C Table 2. Absolute Maximum Ratings Unit V V V mA C C C sec W Recommended Operating Conditions Symbol VCC, LVDS_VCC, PLL_VCC Ta fclk Parameter All Supply Voltage Min Typ. Max Unit 3.0 3.3 3.6 V +105 160 C MHz Operating Ambient Temperature -40 25 Clock Frequency 8 Table 3. Recommended Operating Conditions "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics Table4, 5, 6, 7" specify conditions for device operation. "Absolute Maximum Rating" value also includes behavior of overshooting and undershooting. Equivalent LVDS Output Schematic Diagram 3.5mA IN_N LVDS_OutN LVDS_OutP IN_P Figure 3. LVDS Output Schematic Diagram Copyright(c)2016 THine Electronics, Inc. 4/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Power Consumption Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Typ.* Max Unit Symbol RL=100, CL=5pF, f=85MHz, RS=VCC ITCCW LVDS Transmitter Operating Current Worst Case Pattern (Fig.4) RL=100, CL=5pF, f=135MHz, RS=VCC RL=100, CL=5pF, f=160MHz, RS=VCC RL=100, CL=5pF, f=85MHz, RS=GND RL=100, CL=5pF, f=135MHz, RS=GND RL=100, CL=5pF, f=160MHz, RS=GND LVDS Transmitter /PDWN=L, All Inputs=L or H Power Down Current *Typ. values are at the conditions of VCC=3.3V and Ta = +25C Table 4. Power Consumption ITCCS 48 67 mA 65 83 mA 73 92 mA 40 56 mA 56 71 mA 65 80 mA - 10 A Worst Case Pattern CLKIN Tx0-6 x=A,B,C,D Figure 4. Worst Case Pattern Copyright(c)2016 THine Electronics, Inc. 5/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Electrical Characteristics LVCMOS DC Specifications Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Min Typ.* Max Unit High Level Input Voltage RS=VCC or GND 2.0 VCC V Low Level Input Voltage RS=VCC or GND GND 0.8 V Small Swing Voltage 1.2 2.8 V Input Reference Voltage Small Swing (RS=VDDQ/2) VDDQ/2 VDDQ/2 Small Swing High Level VREF= VDDQ/2 +150m V Input Voltage V VSL2 Small Swing Low Level VDDQ/2 VREF= VDDQ/2 V Input Voltage -150mV IINC Input Current 10 A GND VIN VCC *Typ. values are at the conditions of VCC=3.3V and Ta = +25C Notes : 1 VDDQ voltage defines the max voltage of small swing inputs at RS=VREF. It is not an actual input Symbol VIH VIL VDDQ1 VREF VSH2 voltage. 2 Small swing signals are applied to TA0-6, TB0-6, TC0-6, TD0-6 and CLKIN. Table 5. LV-CMOS DC Specifications LVDS Transmitter DC Specifications Over recommended operating supply and temperature range unless otherwise specified Parameter Conditions Min Typ.* Max Unit Normal swing RS=VCC 250 350 450 mV Ta=25C VOD Differential Output Voltage RL=100 Reduced swing 110 200 300 mV RS=GND Change in VOD between VOD complementary output RL=100 35 mV states RL=100, Ta=25C, VOC Common Mode Voltage 1.125 1.25 1.375 V RS=VCC Change in VOC between VOC complementary output RL=100 35 mV states Output Short Circuit IOS -24 mA VOUT=GND, RL=100 Current Output TRI-STATE /PDWN=GND, IOZ 10 A Current VOUT=GND to VCC *Typ. values are at the conditions of VCC=3.3V and Ta = +25C Table 6. LVDS Transmitter DC Specifications Symbol Copyright(c)2016 THine Electronics, Inc. 6/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E LVCMOS & LVDS Transmitter AC Specifications Over recommended operating supply and temperature range unless otherwise specified Parameter Min Typ. Max Unit CLK IN Transition Time 5.0 ns CLK IN Period 6.25 T 125 ns CLK IN High Time 0.35T 0.5T 0.65T ns CLK IN Low Time 0.35T 0.5T 0.65T ns CLK IN to TCLK+/- Delay 3T 3T+4 ns LVCMOS Data Setup to CLK IN 2.0 ns LVCMOS Data Hold from CLK IN 0.0 ns LVDS Transition Time 0.6 1.5 ns Output Skew Accuracy(T=11.76ns) 120 275 ps Output Skew Accuracy(T=11.76ns) 120 250 ps tsk (3.2VVCC3.6V) Output Skew Accuracy(T=7.4ns) 120 250 ps tTop1 Output Data Position0 (T=6.25ns ~ 20ns) - tsk 0.0 + tsk ns tTop0 Output Data Position1 (T=6.25ns ~ 20ns) T/7- tsk T/7 T/7+ tsk ns tTop6 Output Data Position2 (T=6.25ns ~ 20ns) 2T/7- tsk 2T/7 2T/7+ tsk ns tTop5 Output Data Position3 (T=6.25ns ~ 20ns) 3T/7- tsk 3T/7 3T/7+ tsk ns tTop4 Output Data Position4 (T=6.25ns ~ 20ns) 4T/7- tsk 4T/7 4T/7+ tsk ns tTop3 Output Data Position5 (T=6.25ns ~ 20ns) 5T/7- tsk 5T/7 5T/7+ tsk ns tTop2 Output Data Position6 (T=6.25ns ~ 20ns) 6T/7- tsk 6T/7 6T/7+ tsk ns tTPLL Phase Lock Loop Set 1.0 ms *Typ. values are at the conditions of VCC=3.3V and Ta = +25C Table 7. LVCMOS & LVDS Transmitter AC Specifications Symbol tTCIT tTCP tTCH tTCL tTCD tTS tTH tLVT LVCMOS Input 90% CLK IN 90% 10% 10% t TCIT t TCIT Figure 5. CLKIN Transmission Time OpenLDI(LVDS) Output LVDS Output Load Figure 6. LVDS Output Load and Transmission Time Copyright(c)2016 THine Electronics, Inc. 7/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E AC Timing Diagrams LVCMOS Inputs tTCP tTCH V DDQ CLKIN RS VCC 0.6V1.4V GND0.2V VOD 350mV 200mV GND tTCL tTH tTS V DDQ Tx0-Tx6 GND VOD tTCD TCLK+ VOC TCLK- Note : CLKIN : Solid line denotes the setting of R/F=GND Dashed line denotes the setting of R/F = VCC Figure 7. LVCOMS Inputs and LVDS Clock Output Timing 1 Small Swing Inputs tTCP tTCH V DDQ CLKIN VDDQ /2 V DDQ /2 VDDQ /2 VREF GND tTCL tTS RS VCC 0.6V1.4V VREF -VDDQ/2 GND0.2V -- tTH V DDQ VDDQ /2 Tx0-Tx6 V DDQ /2 V REF GND tTCD TCLK+ VOC TCLK- Note : CLKIN : Solid line denotes the setting of R/F=GND Dashed line denotes the setting of R/F = VCC Figure 8. LVCMOS Inputs and LVDS Output Timing 2 Copyright(c)2016 THine Electronics, Inc. 8/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E OpenLDI(LVDS) Output Data Position TCLK+/(Differential) Vdiff = 0V Vdiff = 0V TA+/- TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB+/- TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC+/- TC6 TC5 TC4 TC3 TC2 TC1 TC0 TD+/- TD6 TD5 TD4 TD3 TD2 TD1 TD0 Previous Cycle Next Cycle t TOP1 t TOP0 t TOP6 t TOP5 t TOP4 t TOP3 t TOP2 Figure 9. LVDS Output Data Position Phase Lock Loop Set Time /PDWN VCC 2.0V 3.0V tTPLL CLKIN Vdiff = 0V TCLK+/- Figure 10. PLL Lock Loop Set Time Copyright(c)2016 THine Electronics, Inc. 9/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Spread Spectrum Clocking Tolerant Figure 11. Spread Spectrum Clocking Tolerant The graph indicates the range that the IC works normally under SS clock input operation. The results are measured with a typical sample on condition of +25C and 3.3V, therefore these values are for reference and do not guarantee the performance of a product under other circumstance. Copyright(c)2016 THine Electronics, Inc. 10/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E OpenLDI(LVDS) Data Timing Diagram Figure 12. LVDS Data Timing Diagram THC63LVDM83D-Z Pixel Data Mapping for JEIDA Format (6bit, 8bit Application) TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 6bit R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 Hsync Vsync DE - 8bit R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 Hsync Vsync DE R0 R1 G0 G1 B0 B1 N/A Note : Use TA to TC channels and open TD channel for 6bit application. Table 8. Data Mapping for JEIDA Format Copyright(c)2016 THine Electronics, Inc. 11/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E THC63LVDM83D-Z Pixel Data Mapping for VESA Format (6bit, 8bit Application) TA0 TA1 TA2 TA3 TA4 TA5 TA6 TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TD0 TD1 TD2 TD3 TD4 TD5 TD6 6bit R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 Hsync Vsync DE - 8bit R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 Hsync Vsync DE R6 R7 G6 G7 B6 B7 N/A Note : Use TA to TC channels and open TD channel for 6bit application. Table 9. Data Mapping for VESA Format Copyright(c)2016 THine Electronics, Inc. 12/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Normal Connection THC63LVDM83D-Z THC63LVDF(R)84C Figure 13. Typical Connection Diagram Copyright(c)2016 THine Electronics, Inc. 13/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Notes 1) Cable Connection and Disconnection Do not connect and disconnect the OpenLDI(LVDS) cable, when the power is supplied to the system. 2) GND Connection Connect each GND of the PCB which THC63LVDM83D-Z and OpenLDI(LVDS)-Rx on it. EMI reduction to place GND cable as close to OpenLDI(LVDS) cable as possible. It is better for 3) Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVDM83D-Z TCLK- OpenLDI (LVDS)-RX OpenLDI (LVDS)-RX Figure 14. Multi Drop Connection 4) Asynchronous use Asynchronous using such as following systems is not recommended. CLKOUT TCLK+ DATA THC63LVDM83D-Z TCLKIC CLKOUT TCLK+ DATA THC63LVDM83D-Z TCLK- CLKOUT OpenLDI (LVDS)-RX OpenLDI CLKOUT DATA IC DATA (LVDS)-RX TCLK+ DATA THC63LVDM83D-Z TCLKIC CLKOUT TCLK+ IC DATA THC63LVDM83D-Z TCLK- Figure 15. Asynchronous Use Copyright(c)2016 THine Electronics, Inc. 14/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E 8.10 NOM 0.05~0.15 0.25 1.20MAX 6.10+/-0.1 Package Figure 16. Package Diagram Copyright(c)2016 THine Electronics, Inc. 15/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Reference Land Pattern Figure 17. Reference of Land Pattern The recommendation mounting method of THine device is reflow soldering. The reference pattern is using the calculation result on condition of reflow soldering. Notes This land pattern design is a calculated value based on JEITA ET-7501. Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of connection, the density of mounting, and the solder paste used, etc... The optimal land pattern size changes with these parameters. Please use the value shown by the land pattern as reference data. Copyright(c)2016 THine Electronics, Inc. 16/17 THine Electronics, Inc. Security E THC63LVDM83D-Z_Rev.1.00_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet. THine Electronics, Inc. ("THine") accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp Copyright(c)2016 THine Electronics, Inc. 17/17 THine Electronics, Inc. Security E