2017 Microchip Technology Inc. DS20005537B-page 1
DN2625
Features
• Very Low Gate Threshold Voltage
• Designed to be Source-driven
• Low Switching Losses
• Low Effective Output Capacitance
• Designed for Inductive Loads
Applications
• Medical Ultrasound Beamforming
• Ultrasonic Array-focusing Transmitter
• Piezoelectric Transducer Waveform Drivers
• High-speed Arbitrary Waveform Generator
• Normally-on Switches
• Solid-state Relays
• Constant Current Sources
• Power Supply Circuits
General Description
The DN2625 is a low-threshold Depletion-mode
(normally-on) transistor that utilizes an advanced
vertical DMOS structure and a well-proven silicon gate
manufacturing process. This combination produces a
device with the power handling capabilities of bipolar
transistors as well as the high input impedance and
positive temperature coefficient inherent in
Metal-Oxide Semiconductor (MOS) devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally induced
secondary breakdown.
Vertical DMOS Field-Effect Transistors (FETs) are ide-
ally suited to a wide range of switching and amplifying
applications where high breakdown voltage, high input
impedance, low input capacitance and fast switching
speeds are desired.
The DN2625DK6-G contains two MOSFETs in an
8-lead, dual-pad DFN package. The DN2625 contains
a single MOSFET in a TO-252 D-PAK package.
Package Types
TO-252 D-PAK
(Top view)
GATE
SOURCE
DRAIN
See Table 3-1 and Table 3-2 for pin information.
8
1
2
3
4
7
6
5
S1
G1
D1
S2
G2
D1
D2
D2
D1
D2
8-lead DFN (Dual Pad)
(Top view)
N-Channel Depletion-Mode Vertical DMOS FET in Single and Dual Options
DN2625
DS20005537B-page 2 2017 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-source Voltage ....................................................................................................................................... BVDSX
Drain-to-gate Voltage .......................................................................................................................................... BVDGX
Gate-to-source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ..................................................................................................... –55°C to 150°C
Storage Temperature, TS ....................................................................................................................... –55°C to 150°C
Soldering Temperature (Note 1) ........................................................................................................................... 300°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Distance of 1.6 mm from case for 10 seconds
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = 25°C. (Note 1)
Parameter Sym. Min. Typ. Max. Unit Conditions
Drain-to-source Breakdown Voltage BVDSX 250 — — V VGS = –2.5V, ID = 50 µA
Drain-to-gate Breakdown Voltage BVDGX 250 — — V VGS = –2.5V, ID = 50 µA
Gate-to-source Off Voltage VGS(OFF) –1.5 —–2.1 V VDS = 15V, ID = 100 µA
Change in VGS(OFF)
with Temperature
∆VGS(OFF) — — –4.5 mV/°C VDS = 15V, ID = 100 µA (Note 2)
Gate Body Leakage Current IGSS — — 100 nA VGS = ±20V, VDS = 0V
Drain-to-source Leakage Current ID(OFF)
— — 1
µA
VDS = 250V, VGS = –5V
— — 200 VDS = 250V, VGS = –5V,
TA = 125°C (Note 2)
Saturated Drain-to-source Current IDSS 1.1 — — A VGS = 0V, VDS = 15V
Pulsed Drain-to-source Current IDS(PULSE) 3.1 3.3 — A VGS = 0.9V, VDS = 15V
(With duty cycle of 1%)
Static Drain-to-source On-resistance RDS(ON) — — 3.5 ΩVGS = 0V, ID = 1A
Change in RDS(ON) with
Temperature ∆RDS(ON) — — 1.1 %/°C VGS = –0V, ID = 200 mA (Note 2)
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TA = 25°C. (Note 2)
Parameter Sym. Min. Typ. Max. Unit Conditions
Forward Transconductance GFS 100 — — mmh0 VDS = 10V, ID = 150 mA
Input Capacitance CISS —800 1000 pF VGS = –2.5V,
VDS = 25V,
f = 1 MHz
Common Source Output Capacitance COSS —70 210 pF
Reverse Transfer Capacitance CRSS —18 70 pF
Turn-on Delay Time td(ON) — — 10 ns VDD = 25V,
ID = 150 mA,
RGEN = 3Ω,
VGS = 0V to –10V
Rise Time tr— — 20 ns
Turn-off Delay Time td(OFF) — — 10 ns
Fall Time tf— — 20 ns
Total Gate Charge QG— — 7.04 nC ID = 3.5A,
VDS = 100V,
VGS = 1.5V
Gate-to-source Charge QGS — — 0.783 nC
Gate-to-drain Charge QGD — — 3.73 nC
DIODE PARAMETER
Diode Forward Voltage Drop VSD — — 1.8 V VGS = –2.5V, ISD = 150 mA
(Note 1)
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Ambient Temperature TA–55 —150 °C
Storage Temperature TS–55 —150 °C
Soldering Temperature — — — 300 °C Note 1
PACKAGE THERMAL RESISTANCE
TO-252 D-PAK θJA —81 —°C/W Note 2
8-lead DFN (Dual Pad) θJA —29 —°C/W Note 3
Note 1: Distance of 1.6 mm from case for 10 seconds
2: Four-layer, 1-oz, 3 x 4-inch PCB with 20 via for drain pad
3: Four-layer, 1-oz, 3 x 4-inch PCB with 12 via for drain pad
THERMAL CHARACTERISTICS
Package
ID ( 1)
(Continuous)
(A)
ID
(Pulsed)
(A)
IDR( 1)
(A)
IDRM
(A)
TO-252 D-PAK 1.1 3.3 1.1 3.3
8-lead DFN (Dual Pad) 1.1 3.3 1.1 3.3
Note 1: ID (Continuous) is limited by maximum TJ.
2017 Microchip Technology Inc. DS20005537B-page 3
DN2625
DN2625
DS20005537B-page 4 2017 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
0 50 100 150 200 250
VDS (volts)
ID (amps)
VGS = 2.0V
VGS = 1.5V
VGS = 1.0V
VGS = 0.5V
VGS = 0V
VGS = -0.5V
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1: Output Characteristics.
0
1
2
3
4
5
6
7
8
9
10
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0
VGS (V)
I
D
(amps)
-55OC
25OC
125OC
FIGURE 2-2: Transfer Characteristics.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
012345678910
VDS (V)
ID (A)
VGS = -2V
VGS = -1.5V
VGS = -1V
VGS = -0.5V
VGS = 0V
VGS = 0.5V
VGS = 1V
VGS = 1.5V
VGS = 2V
FIGURE 2-3: Saturation Characteristics.
FIGURE 2-4: BVDSX Variation with
Temperature.
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-50 -25 0 25 50 75 100 125 150
Tj (OC)
BVDSX (normalized)
VGS = -2.5V
ID = 1mA
D
FIGURE 2-5: On-resistance vs. Drain
Current.
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
-50 -25 0 25 50 75 100 125 150
T
j
(
O
C)
V
GS(OFF)
(normalized)
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
V
GS(OFF)
@100µA
V
DS
= 15V
R
DS(ON)
@V
GS
= 1V
I
D
=1A
R
DS(ON)
(normalized)
FIGURE 2-6: VGS(OFF) and RDS(ON)
Variation with Temperature.
2017 Microchip Technology Inc. DS20005537B-page 5
DN2625
FIGURE 2-7: Transconductance vs. Drain
Current.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
I
D
(A)
G
FS
(Siemens)
-55OC
25OC
125OC
VDS = 10V
DN2625
DS20005537B-page 6 2017 Microchip Technology Inc.
3.0 PIN DESCRIPTION
The details on the pins of TO-252 D-PAK and 8-lead
DFN (dual pad) are listed in Ta b l e 3-1 and Tab l e 3-2.
Refer to Package Types for the location of pins.
TABLE 3-1: TO-252 D-PAK PIN FUNCTION TABLE
Pin Number Pin Name Description
1Gate Gate
2Drain Drain
3Source Source
4Drain Drain
TABLE 3-2: 8-LEAD DFN (DUAL PAD) PIN FUNCTION TABLE
Pin Number Pin Name Description
1S1 Device 1 source
2G1 Device 1 gate
3S2 Device 2 source
4G2 Device 2 gate
5D2 Device 2 drain
6D2 Device 2 drain
7D1 Device 1 drain
8D1 Device 1 drain
2017 Microchip Technology Inc. DS20005537B-page 7
DN2625
4.0 FUNCTIONAL DESCRIPTION
Figure 4-1 shows the switching waveforms and test
circuit for DN2625.
90%
10%
90% 90%
10%
10%
Pulse
Generator
VDD
R
L
OUTPUT
D.U.T.
t(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
r
INPUT
INPUT
OUTPUT
0V
VDD
R
GEN
0V
-10V
t
f
FIGURE 4-1: Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSX/BVDGX
(V)
VGS(OFF)
(Maximum)
(V)
IDS (Pulsed)
(VGS = 0.9V)
(Minimum)
(A)
250 –2.1 3.3
DN2625
DS20005537B-page 8 2017 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
TO-252 (D-PAK) Example
YYWWNNN
XXXXX
XXXX
e3
1641343
2625
DN
e3
8-lead DFN Example
NNN
XXXXXXX
XXXXXXX
YYWW
e3
343
K6
DN2625D
1613
e3
2017 Microchip Technology Inc. DS20005537B-page 9
DN2625
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
DN2625
DS20005537B-page 10 2017 Microchip Technology Inc.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc. DS20005537B-page 11
DN2625
APPENDIX A: REVISION HISTORY
Revision A (December 2016)
• Converted Supertex Document DSFP-DN2625 to
Microchip DS20005537B
• Removed obsolete package, 14-lead QFN
• Changed the TO-252 D-PAK packaging quantity
from 1000/Bag to 2000/Reel
• Revised the Features section
Revision B (May 2017)
• Corrected the 8L DFN Package Outline dimen-
sions by changing it from 4 mm x 4 mm body/1
mm height/1 mm pitch to 5 mm x 5 mm body/0.9
mm height/1.27 mm pitch
• Made minor text changes throughout the docu-
ment
DN2625
DS20005537B-page 12 2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Devices: DN2625 = N-Channel Depletion-Mode
Vertical DMOS FET (Single Option)
DN2625D = N-Channel Depletion-Mode Vertical
DMOS FET (Dual Option)
Packages: K4 = TO-252 D-PAK
K6 = 8-lead DFN
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Types: (blank) = 2000/Reel for a K4 Package
= 490/Tray for a K6 Package
Examples:
a) DN2625K4-G: N-Channel Depletion-Mode
Vertical DMOS FET (Single
Option), TO-252 D-PAK
Package, 2000/Reel
b) DN2625DK6-G: N-Channel Depletion-Mode
Vertical DMOS FET (Dual
Option), 8-lead DFN
Package, 490/Tray
PART NO. X
Device
X
Environmental
XX
Package
Options
Media
--
Type
2017 Microchip Technology Inc. DS20005537B-page 13
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1759-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005537B-page 14 2017 Microchip Technology Inc.
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