________________General Description
The MAX192 is a low-cost, 10-bit data-acquisition system
that combines an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and ultra-low power consumption. The device
operates with a single +5V supply. The analog inputs are
software configurable for single-ended and differential
(unipolar/bipolar) operation.
The 4-wire serial interface connects directly to SPI™,
QSPI™, and Microwire™ devices, without using external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The MAX192
uses either the internal clock or an external serial-
interface clock to perform successive approximation A/D
conversions. The serial interface can operate beyond
4MHz when the internal clock is used. The MAX192 has
an internal 4.096V reference with a drift of ±30ppm typi-
cal. A reference-buffer amplifier simplifies gain trim and
two sub-LSBs reduce quantization errors.
The MAX192 provides a hardwired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the device, and
the quick turn-on time allows the MAX192 to be shut
down between conversions. By powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
The MAX192 is available in 20-pin DIP and SO pack-
ages, and in a shrink-small-outline package (SSOP)
that occupies 30% less area than an 8-pin DIP. The
data format provides hardware and software compati-
bility with the MAX186/MAX188. For anti-aliasing filters,
consult the data sheets for the MAX291–MAX297.
________________________Applications
Automotive
Pen-Entry Systems
Consumer Electronics
Portable Data Logging
Robotics
Battery-Powered Instruments, Battery
Management
Medical Instruments
____________________________Features
♦8-Channel Single-Ended or 4-Channel Differential
Inputs
♦Single +5V Operation
♦Low Power: 1.5mA (operating)
2µA (power-down)
♦Internal Track/Hold, 133kHz Sampling Rate
♦Internal 4.096V Reference
♦4-Wire Serial Interface is Compatible
with SPI, QSPI, Microwire, and TMS320
♦20-Pin DIP, SO, SSOP Packages
♦Pin-Compatible 12-Bit Upgrade (MAX186/MAX188)
_______________Ordering Information
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
________________________________________________________________ Maxim Integrated Products
1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
DIP/SO/SSOP
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREFSHDN
AGND
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX192
___________________Pin Configuration
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Corp.
19-0247; Rev. 1; 4/97
PART TEMP. RANGE
MAX192ACPP 0°C to +70°C
MAX192BCPP 0°C to +70°C
MAX192ACWP 0°C to +70°C 20 Wide SO
20 Plastic DIP
20 Plastic DIP
PIN-PACKAGE
MAX192BCWP 0°C to +70°C 20 Wide SO
MAX192ACAP 0°C to +70°C 20 SSOP
MAX192BCAP 0°C to +70°C 20 SSOP
±1/2
±1
±1/2
INL (LSB)
±1
±1/2
±1
MAX192AEPP -40°C to +85°C 20 Plastic DIP ±1/2
MAX192BEPP -40°C to +85°C 20 Plastic DIP ±1
MAX192AEWP -40°C to +85°C 20 Wide SO ±1/2
MAX192BEWP -40°C to +85°C 20 Wide SO ±1
MAX192AEAP -40°C to +85°C 20 SSOP ±1/2
MAX192BEAP -40°C to +85°C 20 SSOP ±1
MAX192AMJP -55°C to +125°C 20 CERDIP ±1/2
MAX192BMJP -55°C to +125°C 20 CERDIP ±1
See last page for Typical Operating Circuit.
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
2 _______________________________________________________________________________________
VDD to AGND........................................................... -0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH7 to AGND, DGND ...................... -0.3V to (VDD + 0.3V)
CH0–CH7 Total Input Current.......................................... ±20mA
VREF to AGND .......................................... -0.3V to (VDD + 0.3V)
REFADJ to AGND...................................... -0.3V to (VDD + 0.3V)
Digital Inputs to DGND.............................. -0.3V to (VDD + 0.3V)
Digital Outputs to DGND........................... -0.3V to (VDD + 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
SO (derate 10.00mW/°C above +70°C)...................... 800mW
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
MAX192_C_P..................................................... 0°C to +70°C
MAX192_E_P .................................................. -40°C to +85°C
MAX192_MJP ............................................... -55°C to +125°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10sec)............................ +300°C
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
MAX192A
-3dB rolloff
65kHz, VIN = 4.096Vp-p (Note 3)
External reference, 4.096V
MAX192B
No missing codes over temperature
External reference, 4.096V
CONDITIONS
kHz800Full-Power Bandwidth MHz4.5Small-Signal Bandwidth dB-75Channel-to-Channel Crosstalk dB70SFDRSpurious-Free Dynamic Range
dB-70THD
Total Harmonic Distortion
(up to the 5th harmonic)
dB66SINADSignal-to-Noise + Distortion Ratio
±1/2 Bits10Resolution
LSB±0.1
Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
LSB
±1
Relative Accuracy (Note 2)
LSB±1DNLDifferential Nonlinearity LSB±2Offset Error LSB±2Gain Error
UNITSMIN TYP MAXSYMBOLPARAMETER
Internal clock 5.5 10
Conversion Time (Note 4) tCONV External clock, 2MHz, 12 clocks/conversion 6 µs
Track/Hold Acquisition Time tAZ 1.5 µs
Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock)
CONVERSION RATE
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Internal compensation
0mA to 0.5mA output load
TA= +25°C (Note 7)
(Note 5)
On/off leakage current; VIN = 0V, 5V
Bipolar
Used for data transfer only
Internal compensation (Note 5)
External compensation, 4.7µF
Single-ended range (unipolar only)
Common-mode range (any input)
CONDITIONS
0mV2.5Load Regulation (Note 8) ppm/°C±30VREF Tempco mA30VREF Short-Circuit Current V4.066 4.096 4.126VREF Output Voltage
pF16Input Capacitance µA±0.01 ±1Multiplexer Leakage Current
V
-VREF +VREF
-2 2
Analog Input Voltage
(Note 6) 0 VREF
0 VREF
0 VDD
MHz
10
External Clock Frequency 0.1 0.4
0.1 2.0 UNITSMIN TYP MAXSYMBOLPARAMETER
Capacitive Bypass at VREF External compensation 4.7 µF
Internal compensation 0.01
Capacitive Bypass at REFADJ External compensation 0.01 µF
REFADJ Adjustment Range ±1.5 %
Input Voltage Range 2.5 VDD +
50mV V
Input Current 200 350 µA
Input Resistance 12 20 kΩ
Shutdown VREF Input Current 1.5 10 µA
Buffer Disable Threshold
REFADJ VDD -
50mV V
Unipolar
Differential range
Internal compensation mode 0
Capacitive Bypass at VREF External compensation mode 4.7 µF
Reference-Buffer Gain 1.678 V/V
REFADJ Input Current ±50 µA
ANALOG INPUT
INTERNAL REFERENCE (reference buffer enabled)
EXTERNAL REFERENCE AT VREF (buffer disabled, VREF = 4.096V)
EXTERNAL REFERENCE AT REFADJ
Note 1: Tested at VDD = 5.0V; single-ended, unipolar.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ISINK = 16mA
ISINK = 5mA
SHDN = open
SHDN = open
SHDN = 0V
SHDN = VDD
(Note 5)
VIN = 0V or VDD
CONDITIONS
V
0.3
VOL
Output Voltage Low 0.4
nA-100 100
SHDN Max Allowed Leakage,
Mid Input
V2.75VFLT
SHDN Voltage, Floating V1.5 VDD - 1.5VIM
SHDN Input Mid Voltage µA-4.0IINL
SHDN Input Current, Low µA4.0IINH
SHDN Input Current, High V0.5VINL
SHDN Input Low Voltage VVDD - 0.5VINH
SHDN Input High Voltage pF15CIN
DIN,SCLK, CS Input Capacitance µA±1IIN
DIN, SCLK, CS Input Leakage V0.15VHYST
DIN, SCLK, CS Input Hysteresis V0.8VINL
DIN,SCLK, CS Input Low Voltage V2.4VINH
DIN,SCLK, CS Input High Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current ILCS = 5V ±10 µA
Three-State Leakage Capacitance COUT CS = 5V (Note 5) 15 pF
Positive Supply Voltage VDD 5 ±5% V
Operating mode 1.5 2.5 mA
Fast power-down 30 70Positive Supply Current IDD Full power-down 2 10 µA
Positive Supply Rejection
(Note 9) PSR VDD = 5V ±5%; external reference, 4.096V;
full-scale input ±0.06 ±0.5 mV
EXTERNAL REFERENCE AT REFADJDIGITAL INPUTS (DIN, SCLK, –
C
—
S
–, –
S
—
H
—
D
—
N
–)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
Note 5: Guaranteed by design. Not subject to production testing.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS
(VDD = 5V ±5%, TA= TMIN to TMAX, unless otherwise noted.)
CLOAD = 100pF
External clock mode only, CLOAD = 100pF
CLOAD = 100pF
CLOAD = 100pF
CLOAD = 100pF
External clock mode only, CLOAD = 100pF
CONDITIONS
ns200tSTR
CS Rise to SSTRB Output
Disable (Note 5)
CS Fall to SSTRB Output Enable
(Note 5) ns200tSDV
ns0tDH
DIN to SCLK Hold ns100tDS
µs1.5tAZ
Acquisition Time
DIN to SCLK Setup
ns200tSSTRB
SCLK Fall to SSTRB ns200tCL
SCLK Pulse Width Low ns200tCH
SCLK Pulse Width High ns0tCSH
CS to SCLK Rise Hold
ns20 150tDO ns100tDV ns100tTR
SCLK Fall to Output Data Valid
ns100tCSS
CS to SCLK Rise Setup
UNITSMIN TYP MAXSYMBOLPARAMETER
SSTRB Rise to SCLK Rise
(Note 5) tSCK Internal clock mode only 0 ns
CS Rise to Output Disable
CS Fall to Output Enable
__________________________________________Typical Operating Characteristics
0.16
0-60 -20 60 140
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.02
0.12
TEMPERATURE (°C)
OFFSET MATCHING (LSBs)
20 100
0.10
0.04
-40 0 40 80 120
0.14
0.08
0.06
0.30
-0.05 -60 140
POWER-SUPPLY REJECTION
vs. TEMPERATURE
0
0.25
TEMPERATURE (°C)
PSR (LSBs)
60
0.10
0.05
-40 20 100
0.15
0.20
-20 0 40 80 120
VDD = +5V ±5%
2.456
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.452
2.455
TEMPERATURE (°C)
VREFADJ (V)
2.454
2.453
-40 -20 0 20 40 60 80 100 120
-60 140
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADCs
6
________________________________________________________________________________________________
+5V
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
+3V
3k
CLOAD
DGND
DOUT
CLOAD
DGND
3k
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disabled Time
Pin Description
PIN NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
9, 13 AGND Analog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.
10 SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.
11 VREF Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.
12 REFADJ Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.
14 DGND Digital Ground
15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is
high.
16 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. SSTRB is high impedance when CS is high
(external mode).
17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
18 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20 VDD Positive Supply Voltage, +5V ±5%
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
_______________________________________________________________________________________ 7
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.46V
REFERENCE
T/H
ANALOG
INPUT
MUX SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
AGND
REFADJ
VREF
OUT
REF
CLOCK
+4.096V
20k ≈ 1.65
1
2
3
4
5
6
7
8
10
11
12
13
15
16
17
18
19
CS
SHDN
A
20
14
AGND 9
MAX192
Figure 3. Block Diagram
Detailed Description
The MAX192 uses a successive-approximation conver-
sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX192.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.
In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
action is equivalent to transferring a charge of
16pF x (VIN+ - VIN-) from CHOLD to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
CSWITCH
TRACK
T/H
SWITCH
10k
RS
CHOLD
HOLD
CAPACITIVE DAC
VREF
ZERO COMPARATOR
–+
16pF
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX192
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for single-ended
inputs, IN- is connected to AGND, and the converter
samples the “+” input. If the converter is set up for differ-
ential inputs, IN- connects to the “-” input, and the differ-
ence of IN+ - IN-is sampled. At the end of the conver-
sion, the positive input connects back to IN+, and
CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acquisi-
tion time lengthens and more time must be allowed
between conversions. Acquisition time is calculated by:
tAZ = 9 (RS+ RIN) 16pF
where RIN = 5kΩ, RS= the source impedance of the
input signal, and tAZ is never less than 1.5µs. Note that
source impedances below 5kW do not significantly affect
the AC performance of the ADC. Higher source imped-
ances can be used if an input capacitor is connected to
the analog inputs, as shown in Figure 5. Note that the
input capacitor forms an RC filter with the input source
impedance, limiting the ADC’s signal bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
See the data sheets for the MAX291–MAX297 filters.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV, or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
The MAX192 can be configured for differential (unipolar
or bipolar) or single-ended (unipolar only) inputs, as
selected by bits 2 and 3 of the control byte (Table 3).
In the single-ended mode, set the UNI/BIP bit to unipolar.
In this mode, analog inputs are internally referenced to
AGND, with a full-scale input range from 0V to VREF.
In differential mode, both unipolar and bipolar settings
can be used. Choosing unipolar mode sets the differen-
tial input range at 0V to VREF. The output code is invalid
(code zero) when a negative differential input voltage is
applied. Bipolar mode sets the differential input range to
±VREF / 2. Note that in this differential mode, the com-
mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.
Quick Look
To evaluate the analog performance of the MAX192
quickly, use Figure 5’s circuit. The MAX192 requires a
control byte to be written to DIN before each
conversion. Tying DIN to +5V feeds in control bytes of
Low-Power, 8-Channel,
Serial 10-Bit ADC
8 _______________________________________________________________________________________
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND
0 0 0 + –
1 0 0 + –
0 0 1 + –
1 0 1 + –
0 1 0 + –
1 1 0 + –
0 1 1 + –
1 1 1 + –
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
_______________________________________________________________________________________ 9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
Bit Name Description
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion.
5 SEL1 See Tables 1 and 2.
4 SEL0
3 UNI/BIP 1= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in differential bipolar
mode, the differential signal can range from -VREF / 2 to +VREF / 2. Select differential
operation if bipolar mode is used.
2 SGL/DIF 1= single ended, 0= differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. Select unipolar operation
if single-ended mode is used. See Tables 1 and 2.
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
00Full power-down (IQ= 2µA)
01Fast power-down (IQ= 30µA)
10Internal clock mode
1 1 External clock mode
Table 3. Control-Byte Format
Table 2. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 0 0 + –
0 0 1 + –
0 1 0 + –
0 1 1 + –
1 0 0 – +
1 0 1 – +
1 1 0 – +
1 1 1 – +
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
10 ______________________________________________________________________________________
$FF (HEX), which trigger single-ended conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result comes
out of DOUT. Varying the analog input to CH7 should
alter the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a Conversion
A conversion is started on the MAX192 by clocking
a control byte into DIN. Each rising edge on SCLK,
with CS low, clocks a bit from DIN into the MAX192’s
internal shift register. After CS falls, the first arriving
logic “1” bit defines the MSB of the control byte. Until
this first “start” bit arrives, any number of logic “0” bits
can be clocked into DIN with no effect. Table 3 shows
the control-byte format.
The MAX192 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire and SPI both
transmit a byte and receive a byte at the same time.
Using the
Typical Operating Circuit
, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Example: Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode,
call it TB1. TB1 should be of the format:
1XXXXX11 binary, where the Xs denote the par-
ticular channel and conversion-mode selected.
2) Use a general-purpose I/O line on the CPU to
pull CS on the MAX192 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and
simultaneously receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and
simultaneously receive byte RB3.
6) Pull CS on the MAX192 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero, two sub-LSB bits, and
three trailing zeros. The total conversion time is a func-
tion of the serial clock frequency and the amount of
dead time between 8-bit transfers. Make sure that the
total conversion time does not exceed 120µs, to avoid
excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs in differential mode, the
output is twos-complement (Figure 16). Data is clocked
out at the falling edge of SCLK in MSB-first format.
Internal and External Clock Modes
The MAX192 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX192. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7 through 10
show the timing characteristics common to both
modes.
REFERENCE ZERO
SCALE FULL SCALE
Internal Reference 0V +4.096V
External
Reference 0V VREF
at REFADJ
at VREF 0V VREFADJ (1.678)
Table 4a. Unipolar Full Scale and Zero
Scale
Table 4b. Differential Bipolar Full Scale,
Zero Scale, and Negative Full Scale
REFERENCE NEGATIVE
FULL SCALE FULL SCALE
Internal Reference -4.096V / 2 +4.096V / 2
External
Reference
-1/2VREFADJ
(1.678)
+1/2VREF
at
REFADJ
0.at VREF -1/2VREF
+1/2VREFADJ
(1.678)
ZERO
SCALE
0V
0V
0V
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte.
Successive-approximation bit decisions are made and
appear at DOUT on each of the next 12 SCLK falling
edges (see Figure 6). The first 10 bits are the true data
bits, and the last two are sub-LSB bits.
SSTRB and DOUT go into a high-impedance state when
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX192 generates its own
conversion clock internally. This frees the microproces-
sor from the burden of running the SAR conversion
clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the
conversion is complete. SSTRB will be low for a maxi-
mum of 10µs, during which time SCLK should remain
low for best noise performance. An internal register
stores data when the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the
next falling clock edge will produce the MSB of the
conversion at DOUT, followed by the remaining bits in
MSB-first format (Figure 9). CS does not need to be
held low once a conversion is started.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 11
0.1µF
VDD
DGND
AGND
AGND
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+5V
N.C.
0.01µFCH7
REFADJ
VREF
C2
0.01µF
+2.5V
REFERENCE
C1
4.7µF
0V TO
4.096V
ANALOG
INPUT
+2.5V **
OSCILLOSCOPE
CH1 CH2 CH3 CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**OPTIONAL. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
MAX192
+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5. Quick-Look Circuit
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
12 ______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
1 4 8 12 16 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B9
MSB B8 B7 B6 B5 B4 B3 B2 B1 B0
LSB S1 SO
ACQUISITION
1.5µs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
tACQ
A/D STATE
RB1
RB1 RB2 RB3
RB2 RB3
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
tCSH tCSS tCL
tDS tDH
tDV
tCH
tDO tTR
tCSH
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
Pulling CS high prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
and out of the MAX192 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time,
tAZ, is kept above 1.5µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after VDD is applied.
OR
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
If a falling edge on CS forces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX192. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX192 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have been sta-
bilized, the internal reset time is 100µs and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT will shift out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample -and-hold.
To select external compensation, float SHDN. See the
Typical Operating Circuit
, which uses a 4.7µF capacitor
at VREF. A value of 4.7µF or greater ensures stability
and allows operation of the converter at the full clock
speed of 2MHz. External compensation increases
power-up time (see the
Choosing Power-Down Mode
section, and Table 5).
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal
compensation allows for shortest power-up times, but is
only available using an external clock and reduces the
maximum clock rate to 400kHz.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 13
• • •
• • • • • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
• • • • • • • •
SSTRB
CS
SCLK
DIN
DOUT
1 4 8 12 18 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B9
MSB B8 B7 B0
LSB S1 S0
ACQUISITION
1.5µs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
10µs MAX
A/D STATE
2 3 5 6 7 9 10 11 19 21 22 23
tCONV
Figure 8. External Clock Mode SSTRB Detailed Timing
Figure 9. Internal Clock Mode Timing
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
14 ______________________________________________________________________________________
PD0 CLOCK IN
tSSTRB
tCSH
tCONV tSCK
SSTRB
SCLK
tCSS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2S
18 1 8 1
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6
CONVERSION RESULT 1
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN either
high or floating (see Tables 3 and 6). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of DIN word (see Table 7).
Full power-down mode turns off all chip functions that
draw quiescent current, typically reducing IDD to 2µA.
Fast power-down mode turns off all circuitry except the
bandgap reference. With the fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.
In both software shutdown modes, the serial interface
remains operational, however, the ADC will not convert.
Table 5 illustrates how the choice of reference-buffer
compensation and power-down mode affects both
power-up delay and maximum sample rate.
In external compensation mode, the power-up time is
20ms with a 4.7µF compensation capacitor when the
capacitor is fully discharged. In fast power-down, you
can eliminate start-up time by using low-leakage capaci-
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 15
POWERED UP FULL
POWER-
DOWN
POWERED
UP
POWERED UP
DATA VALID
(10 + 2 DATA BITS) DATA VALID
(10 + 2 DATA BITS) DATA INVALID
VALID
EXTERNAL
EXTERNAL
INTERNAL
SXXXXX1 1 S 0 1
X XXXX X X X X X
S 1 1
FAST
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN SETS EXTERNAL
CLOCK MODE SETS EXTERNAL
CLOCK MODE
SETS FAST
POWER-DOWN
MODE
Figure 12a. Timing Diagram Power-Down Modes, External Clock
FULL
POWER-DOWN POWERED
UP
POWERED UP
DATA VALID DATA VALID
INTERNAL CLOCK MODE
SXXXXX1 0 S 0 0
X XXXX S
MODE
DOUT
DIN
CLOCK
MODE SETS INTERNAL
CLOCK MODE SETS FULL
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
16 ______________________________________________________________________________________
Reference Reference- VREF Power- Power-Up Maximum
Buffer Buffer Capacitor Down Delay Sampling
Compensation (µF) Mode (sec) Rate (ksps)
Mode
Enabled Internal Fast 5µ 26
Enabled Internal Full 300µ 26
Enabled External 4.7 Fast See Figure 14c 133
Enabled External 4.7 Full See Figure 14c 133
Disabled Fast 2µ 133
Disabled Full 2µ 133
Table 5. Worst-Case Power-Up Delay Times
PD1 PD0 Device Mode
1 1 External Clock Mode
1 0 Internal Clock Mode
0 1 Fast Power-Down Mode
0 0 Full Power-Down Mode
SSHHDDNNDevice Reference-Buffer
State Mode Compensation
1 Enabled Internal Compensation
Floating Enabled External Compensation
0Full Power-Down N/A
tors that will not discharge more than 1/2LSB while shut
down. In shutdown, the capacitor has to supply the cur-
rent into the reference (1.5µA typ) and the transient cur-
rents at power-up.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX192 has already entered a software
power-down.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX192. Following the start bit,
the data input word or control byte also determines
clock and power-down modes. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD1 = 0, a power-down will resume after
one conversion.
Hardware Power-Down
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shutdown
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
Power-Down Sequencing
The MAX192 auto power-down modes can save con-
siderable power when operating at less than maximum
sample rates. The following discussion illustrates the
various power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different
power-down sequences. Other combinations of clock
rates, compensation modes, and power-down modes
may give lowest power consumption in other applica-
tions.
Figure 14a depicts the MAX192 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensa-
tion. A 0.01µF bypass capacitor at REFADJ forms an
Table 7. Hard-Wired Shutdown and
Compensation Mode
Table 6. Software Shutdown and Clock
Mode
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 17
1 0 0
DIN
REFADJ
VREF
2.5V
0V
4V
0V
1 0 1 1 11 1 0 0 1 0 1
FULLPD FASTPD NOPD FULLPD FASTPD
2ms WAIT
COMPLETE CONVERSION SEQUENCE
tBUFFEN ≈ 15µs
τ = RC = 20kΩ x CREFADJ
(ZEROS) CH1 CH7 (ZEROS)
Figure 13. FULLPD/FASTPD Power-Up Sequence
RC filter with the internal 20kΩreference resistor with a
0.2ms time constant. To achieve full 10-bit accuracy,
10 time constants or 2ms are required after power-up.
Waiting 2ms in FASTPD mode instead of full power-up
will reduce the power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 13.
Lowest Power at Higher Throughputs
Figure 14b shows the power consumption with
external-reference compensation in fast power-down,
with one and eight channels converted. The external
4.7µF compensation requires a 50µs wait after
power-up, accomplished by 75 idle clocks after a
dummy conversion. This circuit combines fast
multi-channel conversion with lowest power consump-
tion possible. Full power-down mode may provide
increased power savings in applications where the
1000
10 100 300 500
FULL POWER-DOWN
10
100
MAX192-14A
CONVERSIONS PER CHANNEL PER SECOND
200 400
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
8 CHANNELS
1 CHANNEL
AVG. SUPPLY CURRENT (µA)
10,000
10 0
FAST POWER-DOWN
100
1000
CONVERSIONS PER CHANNEL PER SECOND
8 CHANNELS 1 CHANNEL
4k 8k 12k 16k
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
AVG. SUPPLY CURRENT (µA)
MAX192-14B
3.0
2.5
2.0
1.5
1.0
0.5
00.0001 0.001 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)
POWER-UP DELAY (ms)
Figure 14a. Supply Current vs. Sample Rate/Second, FULLPD,
400kHz Clock Figure 14b. Supply Current vs. Sample Rate/Second, FASTPD,
2MHz Clock
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
MAX192
MAX192 is inactive for long periods of time, but where
intermittent bursts of high-speed conversions are
required.
External and Internal References
The MAX192 can be used with an internal or external
reference. Diode D1 shown in the
Typical Operating
Circuit
ensures correct start-up. Any standard signal
diode can be used. An external reference can either be
connected directly at the VREF terminal or at the
REFADJ pin.
The MAX192’s internally trimmed 2.46V reference is
buffered with a gain of 1.678 to scale an external 2.5V
reference at REFADJ to 4.096V at VREF.
Internal Reference
The full-scale range of the MAX192 with internal reference
is 4.096V with unipolar inputs, and ±2.048V with differen-
tial bipolar inputs. The internal reference voltage is
adjustable to ±1.5% with the Reference-Adjust Circuit of
Figure 17.
External Reference
An external reference can be placed at either the
input (REFADJ) or the output (VREF) of the internal
buffer amplifier. The REFADJ input impedance is
typically 20kΩ. At VREF, the input impedance is a
minimum of 12kΩfor DC currents. During conversion,
an external reference at VREF must be able to deliver
up to 350µA DC load current and have an output
impedance of 10Ωor less. If the reference has higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
Using the buffered REFADJ input avoids external
buffering of the reference. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD.
Transfer Function and Gain Adjust
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the differ -
ential bipolar input/output transfer function. Code
transitions occur halfway between successive integer
LSB values. Output coding is binary with
1LSB = 4.00mV (4.096V / 1024) for unipolar operation
and 1LSB = 4.00mV [(4.096V / 2 - -4.096V / 2)/1024]
for bipolar operation.
Figure 17, the Reference-Adjust Circuit, shows how to
adjust the ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±15LSBs) of
gain adjustment range.
Low-Power, 8-Channel,
Serial 10-Bit ADC
18 ______________________________________________________________________________________
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000 1 2 3
0FS
FS - 3/2LSB
FS = +4.096V
1LSB = FS
1024
INPUT VOLTAGE (LSBs)
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
-FS 0V
DIFFERENTIAL INPUT VOLTAGE (LSBs)
+FS - 1LSB
FS = +4.096
2
1LSB = +4.096
1024
OUTPUT CODE
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale Figure 16. Differential Bipolar Transfer Function,
±4.096V / 2 = Full Scale
Layout, Grounding, Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at AGND, sepa-
rate from the logic ground. All other analog grounds
and DGND should be connected to this ground. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped-
ance and as short as possible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
0.1µF and 4.7µF bypass capacitors close to the
MAX192. Minimize capacitor lead lengths for best sup-
ply-noise rejection. If the +5V power supply is very
noisy, a 10Ωresistor can be connected as a lowpass
filter, as shown in Figure 18.
High-Speed Digital Interfacing
The MAX192 can interface with QSPI at high through-
put rates using the circuit in Figure 19. This QSPI circuit
can be programmed to do a conversion on each of the
eight channels. The result is stored in memory without
taxing the CPU since QSPI incorporates its own
micro-sequencer.
Figure 20 details the code that sets up QSPI for
autonomous operation. In external clock mode, the
MAX192 performs a single-ended, unipolar conversion
on each of the eight analog input channels. Figure 21
shows the timing associated with the assembly code of
Figure 20. The first byte clocked into the MAX192 is the
control byte, which triggers the first conversion on CH0.
The last two bytes clocked into the MAX192 are all
zero, and clock out the results of the CH7 conversion.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 19
+5V
510k
100k
24k 0.01µF
12 REFADJ
MAX192
Figure 17. Reference-Adjust Circuit
+5V GND
SUPPLIES
DGND+5VDGND
AGNDVDD
DIGITAL
CIRCUITRY
MAX192
R* = 10Ω
* OPTIONAL
Figure 18. Power-Supply Grounding Connection
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
20 ______________________________________________________________________________________
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MAX192
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
SHDN
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREF
VDDI, VDDE, VDDSYN, VSTBY
SCK
PCS0
MOSI
MISO
* CLOCK CONNECTIONS NOT SHOWN
VSSI VSSE
MC68HC16
0.1µF 4.7µF
0.01µF
0.1µF4.7µF
ANALOG
INPUTS
+5V
+
Figure 19. MAX192 QSPI Connection
TMS320 to MAX192 Interface
Figure 22 shows an application circuit to interface the
MAX192 to the TMS320 in external clock mode. The
timing diagram for this interface circuit is shown in
Figure 23.
Use the following steps to initiate a conversion in the
MAX192 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR of the TMS320 are
tied together with the SCLK input of the MAX192.
2) The MAX192 CS is driven low by the XF_ I/O port
of the TMS320 to enable data to be clocked into
DIN of the MAX192.
3) An 8-bit word (1XXXXX11) should be written to the
MAX192 to initiate a conversion and place the
device into external clock mode. Refer to Table 3
to select the proper XXXXX bit values for your spe-
cific application.
4) The SSTRB output of the MAX192 is monitored via
the FSR input of the TMS320. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from
the MAX192.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10-bit conversion result and two sub-
LSBs, followed by four trailing bits, which should
be ignored.
6) Pull CS high to disable the MAX192 until the next
conversion is initiated.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 21
* Description :
* This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM
* is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software
* provided in the Motorola 68HC16 Evaluation Kit.
*
* Roger J.A. Chen, Applications Engineer
* MAXIM Integrated Products
* November 20, 1992
*
******************************************************************************************************************************************************
INCLUDE ‘EQUATES.ASM’ ;Equates for common reg addrs
INCLUDE ‘ORG00000.ASM’ ;initialize reset vector
INCLUDE ‘ORG00008.ASM’ ;initialize interrupt vectors
ORG $0200 ;start program after interrupt vectors
INCLUDE ‘INITSYS.ASM’ ;set EK=F,XK=0,YK=0,ZK=0
;set sys clock at 16.78 MHz, COP off
INCLUDE ‘INITRAM.ASM’ ;turn on internal SRAM at $10000
;set stack (SK=1, SP=03FE)
MAIN:
JSR INITQSPI
MAINLOOP:
JSR READ192
WAIT:
LDAA SPSR
ANDA #$80
BEQ WAIT ;wait for QSPI to finish
BRA MAINLOOP
ENDPROGRAM:
INITQSPI:
;This routine sets up the QSPI microsequencer to operate on its own.
;The sequencer will read all eight channels of a MAX192 each time
;it is triggered. The A/D converter results will be left in the
;receive data RAM. Each 16 bit receive data RAM location will
;have a leading zero, 10 + 2 bits of conversion result and three zeros.
;
;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
;A/D Result 0 MSB LSB 0 0 0
***** Initialize the QSPI Registers ******
PSHA
PSHB
LDAA #%01111000
STAA QPDR ;idle state for PCS0-3 = high
LDAA #%01111011
STAA QPAR ;assign port D to be QSPI
LDAA #%01111110
STAA QDDR ;only MISO is an input
LDD #$8008
STD SPCR0 ;master mode,16 bits/transfer,
;CPOL=CPHA=0,1MHz Ser Clock
LDD #$0000
STD SPCR1 ;set delay between PCS0 and SCK,
;set delay between transfers
Figure 20. MAX192 Assembly-Code Listing
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
22 ______________________________________________________________________________________
LDD #$0800
STD SPCR2 ;set ENDQP to $8 for 9 transfers
***** Initialize QSPI Command RAM *****
LDAA #$80 ;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD40 ;store first byte in COMMAND RAM
LDAA #$C0 ;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD41
STAA $FD42
STAA $FD43
STAA $FD44
STAA $FD45
STAA $FD46
STAA $FD47
LDAA #$40 ;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD48
***** Initialize QSPI Transmit RAM *****
LDD #$008F STD $FD20
LDD #$00CF STD $FD22
LDD #$009F STD $FD24
LDD #$00DF STD $FD26
LDD #$00AF STD $FD28
LDD #$00EF STD $FD2A
LDD #$00BF STD $FD2C
LDD #$00FF STD $FD2E
LDD #$0000 STD $FD30
PULB
PULA
RTS
READ192:
;This routine triggers the QSPI microsequencer to autonomously
;trigger conversions on all 8 channels of the MAX192. Each
;conversion result is stored in the receive data RAM.
PSHA
LDAA #$80
ORAA SPCR1
STAA SPCR1 ;just set SPE
PULA
RTS
***** Interrupts/Exceptions *****
BDM: BGND ;exception vectors point here
;and put the user in background debug mode
Figure 20. MAX192 Assembly-Code Listing (continued)
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________ 23
• • • •
• • • •
• • • •
• • • •
CS
SCLK
SSTRB
DIN
Figure 21. QSPI Assembly-Code Timing
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320
MAX192
Figure 22. MAX192 to TMS320 Serial Interface
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB B10 S1 S0 HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 23. TMS320 Serial-Interface Timing Diagram
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
Typical Operating Circuit Chip Information
VDD
I/O
SCK (SK)*
MOSI (SO)
MISO (SI)
VSS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
AGND
AGND
DGND
VDD
REFADJ
CH7
C3
0.1µFC4
0.1µF
CH0
+5V
C2
0.01µF
0V to
4.096V
ANALOG
INPUTS
MAX192
CPU
C1
4.7µF
VREF
TRANSISTOR COUNT: 2278
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
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