1/26Decemb er 200 4
M36W0R6030T0
M36W0R6030B0
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
FEATURES SUMMARY
■MULTI-CHIP PACKAGE
– 1 die of 64 Mbit (4Mb x 16) Flash Memory
– 1 die of 8 Mbit SRAM
■SUPPLY VOLTAGE
–V
DDF = VDDQ = VDDS = 1.7 to 1.95V
■LOW POWER CONSUMPTION
■ELECTRONIC SIGNATURE
– Manufactu rer Code : 20h
– Device Code (Top Flash Configuration):
8810h
– Device Code (Bottom Fl ash
Configuration): 8811h
■PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 66MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70ns
■DUAL OPERATIONS
– Pr ogram Er ase in one Ban k while Re ad in
others
– No delay between Read and Write
operations
Figure 1. Package
■BLOCK LOCKING
– All blocks lock ed at Powe r-up
– Any combination of blocks can be locked
–WP
F for Block Lock-Down
■SECURITY
– 128-bit user programmable OTP cells
– 64-bit unique device number
■COMMON FLASH INTERFACE (CFI)
■100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
■8 Mbit (512Kb x 16 bit)
■ACCESS TIME: 70ns
■LOW VDDS DATA RETENTION: 1.0V
■POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
FBGA
Stacked TF BGA88
(ZAQ)
M36W0R6030T0, M36W0R6030B0
2/26
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Chip Enable inputs (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Write Enable (WS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDS Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/26
M36W0R6030T0, M36W0R6030B0
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . . . . . . . . 16
Figure 9. Read AC Waveforms, GS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Write AC Waveforms, E1S or E2 S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.Write AC Waveforms, WS Controlled, GS High during Write. . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.Write AC Waveform, UBS and LBS Controlled GS Low. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.SRAM Low VDD Data Retention AC Waveforms, E1S or UBS / LBS Controlled . . . . . . . 22
Figure 16.SRAM Low VDD Data Retention AC Waveforms, E2S Controlled. . . . . . . . . . . . . . . . . . 22
Table 11. SRAM Low VDD Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 23
Table 12. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M36W0R6030T0, M36W0R6030B0
4/26
SUMMARY D ESCRIPTION
The M36W 0R6030T0 a nd M36W 0R6030 B0 com -
bine two memory devices in a Multi-Chip Package:
a 64-Mbit, Multiple Bank Flash memory, the
M58WR064FT/B, and an 8-Mbit SRAM. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the stan dard version, the packages
are also available in Lea d-free vers ion, in c ompli-
ance with J EDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All pac ka ges are comp lia nt with Le ad- free solder-
ing processes.
is supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
Table 1. Signal Names
Note: 1. A21-A19 are not connected to the SRAM component.
AI08534C
22
A0-A21 DQ0-DQ15
M36W0R6030T
M36W0R6030B
GF
16
WF
RPF
WPF
E1S
GS
WS
UBS
LBS
VSS
VDDF
VPPF
VDDS
WAITF
LF
KF
VDDQ
EF
E2S
A0-A21 (1) Address Inputs
DQ0-DQ15 Common Data Input/Output
VDDF Flash Me mo ry Po we r Sup ply
VDDQ Common Flash and SRAM Power
Supply for I/O Buffers
VPPF Common Flash Optional Supply
Voltage for Fast Program and Erase
VSS Ground
VDDS SRAM Power Supply
NC Not Connected Internally
DU Do Not Use as Internally Connected
Flash Memory Signals
LFLatch En ab le inp ut
EFChip Enable input
GFOutput Enable input
WFWrite Enable input
RPFReset input
WPFWrite Protect input
KF Burst Clock
WAITFWait Data in Burst Mode
SRAM Signals
E1S, E2SChip Enable input
GSOutput Enable input
WSWrite Enable input
UBSUpp er Byte En ab le inp ut
LBSLow er By te En ab le inp ut
5/26
M36W0R6030T0, M36W0R6030B0
Figure 3. TFBGA Connections (Top view through package)
87654321
C
BA21
KF
A4 A11
D
E
F
DU DU
WF
VSS
A19A18
NC
A5 A12
VSS
NCLBS
A9
A3 A13
VPPF
NCA17
A10A20
A2 A15
LF
WPF
NCA7
A14A8
A1 A16
RPF
UBS
A6
WAITF
DQ13
A0 DQ5
DQ10
DQ2DQ8
DQ7DQ14
GSDQ12
DQ3
DQ1DQ0
DQ15DQ6DQ4
DQ11
DQ9GF
VDDQ
EFNC
VDDS
VSS
VSS
VSS VSS
VSS
VDDF
VDDQ
VSS
DU DU
DU
DU DU
DU
A
G
H
J
K
AI08535
L
M
VDDF NC
WS
E1S
NC
NC
NC NC NC
E2S
NC
NC
VDDQ
M36W0R6030T0, M36W0R6030B0
6/26
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). Addresses A0-A18
are common inputs fo r th e Fl ash memory an d the
SRAM components. The other lines (A19-A21) are
inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the SRAM.
The Flash memory is accessed through the Chip
Enable signal (EF) and through the Write Enable
(WF) sig nal, while the SRA M is acc essed thr ough
two Chip Enable signals (E1S and E2S) and the
Write Enable signal (WS).
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the d ata to be pr ogramme d dur ing a Write Bus
operation.
Flash Chip Enable (EF). The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low , VIL, and Reset is High, VIH, the de-
vice is in active mode. When Chip Enable is at VIH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (GF). The Output Enable
pin controls data outputs during Flash memory
Bus Read operations.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memories’ Comman d Inter face. The data an d ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that giv es an addi tional hardwa re protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Wri te Prote ct is at High, VIH, Lock-Dow n is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064FT/B datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the m emory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters As ynchronous Read mode, but a negativ e
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any addi tional circuitr y. It can be tied to VRPH
(refe r t o Table 7., Flash Memory DC Characteris-
tics - Voltages ).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is in hi bite d wh en Latc h Ena bl e i s H igh , V IH.
Latch Enable can be kept Low (also at board level)
when the Lat ch Enable function is not r equired or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched o n a Cloc k edge ( rising o r falling, accord -
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash output s ig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is a t VIH or Fl ash Reset is at VIL. It c an be con fig-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enabl e.
SRAM Chip Enable inputs (E1S, E2S). The
Chip Enable inputs activate the SRAM memory
control logic, input buffers and decoders. E1S at
VIH with E2S at VIH deselects the memory, red uc-
ing the power consumption to the standby level,
whereas E2S at VIL deselects the memory and re-
duces th e po wer c ons um ption to the Pow er-d own
level, re gardles s of the lev el of E1S. E1 S and E2S
can also be used to control writing to the SRAM
memory array, while WS remains at VIL. It is not al-
lowed to set EF at VIL, E1S at VIL and E2S at VIH at
the same time.
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs throug h the data bu ffers during
a Read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UBS is active low.
7/26
M36W0R6030T0, M36W0R6030B0
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable input enables the lower byte for
SRAM (DQ0 -DQ7). LBS is active low.
VDDF Supply Voltage. VDDF provides the power
supply to the internal core of the Flash memory
component. It is the main power supplies for all
Flash memory operations (Read, Program and
Erase).
VDDS Supply Voltage. VDDS pro vi des t he power
supply to the i nternal cor e of the SRAM d evice. It
is the main power supply for all SRAM operations.
VDDQ Supply Voltage. VDDQ provides the power
supply for the Flash Memory and SRAM I/O pins.
This allows all Outputs to be powered indepen-
dently of the Flash Memory and SRAM core power
supplies: VDDF and VDDS, respectively.
VPPF Program Supply Voltage. VPPF is both a
Flash memory control input and a Flash memory
power supply pin. The two functions are selected
by the voltage range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQ)
VPPF is seen as a control input. In this case a volt-
age lower than VPPLKF gives an absolute protec-
tion against Program or Erase, while VPPF > VPP1F
enables th ese functions ( see Tables 6 an d 7, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPHF it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers ) and SRAM chips .
Note: Each Flash memory device in a system
should have its supply voltage (VDDF) and the
program supply voltage VPPF decoupled with a
0.1µF ceramic capacit or close to the pin (high
frequency, inherently low inductance capaci-
tors should be as close as possible to the
package). See Figure 7., AC Measurement
Loa d Ci rcu it. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
M36W0R6030T0, M36W0R6030B0
8/26
FUNCTIONA L DESCRIPTION
The Flash memory and SRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: EF for the Flash memory and E1S and
E2S for the SRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read oper-
ations on one of the Flash and the SRAM which
would resu lt in a data bu s c ont enti on . T herefo re it
is recommended to put the other devices in the
high impedance state when reading the selected
device.
Figure 4. Functional Block Diagram
AI08536C
E1S
E2S
GS
WS
DQ0-DQ15
VDDF
A0-A18
A19-A21
8 Mbit SRAM
GF
UBS
LBS
WAITF
64 Mbit
Flash
Memory
VDDS
EF
KF
WF
LF
RPF
WPF
VPPF VDDQ
VSS
9/26
M36W0R6030T0, M36W0R6030B0
Table 2. Main Operating Modes
Note: 1. X = Don't care.
2. LF can be tied to VIH if the valid address has been previously latched.
3. Depends on GF.
4. WAIT sig nal polarity is con figured using t he Set Configurat ion Register command. Refer to M58WR064FT/B datasheet for details.
Operation EFGFWFLFRPFWAITF(4) E1SE2SGSWSUBSLBSDQ15-DQ0
Flash Read VIL VIL VIH VIL(2) VIH
SRAM must be disabled
Flash Data Out
Flash Write VIL VIH VIL VIL(2) VIH Flash Data In
Flash Address
Latch VIL XVIH VIL VIH Flash Data Out
or Hi-Z (3)
Flash Output
Disable VIL VIH VIH XVIH
Any SRAM mod e is allo we d
Flash Hi-Z
Flash Standby VIH XX XVIH Hi-Z Flash Hi-Z
Flash Reset X X X X VIL Hi-Z Flash Hi-Z
SRAM Read Flash memory must be disabled VIL VIH VIL VIH VIL VIL SRAM data out
SRAM Write VIL VIH XVIL VIL VIL SRAM data in
Output Dis ab le
Any Flash mode is allowed.
VIL VIH VIH VIH VIL VIL SRAM Hi-Z
SRAM Standby VIH XXXXXSRAM Hi-Z
XVIL XXXXSRAM Hi-Z
M36W0R6030T0, M36W0R6030B0
10/26
FLASH MEMORY DEVICE
The M36W0R6030T0 and M36W0R6030B0 con-
tain a 64 Mbit Flash memory. For detailed informa-
tion on how to use it, see the M58WR064FT/B
datasheet which is available from your local STMi-
croelectronics di stributor.
SRAM DEVICE
The M36W0R6030T0 and M36W0R6030B0 con-
tain an 8 Mbit SRAM. It is described in this section.
Figure 5. Block Diagram
DATA IN DRIVERS
512Kb x 16
RAM Array
2048 x 4096
COLUMN DECODER
ROW DECODER
A0-A10
WS
UBS
LBS
SENSE AMPS
A11-A18
POWER-DOWN
CIRCUIT
DQ0-DQ7
DQ8-DQ15
GS
UBS
LBS
AI08706B
E1S
E2S
E1S
E2S
11/26
M36W0R6030T0, M36W0R6030B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Power-
down, Data Retention and Output Disable.
Read. Read operations are used to output the
contents of the SRAM Array.
The devi ce is in By te R ead mode whe nev er W ri te
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at
VIH, and UBS or LBS is at VIL.
The device is in Word Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Byte Enable inputs UBS and LBS are both at VIL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures 9 and 10, respectively and the parame-
ters are given in Table 9., Read AC Characteris-
tics.
Write. Write operations are used to write data to
the SRAM. The device is in Write mode whenever
WS, E1S and UBS and/o r LBS ar e at VIL, and E2S
is at VIH. All these signals must be asserted to ini-
tiate a Wri te c ycl e. T he d ata is l atc he d on th e fa ll -
ing edge of E1S, the rising edge of E2S, the falling
edge of WS, or the falling edge of UBS and/or LBS,
whichever occurs last. The Write cycle will termi-
nate on the risi ng edge of E1S, the rising edg e of
WS, the rising edge of UBS and/or LBS, or the fall-
ing edge of E2S, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1S, at VIL, E2S at VIH, and WS at VIL).
The Write AC Waveforms are shown in Figures
11, 12, 13 and 14, while Table 10. gives the Wr ite
AC Characteristics.
Standby/Power-Down. The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, ISB.
The devi ce is also i n Standby/ Power-Do wn mode
whenever E1 S is at VIH, E2S is at VIL or both UBS
and LBS are at VIH. The outputs then become high
impedance.
The Stan dby AC Wa veforms are sho wn in Figure
10. See Table 9., Read AC Characteristics, for
timings.
Data Retention. The data retention mode is en-
tered tCDR after de-asserting E1S, E2S or U BS and
LBS. The data retention performance as VDD goes
down to VDR is described in Table 11., Figures 15
and 16, SRAM Low VDD Data Retention AC Wave-
forms, E1S or UBS / LBS Controlled and SRAM
Low VDD Data Retention AC Waveforms, E2S
Controlled, respectively.
Output Disable. The device i s in the O utput Dis -
able mode whenever GS, is at VIH. In this mode,
DQ0-DQ15 are high impedance.
M36W0R6030T0, M36W0R6030B0
12/26
MAXIMUM RATING
Stressing the dev ice above the ratin g lis ted in the
Absolute Maximum Ratin gs table ma y cause pe r-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other cond itions above thos e indicated i n the
Operating sections of this specification is not im-
plie d. Exposu re to Abso lute Max imum Rat ing con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Symbol Parameter Value Unit
Min Max
TAAmbie nt Op era tin g Temperatur e –40 85 °C
TBIAS Temperature Under Bias –40 125 °C
TSTG Storage Temperature –65 155 °C
TLEAD Lead Temperature during Soldering (1) °C
VIO Input or Output Voltage –0.5 VDDQ+0.6 V
VDDF Flash Me mo ry Co re Su pp ly Voltage –0.2 2.45 V
VDDQ Input/Output Supply Voltage –0.2 2.45 V
VDDS SRAM Supply Voltage –0.2 2.4 V
VPPF Flas h Me mo ry Program Voltage –0.2 14 V
IOOutput Short Circuit Current 100 mA
tVPPFH Time for VPPF at VPPFH 100 hours
13/26
M36W0R6030T0, M36W0R6030B0
DC AND AC PARA METERS
This section summarizes the operating measure-
ment condi tions, an d the DC and AC characteri s-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit
Tab le 5. Device Capacitance
Note: Sampled only, not 100% tested.
Parameter Flash Memory SRAM Unit
Min Max Min Max
VDDF Supply Voltage 1.7 1.95 – – V
VDDS Supply Voltage ––1.71.95V
VDDQ Supply Voltage 1.7 1.95 – – V
VPPF Supply Voltage (Factory environment) 11.4 12.6 – – V
VPPF Supply Voltage (Application environment) –0.4 VDDQ +0.4 ––V
Ambient Operating Temperature –40 85 –40 85 °C
Load Capacitance (CL)30 30 pF
Output Cir cui t Resi sto rs (R1, R2)16.7 16.7 kΩ
Input Rise and Fall Times 5 2 ns
Input Pulse Voltages 0 to VDDQ 0 to VDDS V
Input and Output Timing Ref. Voltages VDDQ/2 VDDS/2 V
AI06161
VDDQ
0V
VDDQ/2
AI08364B
V
DDQ
C
L
C
L
includes JIG capacitance
R
1
DEVICE
UNDER
TEST
0.1µF
V
DDQ
R
2
0.1µF
V
DDF
Symb ol Pa ra me te r Test Co nd itio n Min M ax Unit
CIN Input Capacitance VIN = 0V 12 pF
COUT Output Capacitance VOUT = 0V 15 pF
M36W0R6030T0, M36W0R6030B0
14/26
Table 6. Flash Memory DC Characteristics - Currents
Note: 1. Sampled only, not 100% tested.
2. VDDF Dual Operation curren t is the sum of read and progr am or erase currents.
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VDDQ ±1 µA
ILO Output Le aka ge Curr en t 0V ≤ VOUT ≤ VDDQ ±1 µA
IDD1
Supply Cu rre nt
Asynchronous Read (f=6MHz) E = VIL, G = VIH 36mA
Supply Cu rre nt
Synchronous Read (f=54MHz)
4 Word 7 16 mA
8 Word 10 18 mA
16 Word 12 22 mA
Continuous 13 25 mA
Supply Cu rre nt
Synchronous Read (f=66MHz)
4 Word 8 17 mA
8 Word 11 20 mA
16 Word 14 25 mA
Continuous 16 30 mA
IDD2 Supply Cu rre nt (Re se t) RP = VSS ± 0.2V 10 50 µA
IDD3 Supply Cu rre nt (Standb y) E = VDD ± 0.2V 10 50 µA
IDD4 Supply Cu rre nt (Au to ma tic Standb y) E = VIL, G = VIH 10 50 µA
IDD5 (1)
Supply Cu rre nt (Pr og ram ) VPP = VPPH 815mA
VPP = VDD 10 20 mA
Supply Cu rre nt (Er ase ) VPP = VPPH 815mA
VPP = VDD 10 20 mA
IDD6 (1,2) Supply Cu rre nt
(Dual Operations)
Program/Erase in one
Bank, Asynchronous
Read in another Bank 13 26 mA
Program/Erase in one
Bank, Synchronous
Read in another Bank 23 45 mA
IDD7(1) Supply Cu rre nt Pro gr am / Eras e
Suspended (Standby) E = VDD ± 0.2V 10 50 µA
IPP1(1)
VPP Supply Current (Program) VPP = VPPH 25mA
VPP = VDD 0.2 5 µA
VPP Supply Current (Erase) VPP = VPPH 25mA
VPP = VDD 0.2 5 µA
IPP2 VPP Supply Current (Read) VPP ≤ VDD 0.2 5 µA
IPP3(1) VPP Supply Current (Standby) VPP ≤ VDD 0.2 5 µA
15/26
M36W0R6030T0, M36W0R6030B0
Table 7. Flash Memory DC Characteristics - Voltages
Table 8. SRAM DC Characteristics
Symbol Parameter Test Condition Min Typ Max Unit
VIL Input Low Voltage –0.5 0.4 V
VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V
VOL Output Lo w Voltage IOL = 100µA 0.1 V
VOH Output Hig h Voltage IOH = –100µA VDDQ –0.1 V
VPP1 VPP Program Voltage-Logic Program , Era se 1.1 1.8 3.3 V
VPPH VPP Progr am Voltage Facto r y Program , Era se 11.4 12 12.6 V
VPPLK Program or Erase Lockout 0.4 V
VLKO VDD Lock Voltage 1V
VRPH RP pin Extended High Voltage 3.3 V
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage
Current 0V ≤ VIN ≤ VDD ±1 µA
ILO Output Leakage
Current 0V ≤ VOUT ≤ VDD, Output disabled ±1 µA
IDDS VDD Standby
Current
E1S ≥ VDD – 0.2V or E2S ≤ 0.2V
VIN ≥ VDD – 0.2V or VIN ≤ 0.2V
f = fmax (Address and Data inputs only)
f = 0 (GS, WS, UBS and LBS)
225µA
E1S ≥ VDD – 0.2V or E2S ≤ 0.2V
VIN ≥ VDD – 0.2V or VIN ≤ 0.2V
f = 0, VDD(max) 225µA
IDD Supply Current f = fmax = 1/tAVAV, CMOS levels VDD = VDD(max) 815mA
IOUT = 0 mA, f = 1MHz, CMOS levels 15mA
VIL Input Low
Voltage –0.2 0.4 V
VIH Input High
Voltage 1.4 VDD+0.2 V
VOL Output Low
Voltage IOL = 0.1mA, VDD = 1.65V 0.2 V
VOH Output High
Voltage IOH = −0.1mA, VDD = 1.65V 1.4 V
M36W0R6030T0, M36W0R6030B0
16/26
Figure 8. Read Mode AC Waveforms, Address Controlled with UBS = LB S = VIL
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 9. Read AC Waveforms, GS Controlled
Note: 1. UBS, LBS means both UBS and LBS.
2. Write Enable (WS) = High. Address Valid prior to or at the same time as E1S and UBS, LBS go Low and E2S goes High.
Figure 10. Standby AC Waveforms
AI08199
tAVAV
tAVQV
tAVQX
A0-A18
DQ0-DQ15
VALID
DATA VALIDDATA VALID
AI08191C
tE1LE1H
tE2HE2L
tE1LQV
tE2HQV tE1HQZ
tGLQV
tGLQX
tGHQZ
DATA VALID
A0-A18
E1
S
G
S
DQ0-DQ15
tE1LQX
tE2HQX
VALID
tE2LQZ
E2
S
LB
S
, UB
S
tBLQX tBHQZ
AI08192
tPD
E2
S
I
DD
tPU
50%
E1
S
I
DDS
17/26
M36W0R6030T0, M36W0R6030B0
Tab le 9. Read AC Characteristics
Note: 1. Sampled only. Not 100% tested.
2. Whatever the temperature and voltage, tE1HDZ and tE2LDZ are less than tE1LDX and tE2HDX; tBHDZ is less than tBLDX and, tGHDZ is
less than tGHDX.
Symbol Alt Parameter M36W0R6030T0, M36W0R6030B0 Unit
Min Max
tAVAV
tE1LE1H
tE2HE2L tRC Read Cycle Time 70 ns
tAVQV tAA Address Valid to Output Valid 70 ns
tAVQX tOHA Address Transition to Output Transition 10 ns
tBHQZ(2) tHZBE Byte Enab le Hig h to Da ta Hi-Z 25 n s
tBLQV tDBE Byte Enable Low to Data Valid 70 ns
tBLQX(2) tLZBE Byte Enable Low to Data Transition 5 ns
tE1HQZ
tE2LQZ tHZCE Chip Enable 1 High or Chip Enable 2 Low to Data
Hi-Z 25 ns
tE1LQV
tE2HQV tACE Chip Enable 1 Low or Chip Enable 2 High to Data
Valid 70 ns
tE1LQX
tE2HQX tLZCE Chip Enable 1 Low or Chip Enable 2 High to Data
Transition 10 ns
tGHQZ tHZOE Output Enable High to Data Hi-Z 25 ns
tGLQV tDOE Output Enable Low to Data Valid 35 ns
tGLQX tLZOE Output Enable Low to Data Transition 5 ns
tPD(1) Chip Enable 1 High or Chip Enable 2 Low to
Pow er Down 70 ns
tPU(1) Chip Enable 1 Low or Chip Enable 2 High to
Power Up 0ns
M36W0R6030T0, M36W0R6030B0
18/26
Figure 11. Write AC Waveforms, E1S or E2S Controlled
Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
2. The I/O pins are in output mode and input signals should not be applied.
3. If E1S, E2 S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
4. UBS, LBS means both UBS and LBS.
AI08193B
tAVAV
tE1HAX
tDVE1H
tDVE2L
INPUT VALID
A0-A18
E1
S
W
S
DQ0-DQ15
VALID
E2
S
tAVE1H
tAVE2L
tBLE1H
tBLE2L
tGHDZ tE1HDX
tE2LDX
tAVE1L
UB
S
, LB
S
tE2HE2L
tE1LE1H
G
S
tWLE1H
tWLE2L
tAVE2H tE2LAX
Note 2
19/26
M36W0R6030T0, M36W0R6030B0
Figure 12. Write AC Waveforms, WS Controlled, GS High during Write
Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.
2. The I/O pins are in output mode and input signals should not be applied.
3. If E1S, E2 S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
4. UBS, LBS means both UBS and LBS.
AI08194B
tAVAV
tWHAX
tDVWH
INPUT VALID
A0-A18
E1
S
W
S
DQ0-DQ15
VALID
E2
S
tAVWH
tBLWH
tGHDX tWHDX
tAVWL
UB
S
, LB
S
tE2HWH
tE1LWH
G
S
tWLWH
Note 2
M36W0R6030T0, M36W0R6030B0
20/26
Figure 13. Write AC Waveforms, WS Controlled with GS Low
Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.
2. If E1S, E2 S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
3. UBS, LBS means both UBS and LBS.
Figure 14. Write AC Waveform, UBS and LBS Controlled GS Low
Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
2. The I/O pins are in output mode and input signals should not be applied.
3. UBS, LBS means both UBS and LBS.
AI08195B
tAVAV
tWHAX
tDVWH
INPUT VALID
A0-A18
E1S
WS
DQ0-DQ15
VALID
E2S
tAVWH
tWLWHtAVWL
tWHDZ
tWHDX
tBLWH
UBS, LBS
tE1LWH
tE2HWH
tWLDZ
Note 1
AI08196B
tAVAV
tBHAX
tDVBH
INPUT VALID
A0-A18
E1
S
W
S
DQ0-DQ15
VALID
E2
S
tAVBH
tWLBH
tAVBL
tBHDX
tBLBH
UB
S
, LB
S
tE1LBH
tE2HBH
Note 2
21/26
M36W0R6030T0, M36W0R6030B0
Table 10. Write AC Characteristics
Note: 1. Whatever the temperatu r e and voltage, tWLDZ is less than tWHDX.
Symbol Alt Parameter M36W0R6030T0, M36W0R6030B0 Unit
Min Max
tAVAV tWC Write Cycle Time 70 ns
tAVE1L,
tAVE2H,
tAVWL
tAVBL
tSA Address Va lid to Be gin ning of Write 0 ns
tAVWH
tAVE1H
tAVE2L
tAVBH
tAW Address Valid to Write Enable High 60 ns
tBLWH
tBLE1H
tBLE2L
tBLBH
tBW UBS, LBS Valid to End of Write 60 ns
tDVE1H,
tDVE2L,
tDVWH
tDVBH
tSD Input Valid to End of Write 30 ns
tE1HAX,
tE2LAX,
tWHAX
tBHAX
tHA End of Write to Address Change 0 ns
tE1HDX,
tE2LDX,
tWHDX
tBHDX
tHD Data Transiti on to En d of Write 0 n s
tE1LE1H,
tE2HE2L,
tE1LWH
tE2HWH
tE1LBH,
tE2HBH
tSCE Chip Enable 1 Low or Chip Enable 2 High to
End of Write 60 ns
tGHDZ tHZOE Output Enable High to Output Hi-Z 25 ns
tWHDZ(1) tLZWE Write Enable High to Input Transition 10 ns
tWLDZ(1) tHZWE Write Enable Low to Output Hi-Z 25 ns
tWLWH
tWLE1H
tWLE2L
tWLBH
tPWE Write Enable Pulse Width 50 ns
M36W0R6030T0, M36W0R6030B0
22/26
Figure 15. SRAM Low VDD Data Retention AC Waveforms, E1S or UBS / LBS Controlled
Figure 16. SRAM Low VDD Data Retention AC Waveforms, E2S Controlled
Table 11. SRAM Low VDD Data Retention Characteristic
Note: 1. Sampled only. Not 100% tested.
Symbol Parameter Test Condition Min Max Unit
IDDDR Supply Current
(Data Retention)
VDDS = 1.0V, E1S ≥ VDDS – 0.2V
or E2S ≤ 0.2V,
VIN ≥ VDDS – 0.2V or VIN ≤ 0.2V 10 µA
VDR Supply Voltage
(Data Retention) 1.0 V
tCDR Chip Disable to Power Down 0 ns
tROperation Recovery Time 70 ns
AI08197B
E1
S
or UB
S
, LB
S
tCDR
V
DDS
tR
DATA RETENTION MODE
V
DDS (min)
V
DDS (min)
V
DR
AI08198B
E2
S
tCDR
V
DDS
tR
DATA RETENTION MODE
V
DDS (min)
V
DDS (min)
V
DR
23/26
M36W0R6030T0, M36W0R6030B0
PACKAGE MECHANICAL
Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline
Note: Drawing is not to scale.
Table 12. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.200 0.0079
A2 0.850 0.0335
b 0.350 0.300 0.400 0.0138 0.0118 0.0157
D 8.000 7.900 8.100 0.3150 0.3110 0.3189
D1 5.600 0.2205
ddd 0.100 0.0039
E 10.000 9.900 10.100 0.3937 0.3898 0.3976
E1 7.200 0.2835
E2 8.800 0.3465
e 0.800 – – 0.0315 – –
FD 1.200 0.0472
FE 1.400 0.0551
FE1 0.600 0.0236
SD 0.400 0.0157
SE 0.400 0.0157
A2
A1
A
BGA-Z42
ddd
D
E
e
b
SE
FD
E2
D1
SD
BALL "A1"
E1
FE FE1
M36W0R6030T0, M36W0R6030B0
24/26
PART NUMBERING
Table 13. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-
Microelectronics Sales Office nearest to you.
Example: M36W0 R 6 0 3 0 T 0 ZAQ T
Device Type
M36 = Multi-Chip Package (Flash + RAM)
Flash 1 Architecture
W = Multiple Bank, Burst mode
Flash 2 Architecture
0 = none present
Operatin g Voltage
R = VDDF = VDDQ =VDDP = 1.7 to 1.95V
Flash 1 Density
6 = 64 Mbit
Flash 2 Density
0 = none present
RAM 1 Densit y
3 = 8 Mbit
RAM 0 Densit y
0 = none present
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
0 = 0.13µm Flash technology, 70ns; 0.13µm RAM, 70ns speed
Package
ZAQ = Stacke d TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free and RoHS Package, Standard Packing
F = Lead-free and RoHS Package, Tape & Reel Packing
25/26
M36W0R6030T0, M36W0R6030B0
REVISION HISTORY
Table 14. Document Revision History
Date Version Revision Details
03-Jul-2003 1.0 First Issue
12-Nov-2003 2.0
Part num be rs M3 6W0R60 20 T0 and M3 6W 0R 6 020 T0 rem ove d (4M b SR AM part
removed), Figures 2, 4 and 5 modified accordingly.
0.15µm SRAM technology upgraded with new 0.13µm technology (see Table
13., Ordering Information Scheme).
Flash memory device M30W0T6000(T/B)0 replaced by the M58WR064E(T/B).
Product promoted from Product Preview to Preliminary Data.
28-Jul-2004 3.0
0.15µm Flash memory technology replaced by 0.13µm technology (M58WR064ET/B
replaced by M58WR064FT/B, Table 6., Flash Memory DC Ch aracteristics - Currents
and Table 7., Flash Memory DC Characteristics - Voltages updated accordingly).
Package specifications (Tab le 12 .) updated and E and F lead-free options added to
Table 13., Ordering Information Scheme.
10-Dec-2004 4.0
Docum en t status prom ote d from Pre lim ina ry Da ta to full Datashe et .
IDD6 parameter for Program/Erase in one Bank, Synchronous Read in another Bank
modified in Table 6., Flash Memory DC Characteristics - Currents. VDDQ max
modified in Table 3., Absolute Maximum Ratings.
TFBGA88 package fully compliant with the ST ECOPACK specification.
M36W0R6030T0, M36W0R6030B0
26/26
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