QorIQ Multicore Processor Development QorIQ P5020 Development System Overview The QorIQ P5020DS is a flexible development system based on the dual-core 32/64-bit moded P5020 device. The board, with its 2.0 GHz P5020 and rich I/O mix, is intended for evaluation of the QorIQ P5020/ P5010 processor in networking, telecom and industrial applications, where its highperformance, high-efficiency core and integration make it very well suited as a control plane processor. The P5020 development system, which exercises most capabilities of the P5020 processor, can serve as a reference for the customer's own hardware development, as a debug tool to check behaviors on the board compared to behaviors seen on customer boards or be used for software development and performance evaluation prior to completion of the customer's own board. The P5020/P5010 processors are based upon the e5500 core, built on Power Architecture(R) technology, offering speeds of 1.6 to 2.0 GHz. They feature a three-level cache hierarchy with 32 KB of instruction and data cache per core, 512 KB of unified backside L2 cache per core, and 2 MB of shared frontside CoreNet platform cache fronting the dual memory controllers. The I/O includes 18 SerDes lanes running at up to 5 GHz, multiplexed across four PCI Express(R) gen. 2.0 controllers, one 10 GE XAUI interface, four 1 GbE SGMII interfaces, two Serial RapidIO(R) (version 1.3 with features of version 2.1) interfaces, four 2.5 Gb/s SGMII interfaces, two SATA 2.0 interfaces and the high-speed Aurora debug interface. They include a 64-bit DDR3 and DDR3L (low power) DRAM interface with 8-bit ECC support running at up to 1333 MT/s data rate. It includes two USB 2.0 interfaces (including PHY), two DUARTs, an SD/MMC interface, a 32-bit local bus, four I2C and SPI. Both processors also include the accelerator blocks collectively known as the Data Path Acceleration Architecture (DPAA) that offload packet handling, pattern matching and security algorithm calculation from the core as well as support for RAID 5/6 hardware assist. The P5020DS has significant flexibility in allocation of its 18 SerDes lanes to various functions. Its base configuration supports two RGMII ports, two PCI Express x2 slots (two lanes to each slot), 4 x 4 slots for the optional Freescale SGMII-PEX-RISER, a 2 x 4 slot for the optional Freescale XAUI-RISER, the Aurora high-speed debug port and two SATA ports. It can also be configured to support one PCI Express slot of widths up to x8 (at 2.5 Gb/s). The dual memory controllers of the P5020DS support 4 GB of DDR3 at 1333 MT/s. It has 128 MB of NOR flash, 1 GB NAND flash, 256 KB IC EEPROM and two SPI memories: 16 MB flash and 128 KB EEPROM. It also has two USB 2.0 receptacles and an SD card slot. The P5020DS is pre-loaded with a software development kit with support for DPAA, including SMP Linux(R) kernel, Hugetlbfs for applications with a large memory footprint, user space DPAA for high-performance packet handling, u-boot and a GCC toolchain. QorIQ P5020DS Board Features USB 2.0 * Two Full-Speed USB controllers Processor * One Type A and one MicroAB receptacle * P5020, 2.0 GHz core with 1333 MT/s DDR3 data rate Ethernet * Multiple SysClk inputs for generating * Support two 10/100/1000 ports with no various device frequencies add-in cards * dTSEC4 and dTSEC5 as RGMII to Vitesse Memory VSC8244 PHY * Dual unbuffered DDR3 240-pin uDIMM modules with ECC (72-bit bus), 4 GB * Optional SGMII-PEX-RISER expands memory, 1333 MT/s data rate 10/100/1000 port count to five * 128 MB NOR flash * 10 GE supported with optional XAUI-RISER card * 1 GB NAND flash * SPI-based 128 MB flash DUART * SPI-based 128 KB EEPROM * Two DUARTs * SD connector to interface with an SD Debug memory card * JTAG/COP PCI Express * Aurora high-speed connector * Two x2 PCI Express slots * Can support the Freescale XAUI-RISER and SGMII-PEX-RISER option cards Other * IEEE(R) 1588 connector for Symmetricom option card SATA * Temperature sensor * Two vertical SATA connectors * Eight general-purpose I/Os QorIQ P5020DS Block Diagram P5020DS Block Diagram JTAG Board Control: Switches, RST Cntr., etc. ATX PS Control P3041 P4080 Set Secondary PS 16-bit NOR Flash 16-bit NAND Flash 8-bit Bank1: 2,3 3 Flash/RCW, RTC/PWR CNTR/Therm. Monitor, etc. DDR3 uDIMM DDR3 uDIMM x2 Bank1: 0,1 DDR3 Regulator 1.5 V/1.35 V PromJet Emulator DDR3 Cntr. #2 DDR3 Cntr. #1 VDD_CB Regulator 72 V/1.35 V 8-bit I2C P5020 VDD_CA and VDD_PL VID Controlled Regulators .5 V/1.6 V, 60 Amp System Control Logic FPGA COP Legacy Conn. P5040 Four Power Pools Supported by Four Independent Programmable Regulators x2 PEX#1 x2/x4/x8 or SRIO2 x4 SLOT7 PEX#1 x2 SLOT4 Local Bus 16/8-bit SPI Flash SPI 4/8-bit SD/MMC MMC Bank1: 4,5 USB x2 USB 2.0 Bank1: 6,7 x2 10/100/1G RGMII SYS/PEX Clocks SLOT1 3 x2 SGMII [1:4] or XAUI #1/#2 or SGMII #5 x2 SATA 1/2 P4080 (Expedition) Compatible Bank1: 8 DUART x2 Bank3: 14,15 Bank3: 16,17 Bank1: 9 Bank2: 10-13 x2 x2 x2 x1 x4 PEX#2 x2/x4/ or SRIO1 x4 or SRIO2 x2 or SGMII [1:2] SLOT6 or SGMII [1:4] SRIO1 x2 or SGMII [3:4] SLOT5 PEX#4 x1 or PEX#2 x1 or SLOT3 SGMII [3, 8] or SGMII [7:8] Aurora PEX#3 x1/x4 or SGMII [1:4] SLOT2 or XAUI #1 Bank4: 18,19 P5020 (Super Hydra) Update For more information, visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) 2012, 2013 Freescale Semiconductor, Inc. Document Number: P5020DSFS REV 1