ANALOG DEVICES FEATURES Three-State Latched Output Continuous Tracking Even During Data Transfer Simple Data Transfer Facility Low Profile 0.35" (8.9mm) internal Transformers for 6(0Hz, 400Hz and 2.6kHz References Signal and Reference Voltage Scaling with External Resistors High Tracking Rates (50 revs/sec) Lightweight 3.3 oz. (93 gms) MIL Spec/Hi Rel Options Available APPLICATIONS Servo Mechanisms Retransmission Systems Coordinate Conversion Antenna Monitoring Simulators Industrial Controls Artillery Fire Control Systems Machine Tool Control Systems GENERAL DESCRIPTION The SDC1725 and $DC1726 are modular, continuous tracking Synchro/Resolver to Digital Converters which employ a type 2 servo loop and contain three-state latches on the digital outputs. The input signals can be either 3 wire synchro plus reference or 4 wire resolver plus reference depending on the option. The outputs will be presented in TTL compatible parallel natural binary, buffered by three-state latches. The three-state output facility not only simplifies multiplexing of more than one device onto a single data bus but also enables the INHIBIT to be used without opening the internal con- verter loop. Another outstanding feature of these converters is the use of precision Scott T and reference microtransformers. This has made it possible to include internal transformers, even on the 60Hz options, and yet obtain a profile height lower than any other modular Synchro/Resolver to Digital converter cur- rently available. NOTE No external transformers are required with these converters. Ultra-Low Profile (0.35) Three-State Latched Output Synchro to Digital Converters MODELS AVAILABLE The two Synchro/Resolver to Digital Converters described in this data sheet differ primarily in the areas of resolution and accuracy as follows: Model SDC1725XYZ is a 12-bit converter with an overall ac- curacy of +3.2 arc-minutes +1LSB and a resolution of 5.3 arc-minutes. Model SDC1726XYZ is a 10-bit converter with an overall ac- curacy of 22 arc-minutes and a resolution of 21 arc-minutes. The XYZ code defines the option as follows: (X) signifies the operating temperature range, (Y) signifies the reference fre- quency, (Z) signifies the signal and reference voltage and whether it will accept synchro or resolver format. More information about the option code is given under the heading of Ordering Information. S/D AND D/S CONVERTERS 2838SSPECIFICATIONS (typical at +25C unless otherwise stated) Models $DC1725 SDC1726 ACCURACY! (max Error all Options) RESOLUTION 3.2 arc-minutes 1LSB 12 Bits +22 arc-minutes 10 Bits OUTPUT 12-Bits Parallel Natural Binary 10-Bits Parallel Natural Binary SIGNAL AND REFERENCE FREQUENCY 60Hz, 400Hz, 2.6kHz * SIGNAL VOLTAGE (Line to Line) Low Level. 1L.8V rms * High Level 90.0V rms * SIGNAL IMPEDANCES Low Level 26kQ. Resistive * High Level 200kQ Resistive * REFERENCE VOLTAGE Low Level 26V rms (11.8V Signal) * High Level 115V rms (90.0V Signal) * REFERENCE IMPEDANCE Low Level 56kQ (26V Reference) * High Level 270kQ. (115V Reference) * (Impedance is Resistive) * TRANSFORMER ISOLATION 500V de * TRACKING RATE (Minimum) 60Hz Options 400Hz Options 2.6kHz Options 5 Revolutions Per Second 36 Revolutions Per Second 50 Revolutions Per Second ACCELERATION Constant K, 60Hz Options 2000/sec? * 400Hz Options 120,000/sec? * 2.6kHz Options 600,000/sec? " STEP RESPONSE (179 Step) (For 1LSB Error) 60Hz Options 1.5sec * 400Hz Options 175ms * 2.6kHz Options 50ms * POWER LINES +15V @ 25mA * ~15V @ 25mA * +V @ 120mA * POWER DISSIPATION 1.35 Watts * DATA LOGIC OUTPUTS? (TTL Compatible) 67TL Loads All Options * BUSY LOGIC OUTPUT LOADING? 2TTL Loads * BUSY LOGIC OUTPUT WIDTH? 320ns max * INHIBIT INPUT (TO INHIBIT) Logic 0 1 TTL Load ENABLE INPUT (TO ENABLE) Lagic 0 1 TTL Load WARM UP TIME TEMPERATURE RANGE 1sec to Rated Accuracy Operating 0 to +70C Standard . ~55C to +105C Extended * Storage -55C to +125C DIMENSIONS 3.125" X 2.625" X 0.35" * (79.4 X 66.7 X 8.9mm) * WEIGHT 3.3 ozs (93 gms) * Specifications the same as for SDC1725. NOTES * Specified over the appropriate operating temperature range and for: (a) +10% signal and reference amplitude variation; (b) 10% signal and reference harmonic distortion; (c) 5% power supply variation; and (d) +10% variation in reference frequency. 7 Schottky logic loading rules apply. Specifications subject to change without notice. 284S S/D AND D/S CONVERTERSTHEORY OF OPERATION If the unit is a Synchro to Digital Converter the 3 wire synchro output will be connected to S1, $2 and $3 on the module and the Scott T transformer pair will convert these signals into resolver format. ie., Vy =K Eo Sin wt Sin @ V2 = K Eg Sin wt Cos 0 Where @ is the angle of the synchro shaft. If the unit is a Resolver to Digital Converter, the 4 wire re- solver output will be connected to $1, $2, $3 and $4 on the module and the microtransformers will act purely as isolators. To understand the conversion process, assume that the current word state of the up-down counter is @. Then V, is multiplied by Cos @ and V9 is multiplied by Sin to give: K Eo Sin wt Sin @ Cos and K Eg Sin wt Cos 8 Sin These signals are subtracted by the error arnplifier to give: K Ego Sin wt (Sin & Cos ~ Cos @ Sin ) or K Eo Sin wt Sin (6 - ) A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null Sin (6 - @). When this is accomplished, the word state of the up-down counter (#) equals, within the rated accuracy of the converter, the synchro shaft angle 0. Assuming that the INHIBIT is at a logic high state, then the digital word will be strobed into the latches 150ns after the up-down counter has been updated. If the three state EN- ABLE is at a logic low, then the digital output word will be presented to the output pins of the module. DATA TRANSFER Data transfer from the SDC1725 and SDC1726 is very straight- forward. Consider the timing sequence shown in the timing diagram which assumes that the input to the converter is changing. From this diagram, it can be seen that there are two ways to transfer data. One method is to detect the state of the BUSY signal, which is high for 330ns while the up-down counters and latches are settling, and transfer data when it is in a low state. However, a much more satisfactory method is to use the {NHIBIT input. As can be seen from the functional diagram application of the INHIBIT prevents the two monostables being triggered and consequently the latches being updated. Therefore, it follows that data will always be valid from 330ns after the INHIBIT has been taken to a logic low state. It can also be seen that this method of data transfer is valid regard- less of when the INHIBIT is applied. The three-state ENABLE can be used at any time in order to present the data in the latches to the output pins. A logic low on this pin will cause the data to be presented to the outputs. oo EES Note that the operation of the internal converter loop cannot be affected in any way by the logic state present on the INHIBIT and ENABLE pins. OISTANCE DEPENDS ON ~- VELOCITY OF INPUT ->- vco OUTPUT ROTATION {POINT "A" UP-DOWN ON piacraw) | fe COUNTER | | ; UPDATED ' bane 150ns ! LatcH crock ! ! (POINT B LATCHES ON DIAGRAM) UPDATED _ASSUMING 330ns ! INHIBIT = "1" Lage I BUSY | | | ' ' I \ DATA " VALID (HIGH STATE) S8SSSSOed Timing Diagram Bit Number Weight in Degrees 180.0000 90.0000 45.0000 22.5000 11.2500 5.6250 2.8125 1.4063 0.7031 10 (LSB - SDC1726) 0.3516 11 0.1758 12 (LSB - SDC1725) 0.0879 OeNA UMP wWN Bit Weight Table REF ~ Ain) Oa SIN (6 - ) A_ppO+4 micro. [Yt ERROR 1 S1O-Fel TRANS. ["] HIGH SPEED ave PHASE $2 FORMER DIGITAL SENSITIVE |} FREQUENCY, 83 O-p-emd v2 SIN/COS DETECTOR SHAPING tote [v4] MULTIPLIER (DIGITAL) UP-DOWN COUNTER LATCHES THREE-STATE OUTPUTS HIGH $_" A DYNAMIC | RANGE VCO; AO 330ns | . -o MONOSTABLE Busy 1500s MONOSTABLE oT ENABLE 6466666655668 i DIGITAL OUTPUT WORD Functional Diagram SDC 1725 CONNECTING THE CONVERTER The electrical connections to the converter are straightforward. The power lines, which must not be reversed, should be con- nected to the +15V, -15V and +5V' pins with the com- mon connection to the ground pin GND. It is suggested that a parallel combination of a 0.1yF and a 6.8uF capacitor is placed in each of the three positions from +15V to GND, from -15V to GND and from +5V to GND. The digital output is taken from pins: 1 through to 10 for the SDC1726 1 through to 12 for the SDC1725 Pin 1 represents the MSB in each case. S/D AND D/S CONVERTERS 2858The reference connections are made to Ry; and Ryo. The inputs of the converter can therefore be scaled as in the . . i elow. In the case of a Synchro the signals are connected to S1, diagram below oe Gg . : | . : $2 and S3 according to the following convention USING THE CONVERTERS WITH OTHER THAN THE Esi -53 = ERLO - RHI Sin wt Sin 8 SPECIFIED REFERENCE FREQUENCY Es3 -52 = ErLoRuI Sin wt Sin (6 + 120) A 60Hz converter can be used from 50Hz to 400Hz, anda Es2 - 51 = ERLO - RHI Sin wt Sin (8 + 240) 400Hz converter can be used from 400Hz up to 2.6kHz, but they will have the dynamic characteristics specified for the For a resolver, the signals are connected to S1, S2, S3 unit concerned. and S4 according to the following convention: R3 -sS3=E - Sin wt Sin @ one To Fs1 33 RLO - RHI . out oto sz spc INTHE CASE OF THE SIGNAL RESISTORS THE Egz - $4 = Erni - RLO Sin wt Cos 6 oth Losi cae eee ay masts casTagees 11.BV SIGNAL RESISTANCE VALUES. Taya an fa 26Vner 1N GENERAL A 1% RATIO ERROR WILL GIVE RISE. oe 99 46 " es eI . The BUSY, INHIBIT and ENABLE pins should be con- now, [tO TO AN EXTRA INACCURACY OF 17 ARC-MINUTES nected as described under the heading Data Transfer. REE obo Fit TO AN EXTRA INACCURACY OF 1.7 ARC-MINUTES. Re THE ABSOLUTE VALUE OF Ry IS NOT CRITICAL. RESISTIVE SCALING OF INPUTS tesa A feature of this range of converters is that the signal and reference inputs can be resistively scaled to accommodate any OUTLINE DIMENSIONS AND range of input signal and reference voltages. PIN CONNECTION DIAGRAM : : Dimensions shown in inches and (mm). This means that a standard converter can be used with a per- sonality card in systems where a wide range of input and ref- [+2625 (66.7) - 4 erence voltages are encountered. a . . . SDC1725 aan To calculate the values of the external scaling resistors in the + 1 | PINS 0.04 0.07 (10.16 x case of a Synchro Converter, add 1.11k per extra volt of lon 20.03) DIA. (1) BRASS HARD ~l- > * . . 2 {5.1) signal in series with S1", S2 and $3, and 2.2kQ per extra valt of reference in series with Ryy. oR RESOLVER EWAGLE ONLY (RDC} In the case of a Resolver to Digital Converter, add 2.22kQ in U ane series with S1 and S2 per extra volt of signal and 2.2kQ cs per extra volt of reference in series with Ry4;. <2 For example, assume that we have an 11.8V line to line, 26V 3.425 . : (79.4) reference Synchro Converter, and we wish to use it with a 60V line to line signal with a 115V reference. In each signal input line, the extra voltage capability required is: 60 - 11.8 = 48.2V Therefore each one of the three resistors needs to have a value of: TOP VIEW 48.2 X 1.11 = 53.5kQ 1 os 22 one NOTE Similarly the single resistor needed in series with Ry can be THE ABOVE DIAGRAM SHOWS THE CONNECTIONS Fon THe calculated as being 195.8kQ. ANO PIN TONS THE LSS. ORDERING INFORMATION When ordering, the converter part numbers should be suffixed by an option code in order to fully define them. All the stand- ard options and their option codes are shown below. For op- tions not shown, please consult the factory. Part Number Resolution Operating Temp. Range L to L Voltage/Format Ref. Voltage _ Ref. Freq. SDC1725511 12 Bits 0 to +70C 11.8V Synchro 26 Volts 400Hz SDC1725611 12 Bits -55C to +105C 11.8V Synchro 26 Volts 400Hz SDC1725512 12 Bits 0 to +70C 90.0V Synchro 115 Volts 400Hz $DC1725612 12 Bits -55C to +105C 90.0V Synchro 115 Volts 400Hz RDC1725518 12 Bits 0 to +70C 11.8V Resolver 26 Volts 400Hz RDC1725618 12 Bits -55C to +105C 11.8V Resolver 26 Volts 400Hz SDC1725522 12 Bits 0 to +70C 90.0V Synchro 115 Volts 60Hz $DC1725622 12 Bits -55C to +105C 90.0V Synchro 115 Volts 60Hz $DC1725541 12 Bits 0 to +70C 11.8V Synchro 26 Volts 2.6kHz $DC1725641 12 Bits -55C to +105C 11.8V Synchro 26 Volts 2.6kHz RDC1725548 12 Bits 0 to +70C 11.8V Resolver 26 Volts 2.6kHz RDC1725648 12 Bits -55C to +105C 11.8V Resolver 26 Volts 2.6kHz Note For 10-bit resolution, substitute 1726 in place of 1725 in the part number above. 286S S/D AND D/S CONVERTERS